TW409393B - Semiconductor device and the manufacture method thereof - Google Patents
Semiconductor device and the manufacture method thereof Download PDFInfo
- Publication number
- TW409393B TW409393B TW087101324A TW87101324A TW409393B TW 409393 B TW409393 B TW 409393B TW 087101324 A TW087101324 A TW 087101324A TW 87101324 A TW87101324 A TW 87101324A TW 409393 B TW409393 B TW 409393B
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- Taiwan
- Prior art keywords
- lead
- semiconductor wafer
- semiconductor device
- wafer
- main surface
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 290
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
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- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 2
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- 229910000679 solder Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
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- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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Classifications
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Description
40939¾ at ____B7__ 五、發明說明(1 ) 〔發明之背景〕 <請先閲讀背面之注意事項再填窝本頁) 本發明係爲關於半導體裝置及其製造方法,特別是關 於對表面實裝型封裝體的薄型化爲有效之技術。 • 近年,工程技術終端站或個人電腦,爲了高速處理小 型且大量的資料所以必要大容量的記憶體,因此檢討表面 實裝型封裝體的積層化技術。 由於此樣的積層必須是各個表面實裝型封裝體的薄型 化,因而開發種種的薄型封裝體。 例如在日本專利5 _ 1 7 5 4 0 6號公報,具有被配 置在引線框架的晶片搭載部(晶片座)上之半導體晶片· 及被配置在上述半導體晶片的周圍之複數個引線,及封裝 上述半導體晶片與上述複數個引線的內引線部的樹脂封裝 體之 T S Ο P ( Thin Small Outline Package ),T S 0 J (Thin Small Outline J-lead Package)等的薄型封裝體已 被提案。 經濟部智慧財產局員工消費合作社印製 另外,在表面實裝型封裝體的一種具有LOC (Lead On Chip)構造的封裝體*此封裝體,係爲介由絕緣薄片在 半導體晶片的主面(元件形成面)上配置內引線之一部分 :以接合導線導電連接此內引線的前端部與半導體晶片的 接合用電極;以樹脂封裝上述半導體晶片,內引線部,絕 緣薄片及接合導線之構造。上述絕緣薄片,·係爲以聚醯亞 胺的耐熱性樹脂所構成的基部軟片,及被形成在該兩面的 接著劑而被構成。具有此種的L Ο C構造之封裝體,例如 在USA NO.5234866號公報已被提案。 -4- 本紙張尺度適用中國國家標準(CNS)A4規格(210 x297公Μ > 經濟部智慧財產局員工消费合作社印製 A7 40939.Ί_B7 __ 五、發明說明(2 ) 本發明者,針對上述表面實裝型封裝體的筻薄性化’ 高信賴性作檢討,其結果如後述。 上述T S 0 P等的薄型封裝體,爲了防止線配向所造 •成接合導線間的短路,半導體晶片的偏位所造成的外觀不 良,所以具有在於樹脂封裝過程等的製造過程,爲了將上 述半導體晶片支撐或是固定在所定位置之支撐引線及與上 述支撐引線一體形成的晶片搭載部(晶片座)。此晶片搭 載部因被配置在半導體晶片的背面側,所以相當於上述晶 片搭載部的厚度之分量,增厚了表面實裝型封裝體.。 因此,高信賴度且薄型化的表面實裝型封裝體之供給 爲困難β 另外,前述過L 0 C構造的封裝體,沒有上述 T S Ο Ρ的晶片搭載部,其構造上,因引線重疊在半導體 晶片的主面上,所以相當於上述引線的厚度之分量,增厚 了表面封裝型封裝體。進而,由於介隔在上述半導體晶片 與內引線部之間之絕緣薄片的基部軟片,例如具有厚度 5 0 i/m程度的膜厚,所以此膜厚形成爲妨礙封裝體的薄 型化之因素》 進而,因在上述絕緣薄片的厚度,加算接著線的回路 高度,所以增厚了表面實裝型封裝體。 另外,當使用此L 0 C構造的封裝體而製造積層型記 億模組的情況,也是以上述同樣的理由,造成將記憶模組 薄型化時的障礙‘。 進而’上述基部軟片,由於占據封裝體中的面積較大 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------I丨-:—卜裝1_ (請先閱讀背面之注意事項再填寫本頁) • I6· A7 ___B7_____ 五、發明說明(3 ) ,所以會有因該基部軟片吸濕封裝樹脂中的水分而在封裝 樹脂產生龜裂之疑慮》 另外,期待半導體裝置的價格降低,但前述絕緣薄片 •一般性爲高價,而成爲使其上昇半導體裝置的價格之要因 e 本發明的目的係爲提供推進表面實裝型封裝體的薄型 化之技術。 本發明的其他目的係爲提供降低表面實裝型封裝體的 製造成本之技術。 本發明的其他目的係爲提供使其提高表面實裝型封裝 體的信賴性及製造良品率之技術。 本發明的其他目的係爲提供使用表面實裝型封裝體之 積層型記憶模組的薄型化之技術。 本發明的其他目的係爲推進搭載表面實裝型封裝體的 I C卡薄型化之技術。 本發明的代表性槪要,如下述。 本發明的半導體裝置|係爲具有在其主面形成接合用 電極之半導體晶片:及 各個具有內引線,外引線之複數個引線;及 晶片支撐引線;及 連接前述內引線的前端部與前述接合用電極之接合導 線;及 封裝前述半導體晶片,前述內引線,前述接合導線與 前述晶片支撐引線之樹脂封裝體; -------L 裝 i I (諳先閲讀背面之庄意事項再填寫本頁) _ · 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) -6 - 4〇9393 at B7 五、發明說明(4 ) 前述內引線的前端部,係爲被配置在前述半導體晶片 的外周,且在於前述半導體晶片的厚度方向,位於前述半 導體晶片的厚度內; • 前述外引線部從前述樹脂封裝部的側面朝外方延伸; 前述晶片支撐引線的一部分被配置在前述半導體晶片 的主面上,且介由接著劑而被接著在前述半導體晶片的主 面。 另外,本發明的半導體裝置,係爲具有形成複數個配 線之實裝基板:及 被配置在前述實裝基板上之第1表面實裝型封裝體及 被積層在上述第1表面實裝型封裝體上之第2表面實 裝型封裝體; 前述第1及第2表面實裝型封裝體,係爲具有在其主 面形成接合用電極之半導體晶片;及 各個具有內引線,外引線之複數個引線:及 晶片支撐引線:及 連接前述內引線的前端部與前述接合用電極之接著線 ;及 封裝前述半導體晶片,前述內引線’前述接著線及前 述晶片支撐引線之樹脂封裝體: 前述內引線部的前端部,係爲被配置在前述半導體晶 片的外周,且在於前述半導體晶片的厚度方向,位於前述 半導體晶片的厚度內; · 前述外引線部從前述樹脂封裝體的側面朝外方延伸: 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公爱) . C ------------丨-裝— (請先閲讀背面之ii意事項再填寫本頁) 訂· 經濟部智慧財產局BK工消費合作社印製 409393 A7 B7 五、發明說明(5 ) 前述晶片支撐引線的一部分被配置在前述半導體晶片 的上面上,且介由接著劑而被接著在前述半導體晶片的上 面: 前述第1及第2表面實裝型封裝體的所對應的外引線 被導電連接。 另外,本發明半導體裝置之製造方法:係爲含有以下 的過程β (a )預備在其主面形成接合用電極的半導體晶片之 過程:及 (b )具有外框,及各個具有內引線,外引線之複數 個引線,及晶片支撐引線之引線框架;預備前述複數個引 線及前述晶片支撐引線,與前述外框一體形成的引線框架 之過程;及 (c) 將前述內引線的前端部配置在前述半導體晶片 的外周,且在於前述半導體晶片的厚度方向,將前述內引 線的前端部配置在前述半導體晶片的厚度內,且將前述晶 片支撐引線的一部分配置在前述半導體晶片的主面上之過 程:及 (d) 介由接著劑而將前述晶片支撐引線的一部分接 著在前述半導體#片的主面之過程:及 (e) 以接著線連接前述內引線的前端部與外部接合 用電極之過程,及 (f )以樹脂封裝體封裝前述半導體晶片,前述內引 線,前述接著線及前述晶片支撐引線的一部分之過程’及 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) • - C ------------k 裝 i — (諳先閱讀背面之注*事項再填寫本頁) -6J. 經濟部智慧財產局員工消費合作社印製 -8- A7 B7 409393 五、發明說明(6 ) (g.)在於前述樹脂封裝體與前述引線框架的外框間 ,切斷前述晶片支撐引線之過程。 (锖先閱讀背面之注意事項再填窵本頁) 進而具體上: (1 )本發明的半導體裝置,係爲具有在其主面形成 接合用電極之半導體晶片;及以內引線部,外引線部與支 撐引線部所形成之引線;及封裝半導體晶片,內引線部與 支撐引線部之封裝本體;內引線部被配置在半導體晶片的 外周,同時介由導線被連接至接合用電極;外引線部從封 裝體本體的側面朝外方延伸之半導體裝置:支撐引線部* 係爲被封裝在封裝體本體,同時其一部分不含基部軟片, 介由非導電性接著劑而被配置在半導體晶片的主面上。 依據此樣的半導體裝置,由於形成爲半導體晶片被披 著在支撐引線部之構造,所以可以廢止爲了固定突起型或 是島型等的半導體晶片之基體,且可以省略在此樣的基體 所佔有的厚度分量而將半導體裝置的封裝體。 經濟部智慧財產局員工消費合作社印製 另外,由於形成爲不含基部軟片,以非導電性接著劑 半導體晶片被披著在支撐引線部之構造,所以省略基部軟 片分的厚度;可以將半引線的封裝體薄型化,同時抑制基 部軟片所起因的吸濕,且可以提高模塑樹脂的耐流動性而 提高半導體裝置的信賴性。 進而,由於不使用高價的基部軟片,因而可以降低半 導體裝置的價格。 另外,本發明的半導體裝置,係爲半導體晶片的主面 側之支撐引線部高度,不超過導線的最大高度。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 一 409393 五、發明說明(7 ) 依據此樣的半導體裝置,形成爲只以導線的最大高度 決定半引線主面側的模塑樹脂之必要厚度,不必要考慮支 撐引線部的厚度》 • 進而,本發明的半導體裝置I係爲內引線部表面之導 線連接點,不超過半導體晶片厚度方向之半導體晶片主面 的高度,或者是至少連接導線之內引線部的下面,被配置 在比半導體晶片的主面還下側。 依據此樣的半導體裝置,內引線部表面之導線的連接 點’由於不超過半導體晶片的厚度方向之半導體晶片主面‘ 的高度,或者是由於被設置在比半導體晶片的厚度與內引 線部的厚度之合計厚度還低的位置,所以可以降低導線的 高度。如上述,本發明的半導體裝置,由於導線的最大高 度而規定半導體晶片主面側之模塑樹脂的必要厚度,因此 由於減低導線的高度,所以能達到半導體裝置的薄型化。 然而,可以以此樣的構造,係爲將內引線部配置在半 導體晶片的周邊,而可以實現。 經濟部智慧財產局員工消t合作社印装 fv J ----- ------— II 裝 i — {請先ra讀背面之注意事項再填寫本頁) (2 )本發明的半導體裝置,係爲具有在其主面形成 接合用電極之半導體晶片:以內引線部,外引線部與支撐 引線部所形成之引線;及封裝半導體晶片,內引線部與支 撐引線部之封裝體本體:內引線部被配置在半導體晶片的 主面上’同時被連接至接合用電極,外引線部從封裝體本 體的側面朝外方延伸之半導體裝置:支撐引線部,係爲被 封裝在封裝體本體,同時其一部分不含基部軟片,介由非 導電性接著劑而被配置在半導體晶片的主面上。 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) -10- 谢393 A7 B7 五、發明說明(8 ) (諳先閲讀資面之注意事項再填寫本頁) 此樣的半導體裝置,內引線部並不是半導It晶片的周 邊,在被配置在主面上之點,與前述(1 )所記載的半導 體裝置相異;只內引線部的厚度分,對半導體裝置的薄型 •化爲不利,但當接合用電極被配置在半導體晶片的中央部 之情況也能對應。. 另外,由於半導體晶片形成爲被披著在支撐引線部之 構造,因而可以廢止爲了固定突起型或是島型等的半_導體 晶片之基體,且可以省略佔據此樣基體的厚度分量而將半 導體裝置的封裝體薄型化,形成爲不含基部軟片,以非導 電性接著劑而半導體晶片被披著在支撐引線部之構造,所 以可以省略基部軟片分量的厚度,將半導體裝置的封裝體 薄型化,同時抑制基部軟片所起因的吸濕,可以提高模塑 樹脂的耐流動性而提高半導體裝置的信賴性•由於不使用 高價的基部軟片因而可以降低半導體裝置的價格;以上所 述與前述(1 )所記載的半導體裝置同樣。 然而,在本發明的半導體裝置,內引線部及接合用電 極,可以介由導線或是觸動電極而連接。 經濟部智慧財產局員工消費合作社印製 (3 )本發明的半導體裝置,係爲前述(1 )或是( 2 )所記載之半導體裝置;支撐引線部的至少1種,係爲 不與內引線部導電連接之獨立的引線部,或者是支撐引線 部的至少另一種,係爲在於封裝體本體內從內引線部分歧 的引線部。 將支撐引線部設爲不與內引線部導電連接之獨立的引 線部之情況,由於可以從支撐引線部使其獨立傳送電訊之 -11 - 本紙張尺度適用辛國國家標準(CNS)A4規格(210 * 297公釐) 409393 A7 B7 五、發明說明(9 ) <靖先閲讀背面之注*事項再填寫本頁) 內引線部,所以可以降低該內引線部的浮動容量,形成爲 能使用於傳送高速的訊號。另外,將支撐引線部設爲從內 引線部分歧的引線部之情況,可以在任意的位置設置支撐 •引線部,且可以增加引線設計的自由度。 (4) 本發明昀半導體裝置,係爲前述(1)〜(3 )所記載之半導體裝置:非導電性接著劑,係爲至少其一 部分被形成在半導體晶片的主面端部。 依據此樣的半導體裝置,由於非導電性接著劑被形成 在半導體晶片的主面端部,所以可以防止半導體晶片端部 之半引線基板與引線的短路不良。即是在半導體晶片的表 面通常被形成有鈍化等的絕緣性保護膜,但在其端部,爲 了防止在裁切過程裁斷成半導體晶片時損傷絕緣性保護膜 ,所以未設置絕緣性保護膜。在本發明的半導體裝置,由 於不含基部軟片以絕緣性接著劑接著支撐引線部與半導體 晶片之間所以其間隔非常的狹窄,但在這樣的情況由於也 在半導體晶片的主面端部形成絕緣性接著劑,所以半引線 基板與支撐引線部不致短路。 經濟部智慧財產局具工消费合作社印製 (5) 本發明的半導體裝置,係爲前述(1)〜(4 )所記載之半導體裝置:非導電性接著劑,係爲在半導體 晶片的主面與支撐引線部之間的領域,隔著所定的間隔而 形成複數個。 依據此樣的半導體裝置,非導電性接著劑並不是一面 —樣的被形成在半導體晶片的主面與支撐引線部之間的領 域,由於是隔著所定的間隔而形成複數個,所以減少非導 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) -12- 409393 a: B7 五、發明說明(10 ) (請先閲讀背面之注意事項再填寫本頁) 電性接著劑的使用量:另外,在於非導電性接著劑的塗敷 過程,可以縮短過程時間而使過程合理化。塗敷量的減少 及塗敷時間的合理化,不只降低半導體裝置的製造成本, -且可以達到降低因減少塗敷量所造成非導電性接著劑的吸 濕量,提高半導體裝置的耐流動性及信賴性》 (6)本發明的半導體裝置,係爲前述(1 )〜(5 )所記載之半導體裝置:外引線部,爲能表面實裝地被彎 曲:且在其一部分含有朝向與封裝體本體的上面或是底面 水平的方向延伸存在之延長部,或是在其一部分朝向封裝 體本體的斜上方延伸存在之延長部。 另外,本發明的半導體裝置,係爲在外引線部的幅寬 方向之兩側面,設置延伸存在於封裝體本體的上面方向之 一對阻隔構件;另外,外引線部的下端部之幅寬,比朝向 斜上方延伸存在之延長部的幅寬還窄:進而,一對的阻隔 構件,係爲彎曲連結引線框架的同類外引線部之壩型物。 經濟部智慧財產局員工消费合作社印製 依據此樣的半導體裝置,由於能表面實裝地彎曲外引 線’所以可以表面實裝,同時也能將半導體裝置積層化而 構成模組;可以達到搭載本發明半導體裝置之電子電路裝 置的小型化。 另外,由於彎曲外引線部而被形成,在其一部分設置 水平方向的延長部或是斜向的延長部,因而結果是可以增 加外引線部的長度所以以含有延長部之外引線部的全體 ’吸收與焊接所形成實裝後的熱膨脹係數不同的熱應力, 可以降低焊接部所加諸的應力。其結果,提高實裝後焊接 -13- 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) 409393 a? B7 五、發明說明(11 ) 的壽命,且可以提高搭載本發明的半導體裝置之電子電路 裝置的信賴性。 (請先閱讀背面之注意事項再填寫本頁) 進而,外引線部的延長部朝向封裝體本體的斜上方而 •延長存在;另外,在外引線部的幅寬方向之兩側面,設置 延長存在於外引線部的下端部方向之一對阻隔構件,進而 ,由於外引線部之下端部的幅寬,比朝向斜上方延伸存在 之延長部的幅寬還窄,所以積層半導體裝置而構成模組時 ,可以使其易於組裝。然而,一對的阻隔構件,由於是彎 曲連結引線框架的同類外引線部之壩型物而被形成,所以 能簡便地進行製造。 (7 )本發明的半引線模組,係爲具有朝印刷電路板 的上下方向積層複數個所前述過的半導體裝置後實裝的多 層晶片•模組構造。 依據此樣的半引線模組,由於是積層所被薄型化的半 導體裝置而構成,所以可以將模組全體薄型化|且可以提 高搭載半引線模組之電子電路裝置的實裝密度》 經濟部智慧財產局員工消t合作社印製 (8 )本發明的I C卡,係爲具有印刷電路基板,框 體,背向軟片;印刷電路基板與背向軟片之間的實裝空間 厚度爲0.56mm以下的IC卡:在實裝空間實裝前述 過的半導體裝置。 依據此樣的I C卡,由於使用前述過的半導體裝置, 所以可以在I C卡的實裝空間搭載半導體裝置。半導體裝 置,由於並不是裸晶片等未被模塑,以封裝體而被模塑, 所以可以防止污染,且是耐cr線性優良之I C卡。 -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 409393 a; __B7_ 五、發明說明(〗2) ί請先閱讀背面之汶意事項再填寫本頁) (9.)本發明的半導體裝置之製造方法,係爲前述( 2 )所記載半導體裝置之製造方法:利用治具將內引線部 壓著在半導體晶片的主面上,以導線接著連接內引線部與 •接合用電極;其後除去治具而使其浮起內引線部的導線連 接部’或是由於用晶片支撐台推上半導體晶片,因而使其 接觸或是近接半導體晶片的主面與內引線部的底面,以導 線接著連接內引線部與接合用電極,其後除去晶片支撐台 而使其隔間分離內引線部的底面與半導體晶片的主面。 依據此樣半導體裝置之製造方法,用治具將內引線部 壓著在半導體晶片的主面上,由於連接導線後,除去治具 使其浮起內引線部的導線連接部,或者是由於用晶片支撐 台推上半導體晶片,連接導線後,除去晶片支撐台而使其 隔間分離內引線部與半導體晶片,所以可以降低導線的最 高點,而達到半導體裝置的薄型化。 〔實施形態〕 以下,根據圖面詳細說明本發明的實施形態。 經濟部智慧財產局員工消費合作社印^ 實施形態1 第1圖係爲本實施形態1的半導體裝置之平面圖;第 2 (a)圖係爲沿著第1圖的Ha — na線之斷面圖;第 2 (b)圖係爲沿著第1圖的nb — Hb線之斷面圖。然 而,第1圖係爲爲了易於觀測封裝體的內部構造,省略封 裝體本體的一部分圖示。 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 * 297公31) 409393 a? B7 五、發明說明(13 ) (請先閱讀背面之;i意事項再填寫本頁) 本實施形態的半導體裝置,係爲表面實裝型L S I封 裝體的一種之 T S 0 J (Thin Small Outline J-lead Package ) ° 在以轉移·模塑法成形的環氧系樹脂所形成的封裝體 本體1的內部’封裝形成DRAM (Dyicamic Random Access Memory )等的記憶體L S I之單結晶矽的半導體晶 片2。在半導體晶片2的周邊,配置構成T S 0 J的外部 連接端子之複數條引線5的內引線部5 A ;介由A u導線 7而與被形成在半導體晶片2的主面周邊部之接合用電極 8導電連接。另外,在半導體晶片2的主面上,配置複數 條引線5的支撐引線5 C。引線5係爲以C u或是F e系 合金等所形成。_ 支撐引線部5 C,具有從內引線部5A分歧設置( 經濟部智慧財產局員工消費合作社印製 5C — 1),及與內引線部5A爲獨立設置(5C-2) 。從內引線部5A分歧之支撐引線5C—1 ,具有配合內 引線部5 A的配置而能配置在任意位置之設計的自由度, 但與內引線部5 A爲獨立設置的支撐引線部5 C — 2係爲 能作爲大型的引線且可以是良好的半導體晶片2的保持特 性。另則,設置從內引線部5 A分歧的支撐引線部5 C — 1則支撐引線部5 C - 1所形成的浮游容量被附加壓內引 線部5 A,所以設在傳送高速訊號的端子較爲理想。在與 內引線部5A爲獨立設置的支撐引線部5 C — 2沒有此樣 的不良點。然而,在本實施形態1,表示設置上述支撐引 線部5C— 1,5C — 2的兩方之例,但只設匱任何—方 -16- 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) 409393 A7 _B7_.____ 五、發明說明(14 ) (請先閱讀背面之注意事項再填寫本頁) 的支撐引線部5 C亦可。在第2 ( a )圖表示含有支撐引 線部5 C_ 1之斷面圖;在第2 ( b )圖表示含有支撐引 線部5C—2之斷面圖。 如第2 (a)圖及第2 (b)圖所示,引線5的支撐 引線部5 C及半導體晶片2,係爲以非導電性的接著劑6 而被接著。即是此丁SOJ ,係爲在支撐引線部5C與半 導體晶片2之間不設置具有基部軟片之厚絕緣薄片|只以 接著線6接著兩者。接著線6例如是以熱可塑性的聚醯亞 胺樹脂所形成。 經濟部智慧財產局員工消f合作社印製 上述引線5的外引線部5 Β,係爲從封裝體本體1之 長邊方向的兩側面朝外方延伸存在。如第2 ( a )圖所示 ,外引線部5 B,係爲以從封裝體本體1的厚度方向(上 下方向)的幾乎中間部朝水平方向延伸存在之部分(5 B 一 a),及朝向斜上方延伸存在之延長部(5B_b), 及朝垂直方向延伸存在之部分(5 B - c),及所半圓狀 彎曲之前端部分等而被構成,全體上被成形爲J彎曲狀a 因此,外引線部5 B,係爲設置朝向斜上方延伸存在之延 長部(5B — b)的分量,比通常J SOJ的外引線部還 增長全長。 在第3圖表示沿著上述T S O J的厚度方向之各部尺 寸的一例。封裝體本體的下面至半導體晶片2的下面爲止 之樹脂厚度(ATa )爲0 . lmm :半導體晶片2之厚 度(ATc )爲0 . 2mm ;從半導體晶片2的上面至封 裝體本體1的上面之樹脂厚度(^Tb )爲0 · 2mm。 -17- 本纸張尺度適用中國國家標準(CNS)A4規格<210 * 297公釐) 409393 A7 ____B7___ 五、發明說明(15 ) <靖先閱讀背面之注意事項再填寫本頁) 因此,封裝體本體1之厚度形成爲Ο . 5mm。另外,引 線5的板厚爲0 _ 7〜0 · 125mm:接著劑6的膜厚 爲0 . 0 lmm :封裝體本體1的下面與外引線部5 B的 -下端部之空間(AS)爲〇 . 〇3mm» 此樣,封裝體本體1的厚度可以薄至0 . 5mm,係 爲支撐引線部5 C的高度,比A u導線7的最大高度還低 偏差Ad 1之故,進而,在內引線部5A連接Au導線7 之部分的位置,也就是內引線部5 A的上面,係爲比半導 體晶片2的主面還低偏差Ad 2之故。也就是以A u導線 7的最大高度,決定半導體晶片2的上面至封裝體本體1 的上面之樹脂高度(ΛΤ);Au導線7的最大高度,由 於是比半導體晶片2的主面位置還低,因而可以減低支撐 引線部5 C的高度之故= 經濟部智慧財產局員工消費合作社印製 然而,由於A u導線接著至內引線部5 A爲縫合接著 ,所以也有因選擇接著條件而能降低A u導線7的高度之 情況。因此,在本實施形態1,表示比半導體晶片2的主 面還降低設置內引線部5 A的表面之例,但並不拘限於此 例,如第3 ( b )圖所示,內引線部5 A的表面比半導體 晶片2的主面還高亦可, 在組裝本實施形態1的T S 0 J ,首先準備如第4圖 所示的引線框架L F。實際的引線框架L F,形成爲封裝 體5,6個分程度的多連構造,但在圖中表示封裝體1個 分的領域。 其次,在此引線框架L F之支撐引線部5 C的背面使 本紙張尺度通用中國國家標準(CNS>A4規格(210 * 297公釐) -18- 409393 A7 ____B7_ 五、發明說明(10 ) <請先閲讀背面之生意事項再填窝本頁) 用離心塗布機等塗敷接著劑6 <接著劑6,係爲如第5圖 所示’塗敷在被接著至各支撐引線部5 C背面的半導體晶 片2之領域全部亦可,但在本實施形態1,爲了削減接著 -劑6的使用量及塗敷時間,所以如第6圖所示,點狀地塗 敷至各支撐引線部5 C的2,3個處所。另外,取代使用 離心塗布機而塗敷接著劑之手段,將預先裁斷成微細的尺 寸之膜片狀接著劑設置在支撐引線部5 C的上面亦可. 其次’如第7及8圖所示,在半導體晶片2的主面上 定位支撐引線部5 C,以接著劑6接著雨者後,如第9及 1 0圖所示’在半導體晶片2的接合用電極8與內引線部 5 Α之間接著A u‘導線而導電連接兩者。 其次,如第1 1及1 2圖所示,以轉移•模塑法成形 封裝體本體1後封裝半導體晶片2。其後,切斷.除去露 到封裝體本體1外部之引線框架L F的外引線部5 B以外 之部分,繼而成形外引線部5 B,而完成前述第1 ,2圖 所示之T S 0 J · 經濟部智慧財產局員工消費合作社印製 第13圖係爲表示將本實施形態1的TSOJ實裝在 印刷電路板9的狀態之斷面圖β將此T S ◦ J實裝在印刷 電路板9,係爲預先將施予焊錫的外引線部5 Β定位在印 刷電路板9的電極1 0上。在電極1 〇的表面預先印刷糊 體錫;以該粘著力將外引線部5 Β假固定在電極1 0上= 或者是在電極1 0上定位外引線部5 Β後,進行預備加熱 而些微溶解外引線部5 Β的表面焊錫,進行假固定亦可。 另外,當將T S Ο J實裝在印刷電路板9的背面之情況, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) "19- 409393 A7 _B7__ 五、發明說明) 在印刷電路板9的背面及T S 0 J的背面塗敷假固定用樹 脂;加熱此假固定用樹脂而進行TSOJ的定位,固定。 其後,以此狀態浸鍍焊錫。然而,本實施形態的T S〇J •,係爲如第1 4圖所示,不改變外引線部5 B的形狀,同 時使其反轉封裝體本體1的上下面而能實裝。 依據本實施形態1的T S Ο J,在引線5的支撐引線 部5 C與半導體晶片2之間不介有基部薄片,只以接著劑 接著兩者,所以相當於基部薄片的膜厚之分量,可以將封 裝體本體1薄型化。另外,封裝體本體1的薄型化,係爲 將支撐引線部5 C的高度使其不超過A u導線7的最大高 度,或是比半導體晶片2的主面還降低內引線部5 A的表 面,而可以實現· 依據本實施形態的T S 0 J,由於比使用絕緣薄片的 T S 0 J還減少零件件數,所以可以降低製造成本。 依據本實施形態的T S 0 J,使其使用絕緣薄片的 TsoJ ·因在封裝體本體1的內部不封裝吸濕性較高的 基部軟片,所以當將T SO J實裝在印刷電路板時的熱所 形成的流動龜裂則不易產生。另外,如前述第6圖所示, 點狀塗敷接著劑6時,由於接著劑6的吸濕量也可以降低 ,所以更提高流動龜裂耐性。 依據本實施形態的T S 0 J ,由於在外引線部5 B設 置朝向斜上方延伸存在的延長部而增長其全長,因此在外 引線部5 B使其持有彈性。由於此因,以外引線部5 B的 彈性,吸收基板實裝時焊錫等的溫度循環所形成的應力, ------'——I!裝i — (請先IH讀背面之注意事項再填寫本頁) 打· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐> -20- 409393 A7 _B7__ 五、發明說明(18 ) 所以可以.防止在印刷電路板9的電極1 〇與外引線部5 B 的連接部產生焊錫龜裂的缺點。 (請先閱讀背面之注意事項再填寫本頁) •實施形態2 第1 5圖係爲本實施形態2的半導體裝置之斷面圖; 第1 6圖係爲擴大表示第1 5圖的一部分之斷面圖。 本實施形態2的TSOJ ,係爲將接合用電極5的支 撐引線部5 C與半導體晶片2之前述接著劑6的一部分, 配置在半導體晶片2的主面終端 如擴大表示第1 6圖所示,半導體晶片2的主面,通 常是以保護積體電路最終鈍化膜1 1或聚醯亞胺膜1 2所 披覆,在晶圓處理完了後,壓造晶圓而形成半導體晶片時 ,爲了防止在以氮化矽膜等所構成的最終鈍化膜1 1或α 線遮蔽用的聚醯亞胺膜12產生龜裂,所以在半導體晶片 2的主面端部不形成這些膜。 經濟部智慧財i局員工消費合作社印製 因此,削薄接著劑6的膜厚,則會有支撐引線部5 C 的下面與半導體晶片2的主面端部接觸而導致短路不良. 另外,由於在半導體晶片2的側面露出S i基板面,所以 會有因支撐引線部5 C的變形或封裝體內存在導電性異物 ,而支撐引線部5 C與半導體晶片2引起短路不良的疑慮 e 在該外,如本實施形態,由於以非導電性的接著劑披 覆半導體晶片2的主面端部*因而就是減薄接著劑6的膜 厚時,也能確實地防止支撐引線部5 C與半導體晶片2短 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -21 - 40939^ A7 B7 五、發明說明(19 ) 路之不良。 (請先閱讀背面之注意事項再填寫本頁) 實施形態3 第1 7圖係爲本實施形態3的半導體裝置之斜視圖: 第1 8圖係爲此半導體裝置之斷面圖。 本實施形態的TSOJ,係爲在朝向引線5之外引線 部5 B的斜上方延伸存在之延長部,設置從外引線5 B的 幅寬方向的兩側面朝向上方延伸存在之一對阻隔構件3, 3。此阻隔構件3係爲與引線5不同的材料構成亦可。具 體上,如第1 9 ( a )圖所示,在模塑封裝體本體1後引 線框架的裁斷過程將連接外引線部5 B同類之壩型體裁斷 成圖示的彤狀;其次如同圖(b )所示,將此形狀朝上彎 曲而形成阻隔構件3。 第2 0圖係爲例如將積層爲2段之本實施形態的 T S 0 J ,並列成2列實裝在印刷電路板9上之積層型記 億模組的斜視圖。 經濟部智慧財產局員工消費合作社印製 在組裝此積層型記憶模組,如第2 1圖所示,根據在 前述實施形態1所說明過的處理•而在印刷電路板9的電 極10上實裝第1TS0J後,在其上面互相重疊第2 TSOJ ,將第2TS0J之外引線部5B的下端定位於 第1 T S 0 J之外引線部5 B的上面。此時·,預先壓在第 2 T S 0 J之外引線部5 B的下端塗敷糊體錫,以其粘著 力假附著上下的外引線部5 B同類亦可. 本實施形態3的T S 0 J,係爲在外引線部5 B之寬 -22- 本纸張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) 經濟部智慧財產局員工消费合作社印製 40 咖 3 - 五、發明說明(2〇 ) 幅方向的兩側面設置前述過的一對阻隔構件3 ' 3,所以 利用此阻隔構件3,3作爲導引,因而可以將第2 T S 0 J之外引線部5 B的下端,正確且快速地定位在第 • 1 TSO J之外引線部5B的上面。此時,如第2 2圖所 示,由於比朝向斜上方延伸存在之部分的幅寬(Wb )還 窄的加工各外引線部5 B的下端即是彎曲成半圓狀之部分 的幅寬(Wd <Wd ),因而就是若干變形外引線部’5 B 的情況,也可以在阻隔構件3 | 3之間快速的插入外引線 部5 B的下端. 其後,將印刷電路板9置於托架而運送至爐內;由於 使其溶解披著在T S 0 J之外引線部5 B的表面之電鍍錫 ,所以分別連接•固定印刷電路板9的電極1 0與第1 T S 0 J的外引線部5 B,及上下的T S 0 J之外引線部 5 B同類。 上述第2TS0J的各外引線部5B,因被插入至設 在第1TS0J的外引線部5B之阻隔構件3,3之間, 所以將搭置印刷電路板9的托架運送至爐內之途中的振動 ,不會導致外引線部5 B沿著該幅寬方向(封裝體本體1 的長邊方向)偏位。另外,第2TS0 J之外引線部5 B 的下端,由於位於朝向第1 T S 0 J之外引線部5 B的斜 上方延伸存在之部分的上面,所以也防止沿著外引線部 5 B所延伸存在的方向(封裝體本體1的短邊方向)偏位 。然而,阻隔構件3,不必要設置在從封裝體本體1朝外 方延伸存在之全部的外引線部5 B,只設置在一部分的外 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -23- (請先閱讀背面之注意ί項再填苒本頁)
^〇S393 A7 B7 五、發明說明(21 ) 引線部5 B亦可。 (請先閲讀背面之注意事項再填寫本頁) 此樣’依據本實施形態3,在印刷電路板9上積層複 數個T S 0 J後組裝記憶模組時,可以高精度且迅速地連 接上下的T S ◦ J之外引線部5 B同類,所以可以使其提 高此模組的製造良咼率及產量。 另外,依據本實施形態3,由於使用薄型的T S 0 J ,因而可以推展積層型記憶模組的薄型化。 本實施形態3的TSOJ ,當然可以3層或是更多層 重疊而實裝·例如第2 3圖係爲在印刷電路板9上積層複 數個TSOJ ,以配置在其兩面側之一對印刷電路基板 1 3,導電連接TSOJ同類之積層型記憶模組的一例。 實施形態4 第2 4圖係爲本實施形態4的半導體裝置之平面圖; 第2 5圖係爲此半導體裝置之斷面圖。 經濟部智慧財產局員工消費合作社印製 本實施形態4的TSOJ .,係爲在半導體晶片2的主 面上配置引線5的內引線部5 A,介由配置在半導體晶片 的中央部之接合用電極8及A u導線7而導電連接。另外 ,引線5的支撐引線部5 C與半導體晶片2,係爲以非導 電性的接著劑6而被接著》 本實施形態4的T S 0 J ,由於與前述實施形態1〜 3的T S 0 J相異的內引線部5 A被配置在半導體晶片2 的主面上,所以在於減薄封裝體本體1的厚度之點稍微劣 化=但是,在本實施形態4 »在半導體晶片2的中央部配 -24 - 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) A7 409393 B7_ 五、發明說明(22 ) (請先閱讀背面之注意事項再填寫本頁) 置接合用電極8之構成也能對應。然而,半導體晶片2的 主面與內引線部5A的底面之空間約爲0.1mm.其他 構成則與實施形態1同樣。 本實施形態4的T S ◦ J之製造方法,係爲至半導體 晶片2接著至實施形態1的引線框架L F之過程(第7圖 ,第8圖)爲止爲同樣,但Au導線7的接著時,如第 2 6圖所示,以治具1 7 a壓著內引線部5 A ;在此狀態 ,可以進行A u導線7的接著。經此樣進行接著,則由於 壓著內引線部5 A,因而如圖示其先端朝下方降下,可以 縮短A u導線7的路徑。在進行A u導線7的接著後,若 除去治具1 7 a ,則以內引線部5 A的回彈力,而其前端 部形成爲恢復到原來高度,被設置在從半導體晶片2的主 面隔間分離之位置。 若以此方法進行導線接著,則以較短的路徑配置A u 導線7,所以可以降低回彈後A u導線7的高度。此結果 ,形成爲能減低封裝體本體1的厚度。 經濟部智慧財產局員工消费合作社印5取 另外,作爲本實施形態4之丁 S 0_ J的製造方法,也 可以例示以下的方法。即是如第2 7 ( a )圖所示,在晶 片支撐台1 7 b,與支撐引線部5 C的同時推起半導體晶 片2,在此狀態可以進行A u導線7的接著。此時支撐引 線部5 C及外引線部5 B的一部分變形。經此樣進行接著 ,則內引線部5 A的下面及半導體晶片2旳主面係爲平行 狀態的原樣接觸或是近接,不致損傷半導體晶片2的表面 。另外’縮短A u導線7的路徑係爲與前述的方法同樣。 本紙張尺度適用中國國家標準(CNS)A4規格<210*297公爱) -25- 409393 A7 ____B7_ 五、發明說明(23 ) (锖先閱讀背面之江意事項再填寫本頁) 在進行Au導線7的接著後,若降下晶片支撐台17b, 則如第2 7 ( b )圖所示’支撐引線部5 C及外引線部 5 B的變形則恢復到原狀;內引線部5 A形成爲被設置在 .從半導體晶片.2的主面所隔間分離之位置。 若以此樣的方法進行導線連接,則以較短的路徑配置 A u導線7,所以可以降低A u導線7的高度,同時可以 防止損傷半導體晶片2的表面。 這些的情況,也是如前述實施形態,由於以接著劑6 披覆半導體晶片2的主面端部,因而就是減薄接著劑6的 膜厚之情況,也能確實地防止支撐引線部5 C與半導體晶 片2短路的不良。另外,如前述實施形態3,由於在外引 線部5 B的延長部設置阻隔構件3 ’ 3,因而可以使其提 高積層型記憶模組的製造良品率及產量。 實施形態5 經濟部智慧財產局員工消费合作社印製 第2 8圖係爲本實施形態5的半導體裝置之斷面圖= 本實施形_態的TSOJ ,係爲在形成在半導體晶片2 的主面上之A u的觸動電極1 5上,導電連接引線5的內 引線部5 A。另外,引線5的支撐引線部5 C與半導體晶 片2 ·係爲以非導電性的接著劑6而被接著。 本實施形態的T S 0 J ,由於取代A u導線(7 ), 使用觸動電極1 5,因而可以比前述實施形態4的 TSO J還減薄半導體晶片2的上面至封裝體本體1的上 面之樹脂厚度,所以可以將封裝體本體1更薄型化。 本紙張尺度適用中國國家標準(CNS)A4規格(210 * 297公釐) -26- 409393 A7 _____B7___ 五、發明說明(24 ) (請先閱讀背面之注意事項再填寫本頁) 此情況,也是如前述實施形態2,由於以接著劑6披 覆半導體晶片2的主面端部|因而就是減薄接著劑6的膜 厚之情況,也能確實地防止支撐引線部5 C與半導體晶片 • 2短路之不良。另外,如前述實施形態3,由於在外引線 部5 B的延長部設置阻隔構件3,3,因而可以使其提高 積層型記憶模組的製造良品率及產量。 實施形態6 第2 9圖係爲本實施形態6的I C卡之斷面圖。 本實施形態6的1C卡,係爲在具有◦· 1mm厚度 的E卩刷電路板18,與具有0 . lmm厚度的背向軟片 1 9之間的實裝空間,實裝前述過實施形態1〜5的 T S 0 J。印刷電路板1 8與背向軟片1 9係爲以P V C 所形成的框體2 ◦支撐。在印刷電路板1 8被設有連接外 引線部5 B之電極2 1 :電極2 1係爲連接至印刷電路板 1 8的背面之接觸電極2 2。 經濟部智慧財產局員工消費合作社印製 因I C卡的實裝空間最大爲0 . 5 6mm,所以過去 不得不採用實裝裸晶片而進行導線接著之手段,或是進行 帶式搭載的實裝之手段,但在本實施形態,由於前述過 TSOJ的厚度爲0 . 5mm,所以就是0 . 56mm的 較小實裝空間也能搭載。由於此因,顯著容易操作實裝時 的半導體裝置,不僅可以將I C卡的組裝過程簡略化’由 於能使用所被樹脂模塑的半導體裝置,所以對於污染或是 α線也可以確保高信賴性,且可以提高I C卡的信賴性* 本纸張尺度適用争國國家標準(CNS)A4規格(210 X 297公釐〉 -27- 409393 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(25 ) 以上,根據前述實施形態具體說明過本發明者所提案 的發明,但本發明並不限於前述實施形態,只要不脫離本 要旨的範圍,種種變更皆爲可能。 例如,如第3 0.圖所示,由於在封裝體本體1的表面 ,設置鋁箔1 6的光反射層,就是以超薄型構成封裝體本 體1的情況,也可以防止光所形成資料反應等之特性劣化 。另外,引線5的外引線5 B,並不限於前述實施形態1 〜5的形狀,例如如第3 1圖所示的形狀等,種種的變形 皆可。另外,當然,如第31圖的情況設置阻隔構件3亦 可· 本發明並不限於T S 0 J型的封裝體,可以廣範適用 於L Ο C構造的封裝體。另外,也可以適用於在引線的內 引線部上配置半導體晶片之引線上晶片(Chip On Lead) 構造之封裝體。進而不止是封裝記憶體L S I之封裝體, 可以也適用於封微電腦或邏輯L S I之封裝體及用該封裝 體之積層型多晶片·模組。 S. 〔圖面之簡單說明〕 第1圖係爲表示本發明實施形態1的半導體裝置例之 平·面圖。 第2 圖;第2 面圖。 圖係爲沿著第 圖係爲沿著第 圖的Ε -Π 線之斷面 圖的nb-rtb圖線之斷 第3 (\ 圖係爲表示實施形態1的半引線尺寸之說
¾ 紙 平 四 2 格 規 ΜΝ. 公 97 28 (諝先閱讀背面之注意事項再填窝本頁) 409393 A7 B7_ 五、發明說明I) 明圖:第圖係爲表示實施形態1的半’導體裝置他 例之說明圖a ί諝先閲讀背面之汰$項再填寫本頁) 第4圖係爲表^本發明實施形態1的半導體裝置之製 •造方法之平面圖 第5圖係爲表示本發明實施形態1的半導體裝置之製 造方法之平面圖。 第6圖係爲表示本發明實施形態1的半導體裝置之製 造方法之平面圖。 第7圖係爲表示本發明實施形態1的半導體裝置之製 造方法之平面圖。 第8圖係爲表示本發明實施形態1的半導體裝置之製 造方法之斷面圖。 第9圖係爲表示本發明實施形態1的半導體裝置之製 造方法之平面圖。 第10圖係爲表示本發明實施形態1的半導體裝置之 製造方法之斷面圖。 第1 I圖係爲表示本發明實施形態1的半導體裝置之 製造方法之平面圖。 經濟部智慧財產局員工消費合作社印製 第12圖係爲表示本發明實施形態1的半導體裝置之 製造方法之斷面圖。 第13圖係爲表示本發明實施形態1的半導體裝置實 裝在印刷電路板的狀態之斷面圖。 第1 4圖係爲表示將本發明實施形態1的半導體裝置 實裝在印刷電路板的狀態之斷面圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) -29- 409393 at __ B7_ 五、發明說明(27 ) 第15圖係爲本發明實施形態2的半導體裝置之斷面 圖。 第1 6圖係爲本發明實施形態2的半導體裝置之要部 •擴大斷面圖。 第1 7圖係爲本發明實施形態3的半導體裝置之斜視 圖。 第18圖係爲本發明實施形態3的半導體裝置之斷面 圖 \ 第1 及1 9^§狄.圖係爲表示本發明實施形 態3的半導體製造方面圖。 第2 0圖係爲表示用本發明實施形態3的半導體裝置 之積層型記憶模組的一例之斜視圖。 第21圖係爲表示用本發明實施形態3的半導體裝置 之積層型記憶模組的製造方法之說明圖。 第2 2圖係爲表示用本發明實施形態3的半導體裝置 之積層型記億模組的製造方法之說明圖。 第2 3圖係爲表示用本發明實施形態3的半導體裝置 之積層型記億模組的他例之斜視圖。 第2 4圖係爲本發明實施形態4的半導體裝置之平面 圖。 第2 5圖係爲本發明實施形態4的半導體裝置之平面 圖。 第2 6圖係爲表示本發明實施形態4的半導體裝置之 製造方法之斷面圖。 本紙張尺度適用中國國家標準<CNS)A4規格(210 X 297公« ) ------------I·--政.·1 (請先Μ讀背面之注意事項再填寫本頁) 8-
* S 經濟部智慧財產局負工消費合作社印製 -30- 409393 A7 B7 五、發明繼爵J28 ) 第表示本發明實施形態4的半導體裝置之 製造方法的他例之斷面圖。 圖 圖 圖 面 圖 面 第 2 第 第 第 面 斷 之 置 裝 1 導 半 的 5 態 形 施 實 明 發 本 爲 係 圖 面 cn· 斷 之 置 裝 體 導 半 的 5 態 形 施 實 明 發 本 爲 係 圖 他 其 明 發 本 爲 係 圖 斷 之 置 裝 體 導 半 的 態 形 施 1 之 置 裝 澧 導 半 的 態 形 施 實 他 其 明 發 本 爲 係 圖 <諳先閲讀背面之生意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公芨) -31 -
Claims (1)
- A8 409393 § 六、申請專利範圍 1 種半導體裝置,係具有: 在主面形成有接合用電極之半導體晶片; 各具有內引線,外引線之多數個引線: 晶片支撐引線; 連接上述內引線前端部與前述接合墊焊之接合導線; 及 封裝前述半導體晶片,前述內引線,前述接合導線與 前述晶片支撐引線之樹脂封裝體: 前述內引線的前端部,係配置在前述半導體晶片外周 ,且於前述半導體晶片的厚度方向,位於前述半導體晶片 的厚度內, 前述外引線部係從前述樹脂封裝體側面朝外方延伸, 前述晶片支撐引線的一部分配置在前述半導體晶片主 面上,且介由接著劑接著在前述半導體晶片的主面。 2 .如申請專利範圍第1項之半導體裝置,其中前述 半導體晶片的厚度方向之前述晶片支撐引線部的厚度’係 爲不大於前述接合導線之軌跡頂點部高度。 3 .如申請專利範圍第1或2項之半導體裝置’其中 前述晶片支撐引線,係未電連接於前述接合導線的引線。 4 .如申請專利範圍第1項之半導體裝置’其中前述 晶片支撐引線,係於前述樹脂封裝體內,從前述內引線所 分歧之引線部。 5.如申請專利範圍第1項之半導體裝置’其中前述 接著劑,至少其一部分被形成在前述半導體晶片主面之端 -------------裝--- (請先閲讀背面之注*Ϋ項再填寫本頁) -SJ. .4. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS>A4規格<210 x 297公« > -32 - 409393 § D8 六、申請專利範圍 部。 (請先Μ讀背面之沒意事項再填寫本頁) 6 .如申請專利範圍第1項之半導體裝置,其中前述 接著劑,係於前述半導體晶片主面與前述晶片支撐引線間 ,隔著所定間隔存在於複數個領域。 7 .如申請專利範圍第1項之半導體裝置,其中前述 外引線部,係彎曲成表面實裝可能,且在其一部分含有朝 向與前述樹脂封裝體上面或底面水平方向延伸存在之延長 部。 8 .如申請專利範圍第7項之半導體裝置,其中前述 外引線部,係彎曲成表面實裝可能,且在其一部分含有朝 向前述樹脂封裝體的斜上方延伸存在之延長部。 9 .如申請專利範圍第8項之半導體裝置,其中在前 述外引線部寬度方向兩側面,設有朝前述樹脂封裝體上面 方向延伸存在之一對阻隔構件。 1 0 .如申請專利範圍第9項之半導體裝置,其中前 述外引線部之下端部的寬,係比朝前述斜上方延伸存在之 延長部的寬還窄。 經濟部智慧財產局員工消費合作社印製 1 1 .如申請專利範圍第1 0項之半導體裝置,其中 前述一對阻隔構件,係以連結引線框架之外引線間之聯結 桿彎曲形成。 _1 2 . —種半導體裝置,係具有: 形成多數配線之實裝基板: 配置在前述實裝基板上之第1表面實裝型封裝體;及 被積層在上述第1表面實裝型封裝體上之第2表面實 -33- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財岌局員工消費合作社印製 409393 | D8 六、申請專利範圍 裝型封裝體; 前述第1及第2表面實裝型封裝體,係各具有: 在主面形成有接合用電極之半導體晶片; 各具有內引線,外引線之多數引線; 晶片支擦引線: 連接前述內引線的前端部與前述接合用電極之接合導 線.及 封裝前述半導體晶片,前述內引線,前述接合導線與 前述晶片支撐引線之樹脂封裝體: 前述內引線部的前端部,係配置在前述半導體晶片外 周’且於前述半導體晶片的厚度方向,位於前述半導體晶 片的厚度內: 前述外引線部係從前述樹脂封裝體側面朝外方延伸, 前述晶片支撐引線的一部分配置在前述半導體晶片主 面上,且介由接著劑接著在前述半導體晶片的主面; 前述第1及第2表面實裝型封裝體對應之外引線被導 電連接。 13·—種半導體裝置之製造方法,係包含以下過程 (a )準備在主面形成有接合用電極的半導體晶片之 過程: (b)準備具有外框、及各具內引線、外引線的多數 引線、及晶片支撐引線的引線框架,即準備前述多數個引 線及晶片支撐引線與前述外框一體形成的引線框架之過程 -------------裝-------—訂--------線 <請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準<CNS)A4規格(210 X 297公茇> -34 - 409393 A8 B8 C8 D8 經濟部智慧財產局員工消费合作社印製 六、申請專利範圍 _ * r (C)將前述內引線的前端部配置在前述半導體晶片 外周,且於前述半導體晶片厚度方向,將前述內引線的前 端部配置前述半導體晶片的厚度內,且將前述晶片支撐引 線的一部分配置在前述半導體晶片主面上之過程: (d )介由接著劑,將前述晶片支撐引線的一部分接 ¥在前述半導體晶片主面之過程: (e )以接合導線,連接前述內引線前端部與前述接 合用電極之過程; (f )以樹脂封裝體封裝前述半導體晶片、前述內引 線、前述接合導線及前述晶片支撐引線的一部分之過程; 及 (g )在前述樹脂封裝體與前述引線框架的外框間, 裁斷前述晶片支撐引線之過程* 1 4 · ~種半導體裝置,其特徵爲具有: 半導體晶片,其具有主面,與上述主面面對之背面, 及位於上述主面與背面間之側面;在上述主面形成有積體 電路及接合用電極: 第1引線,其具有內引線及與上述內引線一體形成之 外引線,上述內引線之端部配置於上述半導體晶片側面之 近傍; 第2引線,其一端部配置於上述半導體晶片主面上, 且介由接著劑接著於上述半導體晶片主面; 電連接上述第1引線之內引線端部及上述接合用電極 本紙張尺度適用中固國家標準(CNS)A4規格(210 X 297公釐) -35- ---------------裝— <請先閱讀背面之注意事項再填寫本頁) *5J· P. 4- B8 409393__§__ 六、申請專利範圍 的接合用導線;及 (请先閱#背面之注意事項再填寫本頁) 封裝上述半導體晶片’上述第1引線之內引線,上述 第2引線及上述接合用導線的樹脂體; 上述第1引線之內引線端部上面,於上述半導體晶片 之厚度方向,係配置在較上述第2引線上面低之位置, 上述接合用導線之軌跡,於上述半導體晶片之厚度方 向’係具有與第上述半導體晶片主面最遠離之頂點部分,' 上述第2引線上面,於上述半導體晶片之厚度方向, 係配置在較上述接合用導線之頂點部分低之位置^ 1 5 _如申請專利範圍第1 4項之半導體裝置,其中 上述第2引線之另一端部,係終止於上述樹脂體內部. 與外部之境界面。 1 6 .如申請專利範圍第1 5項之半導體裝置,其中 上述第2引線之另一端部,於上述半導體晶片側面與 樹脂體之境界面之間,係具有段差部。 經濟部智慧財產局員工消費合作社印製 1 7 .如申請專利範圍第.1 6項之半導體裝置,其中 上述第2引線之另一端部,於上述半導體晶片之厚度 方向,係位於與上述第1引線之內引線約同高度之位置。 1 8 ·如申請專利範圍第1 4項之半導體裝置,其中 上述半導體晶片背面,係與上述樹脂體直接接觸》 1 9 ·如申請專利範圍第1 4項之半導體裝置,其中 上述半導體晶片爲長方形狀,上述第2引線,係橫切 上述半導體晶片短邊,配置於上述半導體晶片主面上。 2 0 .如申請專利範圍第1 4項之半導體裝置,其中 本紙張尺度適用尹國國家標準<CNS)A4規格(210 * 297公釐) -36- § 409393 六、申請專利範園 上述第2引線’係上述接合用導線未連接之引線。 2 1 .如申請專利範圍第1 4項之半導體裝置,其中 上述第1引線爲信號用引線,上述第2引線爲未電連 接上述半導體晶片之引線》 2 2 _如申請專利範圍第1 4項之半導體裝置,其中 上述第1引線之內引線端部,於上述半導體晶片之厚 度方向,係配置於上述半導體晶片厚度內。 ------------ri.! (#先閲讀背面之ii意事項再填寫本頁) >^_ 經濟部智慧財產局貝工消费合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公莱)
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JP9041263A JPH10242368A (ja) | 1997-02-25 | 1997-02-25 | 半導体装置およびその製造方法ならびに半導体モジュールおよびicカード |
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CN110959191A (zh) * | 2017-08-24 | 2020-04-03 | 新电元工业株式会社 | 半导体装置 |
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US6124150A (en) | 1998-08-20 | 2000-09-26 | Micron Technology, Inc. | Transverse hybrid LOC package |
TW468258B (en) * | 1998-10-21 | 2001-12-11 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
US7057273B2 (en) * | 2001-05-15 | 2006-06-06 | Gem Services, Inc. | Surface mount package |
JP2003006601A (ja) * | 2001-06-22 | 2003-01-10 | Toppan Forms Co Ltd | 絶縁性接着剤を用いたrf−idメディアの形成方法 |
DE10158770B4 (de) * | 2001-11-29 | 2006-08-03 | Infineon Technologies Ag | Leiterrahmen und Bauelement mit einem Leiterrahmen |
KR20050100656A (ko) * | 2003-02-04 | 2005-10-19 | 어드밴스드 인터커넥트 테크놀로지스 리미티드 | 박막 다중 반도체 다이 패키지 |
DE102014100110A1 (de) * | 2014-01-07 | 2015-07-09 | Infineon Technologies Ag | Package mit Anschlusspins mit lateralem Umkehrpunkt und lateral freigelegtem freien Ende |
ITTO20150230A1 (it) * | 2015-04-24 | 2016-10-24 | St Microelectronics Srl | Procedimento per produrre componenti elettronici, componente e prodotto informatico corrispondenti |
DE102016212886A1 (de) * | 2016-07-14 | 2018-01-18 | Zf Friedrichshafen Ag | Anordnung und Verfahren zur Verbesserung der Lötverbindung zwischen einem Bauteil und einem Substrat |
CN111602241B (zh) * | 2018-01-17 | 2023-09-15 | 新电元工业株式会社 | 电子模块 |
JP7238277B2 (ja) * | 2018-06-14 | 2023-03-14 | 富士電機株式会社 | 半導体装置、リードフレーム及び半導体装置の製造方法 |
US11069600B2 (en) * | 2019-05-24 | 2021-07-20 | Infineon Technologies Ag | Semiconductor package with space efficient lead and die pad design |
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US5234866A (en) | 1985-03-25 | 1993-08-10 | Hitachi, Ltd. | Semiconductor device and process for producing the same, and lead frame used in said process |
JP2567961B2 (ja) * | 1989-12-01 | 1996-12-25 | 株式会社日立製作所 | 半導体装置及びリ−ドフレ−ム |
JP3075617B2 (ja) | 1991-12-25 | 2000-08-14 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH05190750A (ja) * | 1992-01-13 | 1993-07-30 | Toshiba Corp | 半導体装置 |
MY114547A (en) * | 1992-05-25 | 2002-11-30 | Hitachi Ltd | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
JP2934119B2 (ja) * | 1992-05-25 | 1999-08-16 | 株式会社日立製作所 | 半導体装置、積層体及びモジュール構造体 |
JPH08125118A (ja) * | 1994-10-21 | 1996-05-17 | Hitachi Ltd | 半導体集積回路装置 |
JPH10199912A (ja) * | 1997-01-16 | 1998-07-31 | Hitachi Ltd | 半導体装置 |
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CN110959191A (zh) * | 2017-08-24 | 2020-04-03 | 新电元工业株式会社 | 半导体装置 |
CN110959191B (zh) * | 2017-08-24 | 2023-10-20 | 新电元工业株式会社 | 半导体装置 |
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KR100679201B1 (ko) | 2007-08-16 |
KR19980071599A (ko) | 1998-10-26 |
JPH10242368A (ja) | 1998-09-11 |
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