TW379328B - Column decoding circuit of flash memory having separated character lines - Google Patents
Column decoding circuit of flash memory having separated character lines Download PDFInfo
- Publication number
- TW379328B TW379328B TW087112684A TW87112684A TW379328B TW 379328 B TW379328 B TW 379328B TW 087112684 A TW087112684 A TW 087112684A TW 87112684 A TW87112684 A TW 87112684A TW 379328 B TW379328 B TW 379328B
- Authority
- TW
- Taiwan
- Prior art keywords
- line
- transistor
- decoding device
- decoder
- word line
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970042210A KR100254565B1 (ko) | 1997-08-28 | 1997-08-28 | 분할된 워드 라인 구조를 갖는 플래시 메모리 장치의 행 디코더회로 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW379328B true TW379328B (en) | 2000-01-11 |
Family
ID=19519162
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087112684A TW379328B (en) | 1997-08-28 | 1998-08-01 | Column decoding circuit of flash memory having separated character lines |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH11134887A (ja) |
KR (1) | KR100254565B1 (ja) |
TW (1) | TW379328B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100308192B1 (ko) * | 1999-07-28 | 2001-11-01 | 윤종용 | 플래시 메모리 셀들의 과소거를 방지할 수 있는 플래시 메모리장치 및 그것의 소거 방법 |
JP3530425B2 (ja) | 1999-08-20 | 2004-05-24 | Necマイクロシステム株式会社 | 半導体記憶装置 |
US6088287A (en) * | 1999-08-23 | 2000-07-11 | Advanced Micro Devices, Inc. | Flash memory architecture employing three layer metal interconnect for word line decoding |
KR100331563B1 (ko) * | 1999-12-10 | 2002-04-06 | 윤종용 | 낸드형 플래쉬 메모리소자 및 그 구동방법 |
KR100481857B1 (ko) * | 2002-08-14 | 2005-04-11 | 삼성전자주식회사 | 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치 |
CN101002277A (zh) * | 2004-05-12 | 2007-07-18 | 斯班逊有限公司 | 半导体装置及该控制方法 |
KR100673170B1 (ko) * | 2005-03-10 | 2007-01-22 | 주식회사 하이닉스반도체 | 향상된 소거 기능을 가지는 플래쉬 메모리 장치 및 그 소거동작 제어 방법 |
KR100791332B1 (ko) * | 2006-03-03 | 2008-01-07 | 삼성전자주식회사 | 상변화 메모리 장치 |
US7719919B2 (en) | 2007-03-20 | 2010-05-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device in which word lines are driven from either side of memory cell array |
-
1997
- 1997-08-28 KR KR1019970042210A patent/KR100254565B1/ko not_active IP Right Cessation
-
1998
- 1998-08-01 TW TW087112684A patent/TW379328B/zh not_active IP Right Cessation
- 1998-08-27 JP JP24232598A patent/JPH11134887A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
KR19990018929A (ko) | 1999-03-15 |
JPH11134887A (ja) | 1999-05-21 |
KR100254565B1 (ko) | 2000-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW381267B (en) | Non-volatile semiconductor memory elements having single-bit and multi-bit memory cells | |
JP6633295B2 (ja) | サブブロック消去 | |
US7212434B2 (en) | Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, and a memory card including the same | |
TW559815B (en) | Semiconductor memory device having memory cell arrays capable of accomplishing random access | |
US7245530B2 (en) | Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same | |
TW201225108A (en) | Non-volatile memory and method with even/odd combined block decoding | |
US8717816B2 (en) | Semiconductor memory device | |
US7180789B2 (en) | Semiconductor memory device with MOS transistors, each having a floating gate and a control gate, and memory card including the same | |
JPH0746515B2 (ja) | デコ−ダ回路 | |
JP4047001B2 (ja) | 不揮発性半導体メモリ装置、そのローカルロウデコーダ構造、及び半導体メモリ装置、同装置でのワードライン駆動方法 | |
US10083755B2 (en) | Discharge circuit and semiconductor memory device | |
TW379328B (en) | Column decoding circuit of flash memory having separated character lines | |
CN109658965A (zh) | 半导体存储装置 | |
JP2002151601A (ja) | 半導体記憶装置 | |
US6515911B2 (en) | Circuit structure for providing a hierarchical decoding in semiconductor memory devices | |
US6762959B2 (en) | Low-power nonvolatile semiconductor memory device | |
CN109427393B (zh) | 具有受限尺寸的非易失性存储器 | |
JP6122478B1 (ja) | 不揮発性半導体記憶装置 | |
TW434553B (en) | Nonvolatile memory semiconductor devices having alternative programming operations | |
US8520465B2 (en) | Semiconductor device | |
JP2002353345A (ja) | 半導体メモリ装置およびバルク領域形成方法 | |
TW512352B (en) | Method to reduce capacitive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines | |
JP2001085633A (ja) | 容量構造を有する半導体装置、およびこの容量構造を用いたチャージポンプ回路、ならびにチャージポンプ回路を用いた半導体装置 | |
TWI247305B (en) | Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area | |
JP2542110B2 (ja) | 不揮発性半導体記憶装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |