TW362290B - Semiconductor component and manufacturing method thereof - Google Patents
Semiconductor component and manufacturing method thereofInfo
- Publication number
- TW362290B TW362290B TW087106511A TW87106511A TW362290B TW 362290 B TW362290 B TW 362290B TW 087106511 A TW087106511 A TW 087106511A TW 87106511 A TW87106511 A TW 87106511A TW 362290 B TW362290 B TW 362290B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- substrate
- insulation layer
- semiconductor component
- buried
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000009413 insulation Methods 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 4
- 238000005468 ion implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970068562A KR100252866B1 (ko) | 1997-12-13 | 1997-12-13 | 반도체소자 및 이의 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW362290B true TW362290B (en) | 1999-06-21 |
Family
ID=19527274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087106511A TW362290B (en) | 1997-12-13 | 1998-04-28 | Semiconductor component and manufacturing method thereof |
Country Status (4)
Country | Link |
---|---|
US (3) | US6023088A (zh) |
JP (1) | JP3495257B2 (zh) |
KR (1) | KR100252866B1 (zh) |
TW (1) | TW362290B (zh) |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3107024B2 (ja) * | 1997-12-09 | 2000-11-06 | 日本電気株式会社 | 薄膜トランジスタの製造方法 |
JP3408762B2 (ja) * | 1998-12-03 | 2003-05-19 | シャープ株式会社 | Soi構造の半導体装置及びその製造方法 |
US6890827B1 (en) * | 1999-01-13 | 2005-05-10 | Agere Systems Inc. | Method of fabricating a silicon on insulator transistor structure for imbedded DRAM |
JP4540142B2 (ja) * | 1999-01-19 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
TW491952B (en) * | 1999-09-27 | 2002-06-21 | Seiko Epson Corp | Optoelectic apparatus and electronic apparatus |
GB2358080B (en) * | 2000-01-07 | 2004-06-02 | Seiko Epson Corp | Method of manufacturing a thin-film transistor |
GB2358081B (en) * | 2000-01-07 | 2004-02-18 | Seiko Epson Corp | A thin-film transistor and a method for maufacturing thereof |
US6495887B1 (en) * | 2000-06-09 | 2002-12-17 | Advanced Micro Devices, Inc. | Argon implantation after silicidation for improved floating-body effects |
KR100674896B1 (ko) * | 2000-07-26 | 2007-01-26 | 삼성전자주식회사 | 반도체 집적회로의 트렌치 소자 분리 방법 |
US6479866B1 (en) * | 2000-11-14 | 2002-11-12 | Advanced Micro Devices, Inc. | SOI device with self-aligned selective damage implant, and method |
US6406975B1 (en) * | 2000-11-27 | 2002-06-18 | Chartered Semiconductor Manufacturing Inc. | Method for fabricating an air gap shallow trench isolation (STI) structure |
KR100672932B1 (ko) * | 2000-12-26 | 2007-01-23 | 삼성전자주식회사 | 실리콘 온 인슐레이터 트랜지스터 및 그 제조방법 |
US6538284B1 (en) | 2001-02-02 | 2003-03-25 | Advanced Micro Devices, Inc. | SOI device with body recombination region, and method |
KR100512167B1 (ko) * | 2001-03-12 | 2005-09-02 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 트렌치형 소자 분리막형성방법 |
US6509613B1 (en) * | 2001-05-04 | 2003-01-21 | Advanced Micro Devices, Inc. | Self-aligned floating body control for SOI device through leakage enhanced buried oxide |
US7122863B1 (en) | 2001-05-07 | 2006-10-17 | Advanced Micro Devices, Inc. | SOI device with structure for enhancing carrier recombination and method of fabricating same |
US20020197823A1 (en) * | 2001-05-18 | 2002-12-26 | Yoo Jae-Yoon | Isolation method for semiconductor device |
US6528851B1 (en) * | 2001-05-31 | 2003-03-04 | Advanced Micro Devices, Inc. | Post-silicidation implant for introducing recombination center in body of SOI MOSFET |
US6433391B1 (en) * | 2001-06-08 | 2002-08-13 | Advanced Micro Devices, Inc. | Bonded SOI for floating body and metal gettering control |
KR100396469B1 (ko) * | 2001-06-29 | 2003-09-02 | 삼성전자주식회사 | 반도체 장치의 게이트 전극 형성 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법 |
US6740955B1 (en) * | 2001-07-03 | 2004-05-25 | Samsung Electronics Co., Ltd. | Trench device isolation structure |
KR100428806B1 (ko) * | 2001-07-03 | 2004-04-28 | 삼성전자주식회사 | 트렌치 소자분리 구조체 및 그 형성 방법 |
KR100421911B1 (ko) * | 2001-09-20 | 2004-03-11 | 주식회사 하이닉스반도체 | 반도체 소자의 격리 영역 형성 방법 |
JP2003158180A (ja) * | 2001-11-26 | 2003-05-30 | Mitsubishi Electric Corp | トレンチ分離を有する半導体装置およびその製造方法 |
DE10157785A1 (de) * | 2001-11-27 | 2003-06-12 | Austriamicrocsystems Ag Schlos | Isolationsgraben für eine intergrierte Schaltung und Verfahren zu dessen Herstellung |
US6506654B1 (en) * | 2002-03-26 | 2003-01-14 | Advanced Micro Devices, Inc. | Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control |
JP2003297750A (ja) * | 2002-04-05 | 2003-10-17 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
US6727147B2 (en) * | 2002-06-10 | 2004-04-27 | Oki Electric Industry Co., Ltd. | MOSFET fabrication method |
US6828632B2 (en) * | 2002-07-18 | 2004-12-07 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
US6822325B2 (en) * | 2002-08-01 | 2004-11-23 | Altera Corporation | Isolating temperature sensitive components from heat sources in integrated circuits |
US6794269B1 (en) * | 2002-12-20 | 2004-09-21 | Cypress Semiconductor Corp. | Method for and structure formed from fabricating a relatively deep isolation structure |
US7042052B2 (en) * | 2003-02-10 | 2006-05-09 | Micron Technology, Inc. | Transistor constructions and electronic devices |
US6844591B1 (en) * | 2003-09-17 | 2005-01-18 | Micron Technology, Inc. | Method of forming DRAM access transistors |
US6921704B1 (en) | 2003-11-05 | 2005-07-26 | Advanced Micro Devices, Inc. | Method for improving MOS mobility |
US7247569B2 (en) * | 2003-12-02 | 2007-07-24 | International Business Machines Corporation | Ultra-thin Si MOSFET device structure and method of manufacture |
US8427494B2 (en) * | 2004-01-30 | 2013-04-23 | Nvidia Corporation | Variable-length coding data transfer interface |
US7012316B1 (en) * | 2004-09-17 | 2006-03-14 | International Business Machines Corporation | Isolation structures in semiconductor integrated circuits (IC) |
JP5099981B2 (ja) * | 2005-05-31 | 2012-12-19 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法およびmos電界効果トランジスタ |
US8501632B2 (en) * | 2005-12-20 | 2013-08-06 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
US8936995B2 (en) | 2006-03-01 | 2015-01-20 | Infineon Technologies Ag | Methods of fabricating isolation regions of semiconductor devices and structures thereof |
US7659178B2 (en) * | 2006-04-21 | 2010-02-09 | International Business Machines Corporation | Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate |
US7984408B2 (en) * | 2006-04-21 | 2011-07-19 | International Business Machines Corporation | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8725504B1 (en) | 2007-06-06 | 2014-05-13 | Nvidia Corporation | Inverse quantization in audio decoding |
US8726125B1 (en) | 2007-06-06 | 2014-05-13 | Nvidia Corporation | Reducing interpolation error |
US8477852B2 (en) * | 2007-06-20 | 2013-07-02 | Nvidia Corporation | Uniform video decoding and display |
US8502709B2 (en) * | 2007-09-17 | 2013-08-06 | Nvidia Corporation | Decoding variable length codes in media applications |
US8849051B2 (en) * | 2007-09-17 | 2014-09-30 | Nvidia Corporation | Decoding variable length codes in JPEG applications |
JP2009099598A (ja) * | 2007-10-12 | 2009-05-07 | Toshiba Corp | 半導体装置及びその製造方法 |
US8704834B2 (en) * | 2007-12-03 | 2014-04-22 | Nvidia Corporation | Synchronization of video input data streams and video output data streams |
US8934539B2 (en) * | 2007-12-03 | 2015-01-13 | Nvidia Corporation | Vector processor acceleration for media quantization |
US8687875B2 (en) * | 2007-12-03 | 2014-04-01 | Nvidia Corporation | Comparator based acceleration for media quantization |
US7936017B2 (en) * | 2008-05-15 | 2011-05-03 | International Business Machines Corporation | Reduced floating body effect without impact on performance-enhancing stress |
US9307267B2 (en) * | 2008-12-11 | 2016-04-05 | Nvidia Corporation | Techniques for scalable dynamic data encoding and decoding |
JP2013089859A (ja) * | 2011-10-20 | 2013-05-13 | Toshiba Corp | 半導体装置の製造方法 |
US9780117B2 (en) * | 2014-10-22 | 2017-10-03 | Qualcomm Incorporated | Semiconductor structure with active device and damaged region |
US20200212227A1 (en) * | 2016-08-17 | 2020-07-02 | Boe Technology Group Co., Ltd. | Thin film transistor, manufacturing method thereof, array substrate, display device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4169000A (en) * | 1976-09-02 | 1979-09-25 | International Business Machines Corporation | Method of forming an integrated circuit structure with fully-enclosed air isolation |
US4356211A (en) * | 1980-12-19 | 1982-10-26 | International Business Machines Corporation | Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon |
US5098856A (en) * | 1991-06-18 | 1992-03-24 | International Business Machines Corporation | Air-filled isolation trench with chemically vapor deposited silicon dioxide cap |
JP3361922B2 (ja) * | 1994-09-13 | 2003-01-07 | 株式会社東芝 | 半導体装置 |
US6057226A (en) * | 1997-11-25 | 2000-05-02 | Intel Corporation | Air gap based low dielectric constant interconnect structure and method of making same |
US6004837A (en) * | 1998-02-18 | 1999-12-21 | International Business Machines Corporation | Dual-gate SOI transistor |
US6005285A (en) * | 1998-12-04 | 1999-12-21 | Advanced Micro Devices, Inc. | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device |
-
1997
- 1997-12-13 KR KR1019970068562A patent/KR100252866B1/ko not_active IP Right Cessation
-
1998
- 1998-04-28 TW TW087106511A patent/TW362290B/zh not_active IP Right Cessation
- 1998-05-28 US US09/085,016 patent/US6023088A/en not_active Expired - Lifetime
- 1998-07-08 JP JP19269598A patent/JP3495257B2/ja not_active Expired - Fee Related
- 1998-11-19 US US09/195,558 patent/US6127241A/en not_active Expired - Lifetime
-
1999
- 1999-11-30 US US09/450,657 patent/US6210998B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6127241A (en) | 2000-10-03 |
JPH11186564A (ja) | 1999-07-09 |
KR100252866B1 (ko) | 2000-04-15 |
KR19990049592A (ko) | 1999-07-05 |
JP3495257B2 (ja) | 2004-02-09 |
US6210998B1 (en) | 2001-04-03 |
US6023088A (en) | 2000-02-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |