TW327696B - The manufacturing method for MOS device - Google Patents

The manufacturing method for MOS device

Info

Publication number
TW327696B
TW327696B TW086111661A TW86111661A TW327696B TW 327696 B TW327696 B TW 327696B TW 086111661 A TW086111661 A TW 086111661A TW 86111661 A TW86111661 A TW 86111661A TW 327696 B TW327696 B TW 327696B
Authority
TW
Taiwan
Prior art keywords
dielectric
compound structure
substrate
well
manufacturing
Prior art date
Application number
TW086111661A
Other languages
Chinese (zh)
Inventor
Horng-Nan Chen
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW086111661A priority Critical patent/TW327696B/en
Application granted granted Critical
Publication of TW327696B publication Critical patent/TW327696B/en

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A manufacturing method for MOS device with local anti-punchthrough structure, it includes following steps: - Form an compound structure on substrate, that structures includes a gate oxide and a conductive polysilicon layer; - Deposit 1st dielectric on top and side of the compound structure, and exposed substrate; - Deposit 2nd dielectric on 1st dielectric; - Etch back 2nd dielectric to expose 1st dielectric on compound structure; - Isotropic etching 1st dielectric to remove the 1st dielectric on top and side of compound structure to define the well at least one side of compound structure; - Through well to proceed doping on the substrate at one side of compound structure to form anti-punchthrough structure; - Fill the 3rd dielectric into well; - Anisotropic etching 2nd and 3rd dielectric to form side spacer; - Remove the exposed 1st dielectric layer; - Form doping area on exposed substrate.
TW086111661A 1997-08-14 1997-08-14 The manufacturing method for MOS device TW327696B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086111661A TW327696B (en) 1997-08-14 1997-08-14 The manufacturing method for MOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086111661A TW327696B (en) 1997-08-14 1997-08-14 The manufacturing method for MOS device

Publications (1)

Publication Number Publication Date
TW327696B true TW327696B (en) 1998-03-01

Family

ID=58262368

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086111661A TW327696B (en) 1997-08-14 1997-08-14 The manufacturing method for MOS device

Country Status (1)

Country Link
TW (1) TW327696B (en)

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees