TW346670B - Fabrication process and fabrication apparatus of SOI substrate - Google Patents
Fabrication process and fabrication apparatus of SOI substrateInfo
- Publication number
- TW346670B TW346670B TW085115260A TW85115260A TW346670B TW 346670 B TW346670 B TW 346670B TW 085115260 A TW085115260 A TW 085115260A TW 85115260 A TW85115260 A TW 85115260A TW 346670 B TW346670 B TW 346670B
- Authority
- TW
- Taiwan
- Prior art keywords
- crystal
- region
- porous single
- fabrication
- soi substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32292195 | 1995-12-12 | ||
JP32510696A JP3250722B2 (ja) | 1995-12-12 | 1996-12-05 | Soi基板の製造方法および製造装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW346670B true TW346670B (en) | 1998-12-01 |
Family
ID=26570983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085115260A TW346670B (en) | 1995-12-12 | 1996-12-10 | Fabrication process and fabrication apparatus of SOI substrate |
Country Status (7)
Country | Link |
---|---|
US (1) | US5876497A (zh) |
EP (1) | EP0779649A3 (zh) |
JP (1) | JP3250722B2 (zh) |
KR (1) | KR100225699B1 (zh) |
CN (1) | CN1090381C (zh) |
CA (1) | CA2192630C (zh) |
TW (1) | TW346670B (zh) |
Families Citing this family (52)
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EP0991126B1 (en) | 1997-12-09 | 2006-10-18 | Seiko Epson Corporation | Method of manufacturing an electrooptic device |
DE19843984B4 (de) * | 1998-09-25 | 2013-10-24 | Robert Bosch Gmbh | Verfahren zur Herstellung von Strahlungssensoren |
JP4343295B2 (ja) * | 1998-11-06 | 2009-10-14 | キヤノン株式会社 | 試料の処理システム |
US6672358B2 (en) | 1998-11-06 | 2004-01-06 | Canon Kabushiki Kaisha | Sample processing system |
JP2000150836A (ja) | 1998-11-06 | 2000-05-30 | Canon Inc | 試料の処理システム |
TW484184B (en) * | 1998-11-06 | 2002-04-21 | Canon Kk | Sample separating apparatus and method, and substrate manufacturing method |
US6165873A (en) * | 1998-11-27 | 2000-12-26 | Nec Corporation | Process for manufacturing a semiconductor integrated circuit device |
US6890827B1 (en) * | 1999-01-13 | 2005-05-10 | Agere Systems Inc. | Method of fabricating a silicon on insulator transistor structure for imbedded DRAM |
JP2000299263A (ja) * | 1999-04-14 | 2000-10-24 | Seiko Epson Corp | シリコン系部材の固体接合方法 |
FR2794893B1 (fr) | 1999-06-14 | 2001-09-14 | France Telecom | Procede de fabrication d'un substrat de silicium comportant une mince couche d'oxyde de silicium ensevelie |
US6372151B1 (en) | 1999-07-27 | 2002-04-16 | Applied Materials, Inc. | Storage poly process without carbon contamination |
US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
US6984571B1 (en) | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US6398348B1 (en) | 2000-09-05 | 2002-06-04 | Hewlett-Packard Company | Printing structure with insulator layer |
US6774010B2 (en) | 2001-01-25 | 2004-08-10 | International Business Machines Corporation | Transferable device-containing layer for silicon-on-insulator applications |
ATE493368T1 (de) * | 2001-03-29 | 2011-01-15 | Toyota Chuo Kenkyusho Kk | Ein verfahren zum erzeugen einer hohlen struktur aus einer silizium-struktur |
KR100456526B1 (ko) * | 2001-05-22 | 2004-11-09 | 삼성전자주식회사 | 식각저지막을 갖는 에스오아이 기판, 그 제조방법, 그위에 제작된 에스오아이 집적회로 및 그것을 사용하여에스오아이 집적회로를 제조하는 방법 |
JP2002353081A (ja) | 2001-05-25 | 2002-12-06 | Canon Inc | 板部材の分離装置及び分離方法 |
JP2002353423A (ja) * | 2001-05-25 | 2002-12-06 | Canon Inc | 板部材の分離装置及び処理方法 |
WO2003038884A2 (en) * | 2001-10-29 | 2003-05-08 | Analog Devices Inc. | A method for bonding a pair of silicon wafers together and a semiconductor wafer |
US6685302B2 (en) | 2001-10-31 | 2004-02-03 | Hewlett-Packard Development Company, L.P. | Flextensional transducer and method of forming a flextensional transducer |
US6679587B2 (en) * | 2001-10-31 | 2004-01-20 | Hewlett-Packard Development Company, L.P. | Fluid ejection device with a composite substrate |
KR100442105B1 (ko) * | 2001-12-03 | 2004-07-27 | 삼성전자주식회사 | 소이형 기판 형성 방법 |
KR100465630B1 (ko) * | 2002-05-03 | 2005-01-13 | 주식회사 하이닉스반도체 | 웨이퍼의 제조방법 |
US20040124088A1 (en) * | 2002-12-26 | 2004-07-01 | Canon Kabushiki Kaisha | Processing apparatus |
US6883903B2 (en) | 2003-01-21 | 2005-04-26 | Martha A. Truninger | Flextensional transducer and method of forming flextensional transducer |
US20040245571A1 (en) * | 2003-02-13 | 2004-12-09 | Zhiyuan Cheng | Semiconductor-on-insulator article and method of making same |
FR2851846A1 (fr) * | 2003-02-28 | 2004-09-03 | Canon Kk | Systeme de liaison et procede de fabrication d'un substrat semi-conducteur |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
US7410883B2 (en) * | 2005-04-13 | 2008-08-12 | Corning Incorporated | Glass-based semiconductor on insulator structures and methods of making same |
KR100729208B1 (ko) * | 2005-12-22 | 2007-06-19 | 한국야금 주식회사 | 표면 조도 및 광택이 우수한 경질 박막 및 이의제조방법 |
US7790565B2 (en) * | 2006-04-21 | 2010-09-07 | Corning Incorporated | Semiconductor on glass insulator made using improved thinning process |
US7803690B2 (en) | 2006-06-23 | 2010-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy silicon on insulator (ESOI) |
US7875881B2 (en) * | 2007-04-03 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
US7635617B2 (en) * | 2007-04-27 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device |
US20090032873A1 (en) * | 2007-07-30 | 2009-02-05 | Jeffrey Scott Cites | Ultra thin single crystalline semiconductor TFT and process for making same |
JP5430846B2 (ja) * | 2007-12-03 | 2014-03-05 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US20090152663A1 (en) * | 2007-12-18 | 2009-06-18 | Xiang Zheng Tu | Perforated silicon plate assembly for forming and transferring of silicon thin film solar cells |
JP5354900B2 (ja) * | 2007-12-28 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
JP5700617B2 (ja) | 2008-07-08 | 2015-04-15 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
CN102259875B (zh) * | 2010-05-25 | 2013-04-03 | 中国科学院微电子研究所 | 一种发光多孔硅的制备方法 |
DE102010048043A1 (de) * | 2010-10-15 | 2012-04-19 | Ev Group Gmbh | Vorrichtung und Verfahren zur Prozessierung von Wafern |
CN102184881B (zh) * | 2011-04-01 | 2012-08-15 | 百力达太阳能股份有限公司 | 一种硅片干法刻蚀前的整理方法 |
KR102037542B1 (ko) * | 2012-01-17 | 2019-10-28 | 도쿄엘렉트론가부시키가이샤 | 기판 배치대 및 플라즈마 처리 장치 |
JP2014090186A (ja) * | 2013-12-04 | 2014-05-15 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
CN106252219A (zh) * | 2016-07-29 | 2016-12-21 | 浙江大学 | 一种制备高平整度绝缘层上半导体结构的方法 |
CN108456930A (zh) * | 2018-02-24 | 2018-08-28 | 常熟华融太阳能新型材料有限公司 | 一种多晶硅铸锭用多孔硅籽晶及其制备方法和应用 |
US11232975B2 (en) | 2018-09-26 | 2022-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator (SOI) substrate having dielectric structures that increase interface bonding strength |
CN109346495A (zh) * | 2018-11-21 | 2019-02-15 | 德淮半导体有限公司 | 晶圆键合方法 |
US11232974B2 (en) * | 2018-11-30 | 2022-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication method of metal-free SOI wafer |
US10950631B1 (en) * | 2019-09-24 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor-on-insulator wafer having a composite insulator layer |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950014609B1 (ko) * | 1990-08-03 | 1995-12-11 | 캐논 가부시끼가이샤 | 반도체부재 및 반도체부재의 제조방법 |
JPH0817166B2 (ja) * | 1991-04-27 | 1996-02-21 | 信越半導体株式会社 | 超薄膜soi基板の製造方法及び製造装置 |
TW211621B (zh) * | 1991-07-31 | 1993-08-21 | Canon Kk | |
JP3261685B2 (ja) * | 1992-01-31 | 2002-03-04 | キヤノン株式会社 | 半導体素子基体及びその作製方法 |
JPH0726382A (ja) * | 1993-05-10 | 1995-01-27 | Canon Inc | 半導体膜の形成方法及び該半導体膜を有する半導体装置 |
-
1996
- 1996-12-05 JP JP32510696A patent/JP3250722B2/ja not_active Expired - Fee Related
- 1996-12-09 US US08/762,595 patent/US5876497A/en not_active Expired - Fee Related
- 1996-12-10 TW TW085115260A patent/TW346670B/zh active
- 1996-12-11 CA CA002192630A patent/CA2192630C/en not_active Expired - Fee Related
- 1996-12-11 EP EP96309013A patent/EP0779649A3/en not_active Ceased
- 1996-12-12 CN CN96123922A patent/CN1090381C/zh not_active Expired - Fee Related
- 1996-12-12 KR KR1019960064572A patent/KR100225699B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1160285A (zh) | 1997-09-24 |
US5876497A (en) | 1999-03-02 |
EP0779649A3 (en) | 1997-07-02 |
KR19980046273A (ko) | 1998-09-15 |
JPH09223783A (ja) | 1997-08-26 |
KR100225699B1 (ko) | 1999-10-15 |
JP3250722B2 (ja) | 2002-01-28 |
CA2192630A1 (en) | 1997-06-13 |
CN1090381C (zh) | 2002-09-04 |
CA2192630C (en) | 2001-03-13 |
EP0779649A2 (en) | 1997-06-18 |
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