TW328143B - The semiconductor IC apparatus arranged according to cell substrate - Google Patents

The semiconductor IC apparatus arranged according to cell substrate

Info

Publication number
TW328143B
TW328143B TW086105536A TW86105536A TW328143B TW 328143 B TW328143 B TW 328143B TW 086105536 A TW086105536 A TW 086105536A TW 86105536 A TW86105536 A TW 86105536A TW 328143 B TW328143 B TW 328143B
Authority
TW
Taiwan
Prior art keywords
cell
gate electrode
standard
mos transistor
diffusion layer
Prior art date
Application number
TW086105536A
Other languages
English (en)
Inventor
Yasushi Okamoto
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW328143B publication Critical patent/TW328143B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW086105536A 1997-03-11 1997-04-28 The semiconductor IC apparatus arranged according to cell substrate TW328143B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/000763 WO1998040913A1 (fr) 1997-03-11 1997-03-11 Circuit integre a semi-conducteurs dont l'implantation est conçue au niveau des cellules

Publications (1)

Publication Number Publication Date
TW328143B true TW328143B (en) 1998-03-11

Family

ID=14180183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105536A TW328143B (en) 1997-03-11 1997-04-28 The semiconductor IC apparatus arranged according to cell substrate

Country Status (4)

Country Link
US (1) US6335640B1 (zh)
EP (1) EP1026736A4 (zh)
TW (1) TW328143B (zh)
WO (1) WO1998040913A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3372918B2 (ja) * 1999-12-21 2003-02-04 日本電気株式会社 設計支援システム及びセル配置方法
JP4798881B2 (ja) * 2001-06-18 2011-10-19 富士通セミコンダクター株式会社 半導体集積回路装置
JP2004221231A (ja) * 2003-01-14 2004-08-05 Nec Electronics Corp レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法
US7217966B1 (en) * 2005-02-18 2007-05-15 National Semiconductor Corporation Self-protecting transistor array
US7386821B2 (en) * 2006-06-09 2008-06-10 Freescale Semiconductor, Inc. Primitive cell method for front end physical design
JP2008159608A (ja) * 2006-12-20 2008-07-10 Fujitsu Ltd 半導体装置、半導体装置の製造方法および半導体装置の設計装置
JP5580981B2 (ja) * 2008-11-21 2014-08-27 ラピスセミコンダクタ株式会社 半導体素子及び半導体装置
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
JP6001893B2 (ja) * 2012-03-23 2016-10-05 ローム株式会社 セルベースｉｃ、セルベースｉｃのレイアウトシステムおよびレイアウト方法
JP5776802B2 (ja) * 2014-02-14 2015-09-09 ソニー株式会社 半導体集積回路
CN112395823B (zh) * 2020-11-17 2022-08-16 湘潭大学 一种标准单元抗单粒子效应加固的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57190343A (en) * 1981-05-20 1982-11-22 Hitachi Ltd Semiconductor integrated circuit
JPS5878450A (ja) * 1981-11-04 1983-05-12 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置
JPS6052040A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 半導体集積回路
WO1988002110A1 (en) * 1986-09-11 1988-03-24 Gregory Hirsch Point projection photoelectron microscope with hollow needle
US5012427A (en) * 1988-01-30 1991-04-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and method of manufacturing the same
US5157618A (en) * 1988-03-10 1992-10-20 Cirrus Logic, Inc. Programmable tiles
US4931946A (en) * 1988-03-10 1990-06-05 Cirrus Logic, Inc. Programmable tiles
JPH03259549A (ja) 1990-03-08 1991-11-19 Mitsubishi Electric Corp 半導体集積回路
JP3288802B2 (ja) * 1993-05-28 2002-06-04 株式会社東芝 半導体集積回路装置
JPH07130858A (ja) * 1993-11-08 1995-05-19 Fujitsu Ltd 半導体集積回路及び半導体集積回路製造方法
JPH07153926A (ja) * 1993-11-30 1995-06-16 Kawasaki Steel Corp 半導体集積回路装置
JPH07235600A (ja) * 1994-02-22 1995-09-05 Nippon Telegr & Teleph Corp <Ntt> Ｌｓｉ回路およびｌｓｉ回路の製造方法
US5656834A (en) * 1994-09-19 1997-08-12 Philips Electronics North America Corporation IC standard cell designed with embedded capacitors
JPH10284605A (ja) * 1997-04-08 1998-10-23 Mitsubishi Electric Corp 半導体集積回路およびセルベース方式によりレイアウト設計された半導体集積回路
US5959905A (en) * 1997-10-31 1999-09-28 Vlsi Technology, Inc. Cell-based integrated circuit design repair using gate array repair cells

Also Published As

Publication number Publication date
EP1026736A1 (en) 2000-08-09
US6335640B1 (en) 2002-01-01
WO1998040913A1 (fr) 1998-09-17
EP1026736A4 (en) 2002-03-20

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees