TW316342B - - Google Patents

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Publication number
TW316342B
TW316342B TW085107115A TW85107115A TW316342B TW 316342 B TW316342 B TW 316342B TW 085107115 A TW085107115 A TW 085107115A TW 85107115 A TW85107115 A TW 85107115A TW 316342 B TW316342 B TW 316342B
Authority
TW
Taiwan
Prior art keywords
clock signal
circuit
signal
system clock
patent application
Prior art date
Application number
TW085107115A
Other languages
English (en)
Chinese (zh)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW316342B publication Critical patent/TW316342B/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW085107115A 1995-11-28 1996-06-13 TW316342B (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/563,415 US5691660A (en) 1995-11-28 1995-11-28 Clock synchronization scheme for fractional multiplication systems

Publications (1)

Publication Number Publication Date
TW316342B true TW316342B (https=) 1997-09-21

Family

ID=24250394

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085107115A TW316342B (https=) 1995-11-28 1996-06-13

Country Status (5)

Country Link
US (1) US5691660A (https=)
KR (1) KR100195855B1 (https=)
CN (1) CN1091977C (https=)
SG (1) SG67961A1 (https=)
TW (1) TW316342B (https=)

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US5802356A (en) * 1996-11-13 1998-09-01 Integrated Device Technology, Inc. Configurable drive clock
DE10059270B4 (de) * 2000-11-29 2012-08-02 Heidelberger Druckmaschinen Ag Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse
US7242229B1 (en) 2001-05-06 2007-07-10 Altera Corporation Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
US6791380B2 (en) * 2001-11-27 2004-09-14 Winbond Electronics Corporation Universal clock generator
US7319728B2 (en) * 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6801070B2 (en) * 2002-05-16 2004-10-05 Micron Technology, Inc. Measure-controlled circuit with frequency control
US7515666B2 (en) * 2005-07-29 2009-04-07 International Business Machines Corporation Method for dynamically changing the frequency of clock signals
GB0622945D0 (en) * 2006-11-17 2006-12-27 Zarlink Semiconductor Inc Fractional digital PLL
WO2008138053A1 (en) * 2007-05-15 2008-11-20 Fiberbyte Pty Ltd Usb based synchronization and timing system
CN101751068B (zh) * 2008-12-09 2012-04-04 华为技术有限公司 一种同步时钟产生电路和方法
CN101938277B (zh) * 2010-08-12 2012-05-30 四川和芯微电子股份有限公司 倍频系统及实现倍频的方法
CN102594451A (zh) * 2012-02-23 2012-07-18 深圳市新岸通讯技术有限公司 一种测试信号的生成方法及装置
CN103064461B (zh) * 2012-12-31 2016-03-09 华为技术有限公司 一种时钟使能信号的产生方法及装置
US10146732B2 (en) * 2013-01-22 2018-12-04 Apple Inc. Time-division multiplexed data bus interface
US9413364B2 (en) * 2014-07-09 2016-08-09 Intel Corporation Apparatus and method for clock synchronization for inter-die synchronized data transfer
WO2019233571A1 (en) 2018-06-05 2019-12-12 Telefonaktiebolaget Lm Ericsson (Publ) Lo phase correction for aas with multiple rfic
CN111679714B (zh) * 2019-12-31 2022-03-11 泰斗微电子科技有限公司 跨芯片信号同步的方法、装置及芯片
EP4375790A1 (en) * 2022-11-25 2024-05-29 LX Semicon Co., Ltd. Device and method for multi-chip clock synchronization
CN116320098A (zh) * 2023-03-07 2023-06-23 北京旋极信息技术股份有限公司 一种时钟信号的生成方法、时钟装置和信号处理系统

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US3970954A (en) * 1975-04-03 1976-07-20 Bell Telephone Laboratories, Incorporated Digital frequency multiplier
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Also Published As

Publication number Publication date
CN1152822A (zh) 1997-06-25
SG67961A1 (en) 1999-10-19
KR100195855B1 (ko) 1999-06-15
KR970031357A (ko) 1997-06-26
US5691660A (en) 1997-11-25
CN1091977C (zh) 2002-10-02

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