KR100195855B1 - 소수배 시스템에 있어서 클록 동기 체계 - Google Patents

소수배 시스템에 있어서 클록 동기 체계 Download PDF

Info

Publication number
KR100195855B1
KR100195855B1 KR1019960041759A KR19960041759A KR100195855B1 KR 100195855 B1 KR100195855 B1 KR 100195855B1 KR 1019960041759 A KR1019960041759 A KR 1019960041759A KR 19960041759 A KR19960041759 A KR 19960041759A KR 100195855 B1 KR100195855 B1 KR 100195855B1
Authority
KR
South Korea
Prior art keywords
clock signal
system clock
signal
circuit
magnification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960041759A
Other languages
English (en)
Korean (ko)
Other versions
KR970031357A (ko
Inventor
로버트 에드워드 부쉬
케니쓰 마이클 지이크
로버트 모리스 휼
Original Assignee
포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 포만 제프리 엘, 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 포만 제프리 엘
Publication of KR970031357A publication Critical patent/KR970031357A/ko
Application granted granted Critical
Publication of KR100195855B1 publication Critical patent/KR100195855B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1019960041759A 1995-11-28 1996-09-23 소수배 시스템에 있어서 클록 동기 체계 Expired - Fee Related KR100195855B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/563,415 US5691660A (en) 1995-11-28 1995-11-28 Clock synchronization scheme for fractional multiplication systems
US8/563,415 1995-11-28
US08/563,415 1995-11-28

Publications (2)

Publication Number Publication Date
KR970031357A KR970031357A (ko) 1997-06-26
KR100195855B1 true KR100195855B1 (ko) 1999-06-15

Family

ID=24250394

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960041759A Expired - Fee Related KR100195855B1 (ko) 1995-11-28 1996-09-23 소수배 시스템에 있어서 클록 동기 체계

Country Status (5)

Country Link
US (1) US5691660A (https=)
KR (1) KR100195855B1 (https=)
CN (1) CN1091977C (https=)
SG (1) SG67961A1 (https=)
TW (1) TW316342B (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802356A (en) * 1996-11-13 1998-09-01 Integrated Device Technology, Inc. Configurable drive clock
DE10059270B4 (de) * 2000-11-29 2012-08-02 Heidelberger Druckmaschinen Ag Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse
US7242229B1 (en) 2001-05-06 2007-07-10 Altera Corporation Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
US6791380B2 (en) * 2001-11-27 2004-09-14 Winbond Electronics Corporation Universal clock generator
US7319728B2 (en) * 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6801070B2 (en) * 2002-05-16 2004-10-05 Micron Technology, Inc. Measure-controlled circuit with frequency control
US7515666B2 (en) * 2005-07-29 2009-04-07 International Business Machines Corporation Method for dynamically changing the frequency of clock signals
GB0622945D0 (en) * 2006-11-17 2006-12-27 Zarlink Semiconductor Inc Fractional digital PLL
WO2008138053A1 (en) * 2007-05-15 2008-11-20 Fiberbyte Pty Ltd Usb based synchronization and timing system
CN101751068B (zh) * 2008-12-09 2012-04-04 华为技术有限公司 一种同步时钟产生电路和方法
CN101938277B (zh) * 2010-08-12 2012-05-30 四川和芯微电子股份有限公司 倍频系统及实现倍频的方法
CN102594451A (zh) * 2012-02-23 2012-07-18 深圳市新岸通讯技术有限公司 一种测试信号的生成方法及装置
CN103064461B (zh) * 2012-12-31 2016-03-09 华为技术有限公司 一种时钟使能信号的产生方法及装置
US10146732B2 (en) * 2013-01-22 2018-12-04 Apple Inc. Time-division multiplexed data bus interface
US9413364B2 (en) * 2014-07-09 2016-08-09 Intel Corporation Apparatus and method for clock synchronization for inter-die synchronized data transfer
WO2019233571A1 (en) 2018-06-05 2019-12-12 Telefonaktiebolaget Lm Ericsson (Publ) Lo phase correction for aas with multiple rfic
CN111679714B (zh) * 2019-12-31 2022-03-11 泰斗微电子科技有限公司 跨芯片信号同步的方法、装置及芯片
EP4375790A1 (en) * 2022-11-25 2024-05-29 LX Semicon Co., Ltd. Device and method for multi-chip clock synchronization
CN116320098A (zh) * 2023-03-07 2023-06-23 北京旋极信息技术股份有限公司 一种时钟信号的生成方法、时钟装置和信号处理系统

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053839A (en) * 1973-05-29 1977-10-11 Knoedl Jr George Method and apparatus for the frequency multiplication of composite waves
US3970954A (en) * 1975-04-03 1976-07-20 Bell Telephone Laboratories, Incorporated Digital frequency multiplier
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
US4405898A (en) * 1980-06-30 1983-09-20 International Business Machines Corporation Pseudo synchronous clocking
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
US4725786A (en) * 1984-07-26 1988-02-16 Comstron Corporation Full-octave direct frequency synthesizer
US4663541A (en) * 1985-03-18 1987-05-05 Environmental Research Institute Of Michigan Phase-shift stabilized frequency multiplier
US4845437A (en) * 1985-07-09 1989-07-04 Minolta Camera Kabushiki Kaisha Synchronous clock frequency conversion circuit
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5241543A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Independent clocking local area network and nodes used for the same
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
US5077686A (en) * 1990-01-31 1991-12-31 Stardent Computer Clock generator for a computer system
US5208838A (en) * 1990-03-30 1993-05-04 National Semiconductor Corporation Clock signal multiplier
US5245322A (en) * 1990-12-11 1993-09-14 International Business Machines Corporation Bus architecture for a multimedia system
US5175731A (en) * 1990-12-11 1992-12-29 International Business Machines Corporation Arbitration circuit for a multimedia system
US5230041A (en) * 1990-12-11 1993-07-20 International Business Machines Corporation Bus interface circuit for a multimedia system
US5361367A (en) * 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
EP0522720B1 (en) * 1991-06-18 1999-08-18 Nokia Mobile Phones Ltd. Clock frequency adjustment of an electrical circuit
FI88837C (fi) * 1991-08-15 1993-07-12 Nokia Mobile Phones Ltd Frekvensdividering med udda tal och decimaltal
US5281863A (en) * 1992-03-26 1994-01-25 Intel Corporation Phase-locked loop frequency-multiplying phase-matching circuit with a square-wave output
US5394114A (en) * 1992-04-30 1995-02-28 National Semiconductor Corporation One nanosecond resolution programmable waveform generator
US5544203A (en) * 1993-02-17 1996-08-06 Texas Instruments Incorporated Fine resolution digital delay line with coarse and fine adjustment stages
WO1996025796A1 (en) * 1995-02-17 1996-08-22 Intel Corporation Power dissipation control system for vlsi chips
US5548249A (en) * 1994-05-24 1996-08-20 Matsushita Electric Industrial Co., Ltd. Clock generator and method for generating a clock
US5537068A (en) * 1994-09-06 1996-07-16 Intel Corporation Differential delay line clock generator

Also Published As

Publication number Publication date
CN1152822A (zh) 1997-06-25
SG67961A1 (en) 1999-10-19
KR970031357A (ko) 1997-06-26
US5691660A (en) 1997-11-25
TW316342B (https=) 1997-09-21
CN1091977C (zh) 2002-10-02

Similar Documents

Publication Publication Date Title
KR100195855B1 (ko) 소수배 시스템에 있어서 클록 동기 체계
US5914996A (en) Multiple clock frequency divider with fifty percent duty cycle output
US5548620A (en) Zero latency synchronized method and apparatus for system having at least two clock domains
CA2424702C (en) Synchronized multi-output digital clock manager
US5448193A (en) Normalization of apparent propagation delay
KR100380771B1 (ko) 오버샘플링 클럭 리커버리 회로
US6563349B2 (en) Multiplexor generating a glitch free output when selecting from multiple clock signals
US6384647B1 (en) Digital clock multiplier and divider with sychronization during concurrences
JP2008178017A (ja) クロック同期システム及び半導体集積回路
US7236040B2 (en) Method and apparatus for generating multiphase clocks
US20040193931A1 (en) System and method for transferring data from a first clock domain to a second clock domain
JPH10200398A (ja) フェーズロックループ用遅延補償／再同期回路
US6445232B1 (en) Digital clock multiplier and divider with output waveform shaping
US5742799A (en) Method and apparatus for synchronizing multiple clocks
CN1166110C (zh) 压控振荡器
US6477657B1 (en) Circuit for I/O clock generation
US5870592A (en) Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator
US6448915B1 (en) Modulo-M delta sigma circuit
CN1954492B (zh) 在存在抖动时钟源时使时钟发生器同步的方法和装置
KR100513372B1 (ko) 명령 및 어드레스 버스에 사용되는 클럭 신호의 주파수와데이터 버스에 대해 사용되는 클럭 신호의 주파수를다르게 설정하는 서브 시스템
CA2420700C (en) Digital clock multiplier and divider with synchronization
JPH07231223A (ja) 周波数逓倍回路
JPH0693216B2 (ja) 情報処理装置
KR100290592B1 (ko) 클럭분배회로
JP3982095B2 (ja) 位相同期回路

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20021216

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20040219

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20040219

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000