SG67961A1 - Clock synchronization scheme for fractional multiplication systems - Google Patents

Clock synchronization scheme for fractional multiplication systems

Info

Publication number
SG67961A1
SG67961A1 SG1996010871A SG1996010871A SG67961A1 SG 67961 A1 SG67961 A1 SG 67961A1 SG 1996010871 A SG1996010871 A SG 1996010871A SG 1996010871 A SG1996010871 A SG 1996010871A SG 67961 A1 SG67961 A1 SG 67961A1
Authority
SG
Singapore
Prior art keywords
clock synchronization
synchronization scheme
fractional multiplication
multiplication systems
systems
Prior art date
Application number
SG1996010871A
Other languages
English (en)
Inventor
Robert Edward Busch
Kenneth Michael Zick
Robert Maurice Houle
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG67961A1 publication Critical patent/SG67961A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
SG1996010871A 1995-11-28 1996-10-16 Clock synchronization scheme for fractional multiplication systems SG67961A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/563,415 US5691660A (en) 1995-11-28 1995-11-28 Clock synchronization scheme for fractional multiplication systems

Publications (1)

Publication Number Publication Date
SG67961A1 true SG67961A1 (en) 1999-10-19

Family

ID=24250394

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996010871A SG67961A1 (en) 1995-11-28 1996-10-16 Clock synchronization scheme for fractional multiplication systems

Country Status (5)

Country Link
US (1) US5691660A (https=)
KR (1) KR100195855B1 (https=)
CN (1) CN1091977C (https=)
SG (1) SG67961A1 (https=)
TW (1) TW316342B (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802356A (en) * 1996-11-13 1998-09-01 Integrated Device Technology, Inc. Configurable drive clock
DE10059270B4 (de) * 2000-11-29 2012-08-02 Heidelberger Druckmaschinen Ag Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse
US7242229B1 (en) 2001-05-06 2007-07-10 Altera Corporation Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
US6791380B2 (en) * 2001-11-27 2004-09-14 Winbond Electronics Corporation Universal clock generator
US7319728B2 (en) * 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6801070B2 (en) * 2002-05-16 2004-10-05 Micron Technology, Inc. Measure-controlled circuit with frequency control
US7515666B2 (en) * 2005-07-29 2009-04-07 International Business Machines Corporation Method for dynamically changing the frequency of clock signals
GB0622945D0 (en) * 2006-11-17 2006-12-27 Zarlink Semiconductor Inc Fractional digital PLL
WO2008138053A1 (en) * 2007-05-15 2008-11-20 Fiberbyte Pty Ltd Usb based synchronization and timing system
CN101751068B (zh) * 2008-12-09 2012-04-04 华为技术有限公司 一种同步时钟产生电路和方法
CN101938277B (zh) * 2010-08-12 2012-05-30 四川和芯微电子股份有限公司 倍频系统及实现倍频的方法
CN102594451A (zh) * 2012-02-23 2012-07-18 深圳市新岸通讯技术有限公司 一种测试信号的生成方法及装置
CN103064461B (zh) * 2012-12-31 2016-03-09 华为技术有限公司 一种时钟使能信号的产生方法及装置
US10146732B2 (en) * 2013-01-22 2018-12-04 Apple Inc. Time-division multiplexed data bus interface
US9413364B2 (en) * 2014-07-09 2016-08-09 Intel Corporation Apparatus and method for clock synchronization for inter-die synchronized data transfer
WO2019233571A1 (en) 2018-06-05 2019-12-12 Telefonaktiebolaget Lm Ericsson (Publ) Lo phase correction for aas with multiple rfic
CN111679714B (zh) * 2019-12-31 2022-03-11 泰斗微电子科技有限公司 跨芯片信号同步的方法、装置及芯片
EP4375790A1 (en) * 2022-11-25 2024-05-29 LX Semicon Co., Ltd. Device and method for multi-chip clock synchronization
CN116320098A (zh) * 2023-03-07 2023-06-23 北京旋极信息技术股份有限公司 一种时钟信号的生成方法、时钟装置和信号处理系统

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053839A (en) * 1973-05-29 1977-10-11 Knoedl Jr George Method and apparatus for the frequency multiplication of composite waves
US3970954A (en) * 1975-04-03 1976-07-20 Bell Telephone Laboratories, Incorporated Digital frequency multiplier
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
US4405898A (en) * 1980-06-30 1983-09-20 International Business Machines Corporation Pseudo synchronous clocking
US4598257A (en) * 1983-05-31 1986-07-01 Siemens Corporate Research & Support, Inc. Clock pulse signal generator system
US4725786A (en) * 1984-07-26 1988-02-16 Comstron Corporation Full-octave direct frequency synthesizer
US4663541A (en) * 1985-03-18 1987-05-05 Environmental Research Institute Of Michigan Phase-shift stabilized frequency multiplier
US4845437A (en) * 1985-07-09 1989-07-04 Minolta Camera Kabushiki Kaisha Synchronous clock frequency conversion circuit
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5241543A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Independent clocking local area network and nodes used for the same
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
US5077686A (en) * 1990-01-31 1991-12-31 Stardent Computer Clock generator for a computer system
US5208838A (en) * 1990-03-30 1993-05-04 National Semiconductor Corporation Clock signal multiplier
US5245322A (en) * 1990-12-11 1993-09-14 International Business Machines Corporation Bus architecture for a multimedia system
US5175731A (en) * 1990-12-11 1992-12-29 International Business Machines Corporation Arbitration circuit for a multimedia system
US5230041A (en) * 1990-12-11 1993-07-20 International Business Machines Corporation Bus interface circuit for a multimedia system
US5361367A (en) * 1991-06-10 1994-11-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
EP0522720B1 (en) * 1991-06-18 1999-08-18 Nokia Mobile Phones Ltd. Clock frequency adjustment of an electrical circuit
FI88837C (fi) * 1991-08-15 1993-07-12 Nokia Mobile Phones Ltd Frekvensdividering med udda tal och decimaltal
US5281863A (en) * 1992-03-26 1994-01-25 Intel Corporation Phase-locked loop frequency-multiplying phase-matching circuit with a square-wave output
US5394114A (en) * 1992-04-30 1995-02-28 National Semiconductor Corporation One nanosecond resolution programmable waveform generator
US5544203A (en) * 1993-02-17 1996-08-06 Texas Instruments Incorporated Fine resolution digital delay line with coarse and fine adjustment stages
WO1996025796A1 (en) * 1995-02-17 1996-08-22 Intel Corporation Power dissipation control system for vlsi chips
US5548249A (en) * 1994-05-24 1996-08-20 Matsushita Electric Industrial Co., Ltd. Clock generator and method for generating a clock
US5537068A (en) * 1994-09-06 1996-07-16 Intel Corporation Differential delay line clock generator

Also Published As

Publication number Publication date
CN1152822A (zh) 1997-06-25
KR100195855B1 (ko) 1999-06-15
KR970031357A (ko) 1997-06-26
US5691660A (en) 1997-11-25
TW316342B (https=) 1997-09-21
CN1091977C (zh) 2002-10-02

Similar Documents

Publication Publication Date Title
SG67961A1 (en) Clock synchronization scheme for fractional multiplication systems
AU126709S (en) Watch
GB9716969D0 (en) Watch holder system
GB2296166B (en) Clock synchronisation
EP0809160A4 (en) RADIO-APPROVED CLOCK
GB9601348D0 (en) Clock synchronisation
EP0772133A3 (en) System for data synchronization
SG119130A1 (en) Timepiece
GB9506309D0 (en) Pyrimidine compounds
GB2287812B (en) Clock divider
BR9605830A (pt) Multiplicador de relógio
EP0657797A3 (en) Clock distribution system for synchronous circuit arrangements.
GB2333385B (en) Variable clock apparatus
GB2302237B (en) Synchronous clock for digital exchange
GB9519814D0 (en) Clock
GB2308206B (en) Clock
GB2298512B (en) Future clock
GB9322609D0 (en) Clock synchronisation
GB2301994B (en) Apparatus for minimizing clock skew
GB2297404B (en) Media synchronization
GB2308028B (en) Clock generator
GB9524462D0 (en) Clocks
AU131679S (en) Shield clock
CA75819S (en) Watch
CA79710S (en) Watch