GB2301994B - Apparatus for minimizing clock skew - Google Patents

Apparatus for minimizing clock skew

Info

Publication number
GB2301994B
GB2301994B GB9610706A GB9610706A GB2301994B GB 2301994 B GB2301994 B GB 2301994B GB 9610706 A GB9610706 A GB 9610706A GB 9610706 A GB9610706 A GB 9610706A GB 2301994 B GB2301994 B GB 2301994B
Authority
GB
United Kingdom
Prior art keywords
clock skew
minimizing clock
minimizing
skew
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9610706A
Other versions
GB2301994A (en
GB9610706D0 (en
Inventor
Brian D Alleyne
Jae-Won Lee
Jun-Gyu Lee
Sung-Min Song
Gyu-Suk Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9610706D0 publication Critical patent/GB9610706D0/en
Publication of GB2301994A publication Critical patent/GB2301994A/en
Application granted granted Critical
Publication of GB2301994B publication Critical patent/GB2301994B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
GB9610706A 1995-06-07 1996-05-22 Apparatus for minimizing clock skew Expired - Fee Related GB2301994B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US48239495A 1995-06-07 1995-06-07

Publications (3)

Publication Number Publication Date
GB9610706D0 GB9610706D0 (en) 1996-07-31
GB2301994A GB2301994A (en) 1996-12-18
GB2301994B true GB2301994B (en) 1997-08-06

Family

ID=23915894

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9610706A Expired - Fee Related GB2301994B (en) 1995-06-07 1996-05-22 Apparatus for minimizing clock skew

Country Status (4)

Country Link
JP (1) JPH09167038A (en)
KR (1) KR970002691A (en)
CN (1) CN1101097C (en)
GB (1) GB2301994B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6539509B1 (en) * 1996-05-22 2003-03-25 Lsi Logic Corporation Clock skew insensitive scan chain reordering

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1537437A (en) * 1976-09-27 1978-12-29 Honeywell Inf Systems Electronic apparatus
EP0256698A2 (en) * 1986-08-06 1988-02-24 E.I. Du Pont De Nemours And Company Bus structure having constant electrical characteristics
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
WO1993018463A1 (en) * 1992-03-06 1993-09-16 Rambus, Inc. Method and circuitry for minimizing clock-data skew in a bus system
US5446410A (en) * 1992-04-20 1995-08-29 Matsushita Electric Industrial Co.,Ltd. Semiconductor integrated circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228823A (en) * 1985-07-31 1987-02-06 Toshiba Corp Signal switching circuit
JPH0371798A (en) * 1989-08-11 1991-03-27 Hitachi Ltd On-vehicle reproducing device
JPH04344511A (en) * 1991-05-22 1992-12-01 Nec Commun Syst Ltd Live wire attaching/detaching system
JPH06274253A (en) * 1993-03-24 1994-09-30 Matsushita Electric Ind Co Ltd Rack device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1537437A (en) * 1976-09-27 1978-12-29 Honeywell Inf Systems Electronic apparatus
EP0256698A2 (en) * 1986-08-06 1988-02-24 E.I. Du Pont De Nemours And Company Bus structure having constant electrical characteristics
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
WO1993018463A1 (en) * 1992-03-06 1993-09-16 Rambus, Inc. Method and circuitry for minimizing clock-data skew in a bus system
US5446410A (en) * 1992-04-20 1995-08-29 Matsushita Electric Industrial Co.,Ltd. Semiconductor integrated circuit

Also Published As

Publication number Publication date
CN1101097C (en) 2003-02-05
KR970002691A (en) 1997-01-28
CN1149238A (en) 1997-05-07
GB2301994A (en) 1996-12-18
GB9610706D0 (en) 1996-07-31
JPH09167038A (en) 1997-06-24

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080522