TW309656B - - Google Patents

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TW309656B
TW309656B TW085102621A TW85102621A TW309656B TW 309656 B TW309656 B TW 309656B TW 085102621 A TW085102621 A TW 085102621A TW 85102621 A TW85102621 A TW 85102621A TW 309656 B TW309656 B TW 309656B
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calendar
insulation
concentration
teos
degrees
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Hyundai Electronics Ind
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • C23C16/402Silicon dioxide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Description

303656 A7 B7 五、發明説明( 經濟部中央標準局貝工消費合作社印製 <發明领域> 本發明是有關於形成半寒賊元件的方法,尤其是有關 於在具有多曆結檷之金屬互連的半導Μ元件內形成內金羼 絕緣曆的方法。 <習知技越說明> 因為半導嫌元件的積艚化程度老是不斷地播加,所以 半導艚元件就爾要具備多曆的金羼互埋〇在製造半導《9元 件時,在同一曆的金雇線之間的空間和在兩暦之間的空間 應該要由內金屬絕緣曆來做絕緣,此内金屬絕緣曆是介雷 質的材料,例如氣化物或氮化物。高品質的内金雇絕緣曆 需要有下列特性:要有防水性;對金钃互連要有高附蕃性 ;而且要有均匀的步階覆蓋性。最近被用來當作内金屬絕 緣雇的有硼碗鞋酸鹽玻拥(BPSG),旋塗式玻觸(SOGj ,以 及原砂酸四乙酯(TE0S)。 當使用BPSG作為内金屬絕緣靥時*需要額夕卜的回流步 驟。因此,在該層事先決定好的位置内部就會有形成空隙 的問題。另一方面,當使用S0G作為内金靥函緣曆時*會 因為水分的滲入而導致對金屬互連的腐触◊其原因在於該 曆本身就具有大量的水分,且其在金羼靥上的附蕃力也不 強。 除了上述材料以外,通有一種使用TE0S臢來作為涵緣 曆的方法被發表出來。此方法是以原砂酸四乙酿(TE0S)氣 艘和0。氣艚一起反應而形成TE0S膜。因為TE0S膜增加了表 kJ 面反應的效果,所Μ此方法可以很容黑地填滿在金屬線之 3 - 本紙張尺度適用中困國家橾準(CNS ) A4规格(210X297公釐) ----------ΟΙ — # m (請先閲讀背面之注$項再填寫本頁) 303656 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明() 間的空間,但是所形成的TEOS膜會包含大量的水分,而且 該曆本身也可Μ從空氣中吸收水分。存在水分中的氫櫬會 潑透到金靥互連的表面*而導致所形成之曆的壓力變化。 如果變化很劇列•所形成之曆就會断裂。 <發明總論> 因此,本發明的目的是要提供在半導鼸元件上形成内 金靥絕緣靥的方法,此方法不僅具有較優越的附蕃性和均 勻的步階覆Μ *而且邋可Μ避免因為水分潑透而產生空隙。 要達成本發明的目的,苜先要在半導艚基座上形成金 靥互連。然後,形成第一緣層,其厚度要能夠足以填滿在 該曆中金靥互連的任兩條線之間的空間。此緣曆本身是在 CVD爐中Μ事決定好瀰度的原砂四乙酿(TEOS)和事先決定 好濃度的03氣艚在一起反應*而形成的。接下來,在第一 絕緣曆上Μ使用相同的爐子而只改變TEOS濃度的方法來形 成一個事先決好厚度的第二絕緣曆〇 在形成第一絕緣曆時,比較好的播揮是使用3.0到5.0 重最莫耳濃度的〇3攝氏360到420度的沈積通度,以及1.0 至(12.0個si pm的TE0S濺度。此外,在形成第二緣曆時, 比較好的選擇是使用3.0到5.0重量莫耳濃度的03,攝氏360 至(J420度的沈積溫度,Μ及少於1.0到2,0個si pm的TE0S濃 度0 就厚度而言,第一絕緣曆的厚度M6000埃或更厚為較 佳的選擇,而第二緣曆的厚度M1000換或更薄為較佳的選 擇0 一 4 — (請先閲讀背面之注意事項再填寫本頁) .-ο. 訂 本紙張尺度適用中國國家梯準(CNS ) A4规格(210X297公釐) 309656 A7 _B7_ 五、發明説明() <圆式之簡單說明> 第1圓是個圓表,此表顯示了量測所形成之TEOS膜的 物理性質的實驗結果,Μ找出形成第一絕嫌朦時的最合適 條件。 第2圓是顬示膜厚随沈積時間不同而變化的關彳系圓, 其形成溫度是攝氏390度* TEOS無維的補充量是1.3slpm, 而所給的0。的_度是毎立方米130克。 Ο 第3圖是顯示當TE0S氣赖的補充量固定在1.3s Ipb且0 3 的灘度視形成之溫度而改變時•沈積膜之沈積速率的闞係 圖。 第4圃是顯示TE0S膜的沈積逋率随TE0S氣《I補充量變 化的鼷係圃。 第5_是一半導黼元件的SEM顬微彩片,其内金靥絕緣 靥是根據本發明之具髁實例而形成的。 <較佳具體實例之詳細描述> 在下文中,將會描述本發明的較佳具體實例,但是不 應該將其解釋成本發明之精神的限觸範圃。 經濟部中央標準局員工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 在本發明中*用來隔絕金靥互缠的涵靥被分為兩部份 。也就是說,有一個第一絕緣曆,其目的是用來完全填滿 在某一曆金靥互連之金雇線之間的空間* Μ及一個第二絕 緣靥,其目的是用來覆蘧金屬互連和第一絕緣曆。道兩層 絕緣曆因為其形成的條件不同而具有不同的性質。 以下再對本發明作更詳畑的描述。 首先在一半導賊基座上透過沈積法而形成金屬互連的 -5 - 本紙張尺度適用中國國家橾準(CNS ) Α4規格(210Χ297公釐) 經濟部中央樣準局員工消費合作社印製 A7 B7 _ 五、發明説明() 跚案。然後,侬序地以化學氣相沈稹法來使TEOS氣體和0 3 氣體反懕,而形成第一和第二絕緣曆。 TEOS氣艘是形成絕緣曆的材料來源之-一。 在形成上述第一絕緣曆時,是使用3.0到5.0重量奠耳 湄度的03,攝氏360到420度的沈積溫度,Μ及1.0到2.0個 s lpm的TE0S濃度。第一絕緣曆最好是完全填滿在某一曆金 靥互連之金屬線之間的空間,Μ请強成維持此半導體元件 的性質。在本具髓實例中*第一絕緣層的厚度是6000埃。 接下來,在第一絕緣層上形成一曆事先決定好厚度的 第二絕緣曆,其中第二絕緣曆具有與第一絕緣曆不同的物 理性質。為了使元件與存在空氣中之水分接觴的櫬會減到 最小,形成第一絕緣曆的反應爐具與形成第二絕緣曆的反 應爐具最好是同一個。 除了 TE0S的濃度Μ外,第二絕緣曆的形成條件應該與 第一絕緣靥的相同。也就是說•使用3.0到5.0重量莫耳濃 度的03,攝氏360到420度的沈積瀣度,逋座和第一絕緣層 的相同* Μ及等於或少於0.5個slpra的TE0S壤度,逭個量 比第一絕緣曆的少。第二絕緣曆的厚度應該控制在1000埃 或更薄。 (實例) 第1圖是顯示量測所形成之TE0S膜的物理性質之圓表 ,以找出形成第一絕緣曆的合通條件。 為了要形成具有6000埃之厚度的一絕緣曆,我們分別 採用下列條件;形成溫度是攝氏360,390,和420度,TE0S 氣艘的補充量是1.3,2.3和3.3 slpm,而0 3灞度是每立方 —6 — 本紙張尺度適用中國國家標準(CNS > Α4規格(210Χ297公釐) (請先閲讀背面之注意事項再填寫本頁) ‘·
,1T 309656 A7 _B7________ 五、發明説明() 米70克(等於3.27個重量莫耳瀰度)*每立方米100克(等於 4.66個重量萁耳瀟度)。 在上述條件之下,為了要得到壓力變化的比率,就要 測量所形成之第一絕緣曆在此厚度下的懕力與鏞減速率。 此外,沈積厚度、統一度、每分鐘的沈積速率、反射係數 (R. I)、平面度、以及一致度都要測最。 其結果如下:在攝氐420度高溫有百分之1.3到1.4的低 歷力變化率:在攝氏420度高溫有百分之17到24的高壓力變 化率與大約百分之0.5的低厚度縮減速率;而在攝氏360度 和390度有在百分之0.2之内的超低揮:度錢f減速率。當TE0S 濃度為1.3 slpm且沈積溫度為攝氐360度和420度時,第一 絕緣曆的獅減速率_03濃度而變,如下文所示。 對沈積溫度為攝氏360度而0 3濃度為每立方米70克, 100克,和130克而言,縮減速率分別是百分之1.60,1.23 ,和1.86。此夕卜,對沈積溫度為攝氐420度而〇3禳度為每 立方米70克,100克,和130克而言*獅減速率分別是百分 之0.35,0.12,和0.52。因此,當03漉度為每立方张130 克時,變化速率是相對較高值。 經濟部中央樣準局負工消费合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 從上述結果看來,在03濃度是每立方米130克的例子 中,因為在所形成的那一靥中存在大量的水分,所以那一 曆必然是有許多孔的。因為絕緣曆的組成原子要緊密結合 ,才會具有優越的物理特性。因此,03濃度是每立方米130 克的例子被排除在本發明之最合遽的範_之外。 此外,為了要決定在沈積溫度為播氐390度且03濃度 -7 - 本紙張尺度適用中國國家揉準(CNS ) A4规格(210X297公釐)~~" 經濟部中央標準局貝工消費合作社印裝 A7 B7 _ 五、發明説明() 為每立方米100克的情況之下TEOS氣賊的合通補充量,我 們試了 1.3,2.3 *和3.3 slpni的TE0S氣艘之補充最,其厚 度縮減速率分別為百分之0.52 * 1.20,和1.50。此结果顯 示TE0S濃度為2.3,3.3 slpnt時具有比TE0S濃度為1.3slpm 時更多的孔,這是因為前者比後者具有更大量的水分。因 為絕緣靥的組成原子要緊密結合•才會具有優越的物理特 性。因此,2.3,和3.3slpmSU例子被除在本發明之最合適 的範圃之外。 大部分使用在本發明的實例都傾向賴用6000埃的厚度 是百分之0.89到2.59的值。在沈積溫度為攝氏390度,TE0S 氣體補充量為3.3 slpm,瀟度為4.66重量奠耳濃度的例子 中,沈積速率是最高值。當第一絕緣曆沈積在基座上時的 反射係數與經過退火30分鐮後的反射係數幾乎一樣。平面 度的範園從百分之10到百分之41,而其最高值出現在沈積 溫度為攝氐420度時。此外,圃中邐有顯示出TE0S氣級補 充董為1.3s lpm與03濺度為4.66重量莫耳濺度的情況。 第2圃是顯示膜厚随沈積時間不同而變化的鼷係圓, 其形成溫度是攝氏390度,TE0S氣體的補充量是1.3s1pib, 而所給的的瀰度是每立方米130克。 如在第2跚中所示地,沈稹厚度随沈積時間的靖加而 圼線性地谢加。由此结果,我們可Μ確定:要獲得6000埃 或更多的厚度所必需的沈稹時間至少是560秒或更多。 第3圈是顳示當TE0S氣Μ的濃度固定在1.3slpm且03的 漉度視形成之溫度而改變時,沈積膜之沈積速率的關係圃。 一 8 一 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公嫠) ---------Mt, -- (請先閲讀背面之注意事項再填寫本頁) 訂
Μ濟部中央櫺準局負工消资合作社印裝 五、發明说明().. 如在第3圖中所示地’常〇 3的濃度增加’每分鐘的沈 椒速第就會下降。此外,跚中還顯示了在:所給的淵度範_丨 内,在高溫下的沈積速樂比在低溫下的沈横率遵高° 第4 _提顯示TEOSim的沈積速率随TKOS佩體補充撮變 化的關协屬丨.如在窮4關中所沿地,常TKOS的嫌減少時’ 沈憒速莖就會里線性下降·· 第5_® -半導體元件的SEM顯微影片·其内金牖絕緣 臌提根據本發明之具體實例而形成的° 如在此圖中所乐地,我們可以知道並沒有彳数候顯示有 形成之皭中,就如同傳統技越的悄況―櫬。 如先前所詳細描述的,本發明之内金龎絕緣曆趙·由兩 躕絕緣躐所組成,此兩®有互不相同之性質。此外,它們 的物理性質不僅在合適的範圆之内,而且它們可Μ避免水 分的滲透。因此,本發明可以將空隙的產生與/i,力的變化 減到最少饊,此壓力變化昼在半導體元件中造成失敗與不 可餚度的主要來源。此外,本發明遝具有一種效果,就是 它不懺獻抑了空:隙的產生,而且遢增加了製造時的良率, 這是闲為兩廇絕緣®都在間一ί®慽子裡形成的錄故。 那搜熟悉尋常技越者在讓通先前所揭蕊的内容之後, 將會很容晃地就對在此所揭露之本發明的其他特性,優點 和具體實例非常明腺。關於這方面,猶本發明的棠些特定 之具體實例在做相當詳綑的描述時,可Μ在不離開本發明 所描述興哨猜專利的稍神與範剛之下,對遗些具體實例做 -座改變與修正。 一 9 一 本紙伕尺度適用中國國家榡準(CNS Μ4規格(2丨0X297公茇) ---------1-裝------訂-------線 (請先閲讀背而之注意事項再填寫本頁)

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  1. 經濟部中央標率局身工消费合作社印装 309656 H C8 D8 _ 六、申請專利範圍 1. 一種在半導體元件内形成内金鼷絕緣曆的方法,包含 下列步驟: 在半導艘基座上形成金屬互連; 藉由使事先決定好數量之原砂酸四乙酿與事先決定好 數量之氣艘在化學氣相沈積爐中反懕*而形成一能夠充 分填滿在金屬互連之間之空間的第一絕緣曆; 在第一絕緣曆上形成一事先決定好厚度的第二絕緣曆 ,與第-·絕緣曆的條件比起來,第二絕緣曆僅改變了 TEOS 的濃度。 2. 如申請專利範圏第1項之方法》其中所述之第一絕緣 曆是在03«度為3.0到5.0重量莫耳濃度,沈積溫度為 攝氏360度至U420度,Μ及TE0S濃度為1.0到2.Os 1pm的 條件下形成的。 3. 如申讁專利範園第1項之方法,其中所述之第二絕緣 曆是在03濃度為3.0到5.0簠量莫耳濃度,沈積湩度為 攝氐360度到420度,Μ及TE0S濃度為少於0.5 slpm的 條件下形成的。 4. 如申請専利範園第1項之方法,其中所述之第一與第 二絕緣曆的厚度分別為6000埃或更厚些,以及1〇〇〇埃 或更薄些。 _ 10 - 本紙張尺度逋用中國國家榡準(CNS > A4規格(210X297公釐) (請先閲讀背面之注意Ϋ項再填寫本頁) -裝· 訂
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GB2298658B (en) 1998-07-29
JP3026154B2 (ja) 2000-03-27
US5804509A (en) 1998-09-08
DE19608209A1 (de) 1996-10-17
KR960035967A (ko) 1996-10-28
GB9604622D0 (en) 1996-05-01

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