TW302549B - - Google Patents
Download PDFInfo
- Publication number
- TW302549B TW302549B TW085102982A TW85102982A TW302549B TW 302549 B TW302549 B TW 302549B TW 085102982 A TW085102982 A TW 085102982A TW 85102982 A TW85102982 A TW 85102982A TW 302549 B TW302549 B TW 302549B
- Authority
- TW
- Taiwan
- Prior art keywords
- oxide film
- film
- patent application
- flash eeprom
- item
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 239000004576 sand Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 210000004709 eyebrow Anatomy 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 2
- 230000002079 cooperative effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
302549 經濟部中央標準局員工消费合作社印製 B7 五、發明説明(/ ) 發明領域: 本發明係_於一種快閃EEPROM細胞元及其製法,尤指一種分 離閘極型的快閃EEPROM細胞元及其製法,可以隔開隧道區和通 道,以改善元件的可靠性。 發明背景: 一般來說,在製造半導体元件的製程中,同時具有電子程式化 和拭除功能的快閃EEPROM (電子拭除式可程式唯讀記憶体)細胞 元可以分爲二種結構:堆叠閘極結構和分離閘極結構。 如圖1A,傳統堆叠閘極型快閃EEPROM細胞元的結構中,隧 道氧化膜5、浮動閘極6、複晶矽之間的氧化膜11和控制閘極12連 續堆叠在汲極區7和源極區8之間的矽基板1上。 如圖1B,傳統分離閘極型快閃EEPROM細胞元的結構中,隊 道氧化膜5、浮動閘極6、複晶矽之間的氧化膜11和控制閘極12連 緬形成在汲極區7和源極區8之間的矽基板1上,而且在此結構 中,控制閘極12堆叠結構中的上層並向源極區8延展。此延展的控 制閘極12下方的矽基板1則爲選擇閘極通道區9。 雖然堆叠閘極結構與分離閘極結構相較之下*可以縮小毎細胞 元的面積,具有提高元件密度的優點,在拭除時卻容易過度拭除。 但即使分離閘極結構可以克服堆疊閘楹結構的缺點,因爲它毎細胞 元的面積仍大於堆叠閘極型的結構,就無法提高元件的密度。 而且,無論是堆叠閘極型或分離閘楹型的快閃EEPROM細胞 元,進行程式化和拭除的功能時都必須對細胞元施以高壓。當使用 高壓進行程式化和拭除功能時,接面區和閘楹之間的重叠區域會形 成強烈的電場,引發出頻帶對頻帶的穿隧效應和次級熱電子。但因 睡道氧化膜通常厚度約100埃,頻帶對頻帶的穿隧效應和次級熱載 J--·-----ί I裝------訂-----線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS > Α4規格(210X297公釐) 經濟部中央樣準局員工消費合作社印裝 A7 __B7_
五、發明説明(二J 子會破壞這眉隨道氧化膜,而降低了元件的可靠性。 發明的籣要說明: 本發明的目的是要提出一種快閃EEPROM細胞元及其製法,可 以降低高壓對隧道氧化膜的破壞,同時解決細胞元拭除時過度拭除 的問題。 爲了達成以上的目的,本發明快閃EEPROM細胞元的方法,其 步驟係包含: 連續沈積第一氧化膜和氮化膜,然後以光阻圖案作爲蝕刻光 罩,透過触刻製程去除部份的第一氧化膜和氮化膜,並露出部份的 矽基板。 去除光阻圔案,然後氧化露出表面部份的矽基板,形成第二氧 化膜; 以去除部份後的氮化膜作爲蝕刻光罩,去除底下露出的第二氧 化膜,在所去除第二氧化膜之處的矽基板表面形成一凹陷部份,同 時由去除部份後留下的氮化膜所覆蓋的第二氧化膜則保留下來; 在矽基板的凹陷部份形成汲極區; 在矽基板的凹陷部份形成隨道氧化膜,然後在整個結構上形成 第一複晶矽雇; 以浮動閘棰的光罩,利用蝕刻製程連纜去除第一複晶砂層、已 除去部份留下的氣化膜、睡道氧化膜和已除去部份留下的第一氧化 膜,形成第一複晶砂製成的浮動閘棰; 植入控制臨界電壓的雜質,在浮動閘極一側的矽基板上形成選 擇閘楹通道區; 形成選擇閘極氧化膜和複晶矽之間的氧化膜,然後在整個結構 上形成第二複晶败雇;以及 本紙張尺度適用中國國家標準(CNS ) A4規格(210X.297公釐) ~ [--k-----( ·裝------訂------ {請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣隼局員工消費合作社印製 302549 五、發明説明(彡) 以控制閘極的光罩,利用蝕刻製程制定第二複晶矽層的圖案, 形成分離形的控制閘極結構,然後在控制閘極一邊露出的矽基板上 形成源極。 本發明之快閃EEPROM細胞元係包含: 一面矽基板,上有凹陷部份; 汲極區,位在矽基板的凹陷部份; 源極區,位在遠離汲極區的矽基板上; 浮動閘極,覆叠在汲極與源極區之間的部份破基板上,並覆叠 在部份的汲極區上,以一薄絕緣膜與汲極區電性隔離,而以一厚絕 緣膜與矽基板隔開;以及 控制閘極,延展至源極的邊緣部份,以氧化膜分別與浮動閘極 和砂基板隔開。 附圖的簡要說明: 爲了能夠更完全地瞭解本發明的內容和目的,底下將參照附圖 詳加說明,所附附圖分別爲: 圖1A是傳統堆疊閘極型快閃EEPROM細胞元的橫剖面圖。 圖1B是傳統分離閘極型快閃EEPROM細胞元的橫剖面圖。 圖2A至2H的元件橫剖面圓說明依據本發明製造快閃EEPROM 細胞元的方法。 圖3A和3B的狀態圈說明本發明之快閃EEPROM細胞元的操作 方式。 各附圖中相同的編號均代表相同的組件。 發明的詳細說明: 底下將參照附圖,詳細說明本發明。
圖2A至2H的元件橫剖面圖說明依據本發明製造快閃EEPROM 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I---------f ·裝------訂------ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標率局員工消费合作社印装 五、發明説明(卜) 細胞元的方法。 圖2A中,先在矽基板1上連續形成第一氧化膜2和氮化膜 3,然後利用光阻圖案10作爲蝕刻光罩,透過蝕刻製程去除部份的 第一氧化膜2和氮化膜3,露出部份的矽基板1。第一氧化膜2在 矽基板1上的厚度約爲150至250埃,而氣化膜3在第一氧化膜2上 的厚度約爲400至600埃。 圖2B中,去除光阻圈案10後,氧化露出表面部份的矽基板1, 形成厚度約1500至2500埃的第二氧化膜4。 圈2C中,以去除部份後留下的泡化膜3作爲蝕刻光罩,利用乾 蝕刻製程去除第二氧化膜4露出的部份。當去除第二氧化膜4露出 的部份之後,會在矽基板〗的表面上留下一個凹陷部份,但氮化膜 3所覆蓋住的第二氧化膜4則被保留下來。 圖2D中,在矽基板1的凹陷部份植入高濃度的N型雜質離 子,並且進行回火,形成汲極區8A。 圖2E中,先在矽基板1露出的部份上形成厚度約80至120埃的 隆道氧化膜5A,然後在整個結構上形成第一複晶矽層16。 圖2F中,用浮動閘極的光罩,轔由乾蝕刻製程連鑕制定各眉的 圖案,包括第一複晶矽16、氮化膜3、隧道氧化膜5A和第一氧化 膜2。第一複晶矽16制定圖案後就成了浮動閘極16A。由圈2F還可 看到,以汲極區8A中心部份爲主的兩側各有一個浮動閘極16A。 圖2G中,在浮動閘極16A外側露出的矽基板1上植入控制臨界 電壓雜質離子,而形成選擇閘極通道9A。 圖2H的元件横剖面圖中,接著在形成選擇閘楹通道9A之後, 在整個結構上同時成長選擇閘楹氧化膜13和複晶矽之間的氧化膜 11A。然後形成第二複晶砂層,並用乾蝕刻製程以控制閘棰的光罩 (請先閱讀背面之注意事項再填寫本頁) •裝. ,ιτ 本紙張又度適用中國國家榡準(CNS ) Α4规格(210X297公釐) A7 B7 五、發明説明(y) 制定第二複晶矽眉的圖案,在兩個浮動閘極16A上各形成一個控制 閙極12。然後植入高濃度的N型雜質離子,在兩個控制閘極,12之外 的矽基板1上各形成一個源極區7A。 經由上述的製程步驟,即完成兩個共有汲極區8A的快閃 EEPROM細胞元。 根據本發明製造的快閃EEPROM細胞元,其結構包含:一面矽 基板1,上有凹陷部份;汲極區8A,位在矽基板1的凹陷部份; 源極區7A,位在遠離汲極區8A的矽基板1上;浮動閘極16A,覆 疊在汲極區8A和源極區7A之間的部份矽基板1上,並覆疊在部份 的汲極區8A上,同時以一薄絕緣膜與汲極區8A隔開,而以一厚絕 緣膜與矽基板1隔開;控制閘極12,覆蓋住浮動閘極16A,並延展 至源極7A和邊緣部份,以氧化膜分別與浮動閘極16A和矽基板1隔 開° 以上所述薄絕緣膜是隧道氧化膜,厚度約80至120埃,而厚絕 緣膜係由沈積厚度約150至1000埃的絕緣材料所形成。 現在將參照附圖3A和3B,說明本發明之快閃EEPROM細胞元 的操作原理。 圖3A和3B的狀態圖說明本發明之快閃EEPROM細胞元的操作 方式。 圖3A是快閃EEPROM細胞元進行程式化時的狀態圖。 若對矽基板1上的控制閘極12施加約12V的高壓,而使源極區 7A和汲極區8A接地,在汲極區8A和浮動閘極16A之間的隧道氧化 膜5A會因高電場而引發福勒一諾罕(fowler-nordheim)穿隧效應,致 使電子在浮動閘極16A充電,而完成了程式化的動作。 圖3B是快閃EEPROM細胞元拭除操作時的狀態圖。 (請先閲讀背面之注意事項再填寫本頁) : 、? 經濟部中央揉準局員工消费合作社印製 本紙張尺度遑用中國國家橾準(CNS ) A4规格(210X297公釐) A7 B7 五、發明説明(L) 若對矽基板1上的汲極區8A施加約12V的高壓,而使源極區7A 和控制閘極12接地,原先因汲極區8A和浮動閘極16A之間的高電場 引發福一諾罕穿隧效應而在浮動閘極16A充電的電子又會在隧道氧 化膜5A放電,而完成了拭除的動作。 正如以上說明,本發明之分離閘極型快閃EEPROM細胞元中, 隧道區由一厚絕緣膜與通道區隔開,當對結構施加高壓進行程式化 和拭除等操作時,接面區與閘極的重叠區域的高電場所引發的頻帶 對頻帶穿隧效應和次級熱載子,就不致破壞細胞元的隧道氧化膜, 也能避免驅動細胞元時的過度拭除。 以上雖然透過較佳實施例詳加說明,但僅爲了說明本發明的原 則與精神,不應視爲本發明只限於所揭露和說明的較佳實施例。因 此,所有在本發明範圍和精神之內所作細節上的修改都應視爲本發 明進一步的實施例。 1^1 ^^1 —I— n-i ^^1 ^ - (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央橾準局員工消费合作社印製 本紙浪尺度適用中國困家梂準(CNS ) A4规格(210 X 2的公釐)
Claims (1)
- A8 B8 C8 D8 六、申請專利範圍 — 1. 一種製造快閃電子拭除式可程式唯讀記憶体(EEPROM)的方法, 其步驟係包含: 在一面砂基板上連緬沈積第一氧化膜和氮化膜,然後以光阻 圖案作爲光罩,透過蝕刻製程去除部份的第一氧化膜和氮化膜, 並露出該矽基板的一部份; 去除該光阻圈案後,氧化該露出的矽基板部份,形成第二氧 化膜; 以該已部份去除所留下的氮化膜作爲蝕刻光罩,去除該第二 氧化膜露出的部份,在去除該第二氧化膜之處的矽基板表面上形 成一凹陷部份,而由該已部份去除所留下的箱化膜所覆蓋的第二 氧化膜則保留下來; 在該砂基板的凹陷部份形成汲極區; 在該矽基板的凹陷部份形成隧道氧化膜,然後在整個結構上 形成第一複晶矽層; 以浮動閘極的光罩,利用蝕刻製程連績去除該第一複晶砂 雇、該已部份去除所留下的氮化膜、該睡道氧化膜和該已部份去 除所留下的第一氧化膜,形成由該第一複晶败製成的浮動閘極; 經濟部中央揉芈局貝工消費合作社印装 (請先閲讀背面之注意事項再填寫本頁) 植入控制臨界電壓的雜質,在該浮動閘極一側的矽基板上形 成選擇閘極通道區; 形成選擇閘楹氧化膜的複晶矽之間的氧化膜,然後在整個結 構上形成第二複晶矽雇;以及 以控制閘極的光罩,利用蝕刻製程制定該第二複晶矽眉的圈 案,形成分離型的控制閘楹結構,然後在該控制閘極一側露出的 矽基板上形成源極〇 2. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 本紙張尺度逋用中國國家橾準(CNS ) A4规格(210X297公釐) 302549 cs ___ D8 六、申請專利範圍 法,其中該第一氧化膜厚度約150至250埃。 3. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 法,其中該第二氧化膜厚度約1500至2500埃。 4. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 法,其中該親化膜厚度約400至600埃。 5. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞的方法, 其中該隊道氧化膜厚度約80至120埃。 6. _種快閃EEPROM細胞元,係包含: 一面砂基板,上有凹陷部份; 汲極區,位在該砂基板的凹陷部份; 源極區,位在遠離該汲極區的矽基板上; 浮動閘極,覆叠在該汲極與源極區之間的部份砂基板上,並覆叠 在該汲極區的一部份,該浮動閘極以一薄絕緣膜與該汲極區電性 隔離,而以一厚絕緣膜與該矽基板隔開;以及 控制閘極,覆蓋住該浮動閘極,並延屬至該源極的邊緣部份,並 以一氧化膜分別與該浮動閘極和矽基板隔開。 7. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其中 該薄絕緣膜係一隧道氧化膜。 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 8. 根據申請專利範園第7項所述之製造快閃EEPROM細胞元,其中 該隧道氧化膜厚度約80至120埃。 9. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其中 該厚絕緣膜係由沈積厚度約150至1000埃之絕緣材料所形成。 10. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其 中該厚絕緣膜是由氧化膜和氮化膜形成的褸合結構。 11. 根據申請專利範圍第10項所述之製造快閃EEPROM細胞元,其 本紙張尺度逋用中國团家標準(CNS > A4规格(210X297公釐〉 A8 B8 C8 D8 ττ、申請專利範圍 中該氧化膜厚度約150至250埃。 12.根據申請專利範圍第10項所述之製造快閃EEPROM細胞元,其 中該氮化膜厚度約400至600埃。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局負工消費合作社印製 本紙張尺度逋用中國國家橾準(CNS > Α4规格(210X297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950005204A KR0142603B1 (ko) | 1995-03-14 | 1995-03-14 | 플래쉬 이이피롬 셀 및 그 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW302549B true TW302549B (zh) | 1997-04-11 |
Family
ID=19409737
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085102982A TW302549B (zh) | 1995-03-14 | 1996-03-12 |
Country Status (4)
Country | Link |
---|---|
US (2) | US5652161A (zh) |
KR (1) | KR0142603B1 (zh) |
CN (1) | CN1060590C (zh) |
TW (1) | TW302549B (zh) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100470184B1 (ko) * | 1997-12-10 | 2005-07-18 | 주식회사 하이닉스반도체 | 플래쉬메모리소자및그제조방법 |
CN100524633C (zh) * | 1998-01-26 | 2009-08-05 | 索尼株式会社 | 半导体装置的制造方法 |
US5970371A (en) * | 1998-07-06 | 1999-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM |
US5879992A (en) | 1998-07-15 | 1999-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating step poly to improve program speed in split gate flash |
US6011289A (en) * | 1998-09-16 | 2000-01-04 | Advanced Micro Devices, Inc. | Metal oxide stack for flash memory application |
US6756272B1 (en) | 1998-10-01 | 2004-06-29 | Nec Corporation | Method of manufacturing non-volatile semiconductor memory device |
US6340828B1 (en) * | 1998-10-23 | 2002-01-22 | Stmicroelectronics S.R.L. | Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions |
US6133096A (en) * | 1998-12-10 | 2000-10-17 | Su; Hung-Der | Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices |
US6284596B1 (en) | 1998-12-17 | 2001-09-04 | Taiwan Semiconductor Manufacturing Company | Method of forming split-gate flash cell for salicide and self-align contact |
TW407381B (en) * | 1999-03-01 | 2000-10-01 | United Microelectronics Corp | Manufacture of the flash memory cell |
US6358796B1 (en) | 1999-04-15 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation |
US6093608A (en) * | 1999-04-23 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Source side injection programming and tip erasing P-channel split gate flash memory cell |
US6200860B1 (en) | 1999-05-03 | 2001-03-13 | Taiwan Semiconductor Manufacturing Company | Process for preventing the reverse tunneling during programming in split gate flash |
US6355527B1 (en) * | 1999-05-19 | 2002-03-12 | Taiwan Semiconductor Manufacturing Company | Method to increase coupling ratio of source to floating gate in split-gate flash |
US6277686B1 (en) | 1999-07-06 | 2001-08-21 | Taiwan Semiconductor Manufacturing Company | PIP capacitor for split-gate flash process |
KR100298586B1 (ko) * | 1999-07-13 | 2001-11-01 | 윤종용 | 비휘발성 메모리 소자 |
US6242308B1 (en) | 1999-07-16 | 2001-06-05 | Taiwan Semiconductor Manufacturing Company | Method of forming poly tip to improve erasing and programming speed split gate flash |
US6525371B2 (en) * | 1999-09-22 | 2003-02-25 | International Business Machines Corporation | Self-aligned non-volatile random access memory cell and process to make the same |
WO2003088257A1 (en) * | 2002-04-10 | 2003-10-23 | Jeng-Jye Shau | Embedded electrically programmable read only memory devices |
US6204126B1 (en) | 2000-02-18 | 2001-03-20 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a new structure with multi-self-aligned for split-gate flash |
US6245614B1 (en) * | 2000-06-19 | 2001-06-12 | United Microelectronics Corp. | Method of manufacturing a split-gate flash memory cell with polysilicon spacers |
US6620687B2 (en) * | 2001-03-08 | 2003-09-16 | Horng-Huei Tseng | Method of making non-volatile memory with sharp corner |
JP2003168748A (ja) * | 2001-11-30 | 2003-06-13 | Hitachi Ltd | 不揮発性半導体記憶装置およびその製造方法 |
US6541339B1 (en) | 2002-02-21 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Nitride deposition wafer to wafer native oxide uniformity improvement for 0.35 flash erase performance by adding thermal oxide oxidation process |
US6735123B1 (en) * | 2002-06-07 | 2004-05-11 | Advanced Micro Devices, Inc. | High density dual bit flash memory cell with non planar structure |
KR101025921B1 (ko) * | 2003-09-30 | 2011-03-30 | 매그나칩 반도체 유한회사 | 플래시 메모리 셀의 제조 방법 |
KR100546405B1 (ko) * | 2004-03-18 | 2006-01-26 | 삼성전자주식회사 | 스플릿 게이트형 비휘발성 반도체 메모리 소자 및 그제조방법 |
US7199008B2 (en) * | 2004-05-25 | 2007-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Microelectronic device having floating gate protective layer and method of manufacture therefor |
CN101393918B (zh) * | 2007-09-18 | 2011-06-01 | 上海华虹Nec电子有限公司 | 双比特的sonos eeprom存储结构单元及其制备方法 |
CN101419972B (zh) * | 2008-11-13 | 2012-12-12 | 上海宏力半导体制造有限公司 | 高效擦写的分栅闪存 |
CN102610575A (zh) * | 2011-01-21 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | 制作分离栅极式快闪存储器单元的方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2616576B1 (fr) * | 1987-06-12 | 1992-09-18 | Commissariat Energie Atomique | Cellule de memoire eprom et son procede de fabrication |
US4861730A (en) * | 1988-01-25 | 1989-08-29 | Catalyst Semiconductor, Inc. | Process for making a high density split gate nonvolatile memory cell |
US5008212A (en) * | 1988-12-12 | 1991-04-16 | Chen Teh Yi J | Selective asperity definition technique suitable for use in fabricating floating-gate transistor |
JPH081933B2 (ja) * | 1989-12-11 | 1996-01-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US5049515A (en) * | 1990-03-09 | 1991-09-17 | Intel Corporation, Inc. | Method of making a three-dimensional memory cell with integral select transistor |
JP2830447B2 (ja) * | 1990-10-15 | 1998-12-02 | 日本電気株式会社 | 半導体不揮発性記憶装置 |
JP2500871B2 (ja) * | 1991-03-30 | 1996-05-29 | 株式会社東芝 | 半導体不揮発性ram |
US5449941A (en) * | 1991-10-29 | 1995-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
US5477068A (en) * | 1992-03-18 | 1995-12-19 | Rohm Co., Ltd. | Nonvolatile semiconductor memory device |
US5395779A (en) * | 1994-04-08 | 1995-03-07 | United Microelectronics Corporation | Process of manufacture of split gate EPROM device |
US5429969A (en) * | 1994-05-31 | 1995-07-04 | Motorola, Inc. | Process for forming electrically programmable read-only memory cell with a merged select/control gate |
US5427970A (en) * | 1994-07-18 | 1995-06-27 | United Microelectronics Corporation | Method of making flash memory with high coupling ratio |
US5445984A (en) * | 1994-11-28 | 1995-08-29 | United Microelectronics Corporation | Method of making a split gate flash memory cell |
-
1995
- 1995-03-14 KR KR1019950005204A patent/KR0142603B1/ko not_active IP Right Cessation
-
1996
- 1996-03-12 TW TW085102982A patent/TW302549B/zh not_active IP Right Cessation
- 1996-03-13 US US08/614,680 patent/US5652161A/en not_active Expired - Lifetime
- 1996-03-14 CN CN96104337A patent/CN1060590C/zh not_active Expired - Fee Related
-
1997
- 1997-07-16 US US08/895,437 patent/US5859453A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR960036088A (ko) | 1996-10-28 |
KR0142603B1 (ko) | 1998-07-01 |
US5652161A (en) | 1997-07-29 |
CN1138214A (zh) | 1996-12-18 |
CN1060590C (zh) | 2001-01-10 |
US5859453A (en) | 1999-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW302549B (zh) | ||
JP4570240B2 (ja) | 半導体素子及びその製造方法 | |
US6927447B2 (en) | Flash memory devices having a sloped trench isolation structure | |
US6413809B2 (en) | Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench | |
KR100781563B1 (ko) | 비휘발성 메모리 소자 및 그 제조 방법. | |
JP3431367B2 (ja) | 不揮発性半導体記憶装置の製造方法 | |
TW293948B (en) | Flash electrically erasable programmable read only memory cell and process thereof | |
JPH07193121A (ja) | 半導体装置の製造方法 | |
US20070231989A1 (en) | Methods of fabricating nonvolatile memory devices | |
US5336913A (en) | Non-volatile semiconductor memory device and a method for fabricating the same | |
US20020094641A1 (en) | Method for fabricating floating gate | |
US6445029B1 (en) | NVRAM array device with enhanced write and erase | |
US5225361A (en) | Non-volatile semiconductor memory device and a method for fabricating the same | |
JP4553483B2 (ja) | フラッシュメモリ素子の製造方法 | |
JP2003338568A (ja) | フラッシュメモリ素子の製造方法 | |
US6953973B2 (en) | Self-aligned trench isolation method and semiconductor device fabricated using the same | |
US20040157434A1 (en) | Method of manufacturing SONOS flash memory device | |
JPH08181231A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JPH0878542A (ja) | 不揮発性半導体装置 | |
JPH0640586B2 (ja) | 不揮発性半導体記憶装置の製造方法 | |
JPH1117034A (ja) | 半導体記憶装置およびその製造方法 | |
JP3097607B2 (ja) | スプリットゲート型フラッシュメモリセルおよびその製造方法 | |
JPH0223672A (ja) | 半導体記憶装置 | |
JP3028412B2 (ja) | フラッシュメモリセル製造方法 | |
JP3664884B2 (ja) | 半導体記憶装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |