TW302549B - - Google Patents

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TW302549B
TW302549B TW085102982A TW85102982A TW302549B TW 302549 B TW302549 B TW 302549B TW 085102982 A TW085102982 A TW 085102982A TW 85102982 A TW85102982 A TW 85102982A TW 302549 B TW302549 B TW 302549B
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oxide film
film
patent application
flash eeprom
item
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Hyundai Electronics Ind
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Description

302549 經濟部中央標準局員工消费合作社印製 B7 五、發明説明(/ ) 發明領域: 本發明係_於一種快閃EEPROM細胞元及其製法,尤指一種分 離閘極型的快閃EEPROM細胞元及其製法,可以隔開隧道區和通 道,以改善元件的可靠性。 發明背景: 一般來說,在製造半導体元件的製程中,同時具有電子程式化 和拭除功能的快閃EEPROM (電子拭除式可程式唯讀記憶体)細胞 元可以分爲二種結構:堆叠閘極結構和分離閘極結構。 如圖1A,傳統堆叠閘極型快閃EEPROM細胞元的結構中,隧 道氧化膜5、浮動閘極6、複晶矽之間的氧化膜11和控制閘極12連 續堆叠在汲極區7和源極區8之間的矽基板1上。 如圖1B,傳統分離閘極型快閃EEPROM細胞元的結構中,隊 道氧化膜5、浮動閘極6、複晶矽之間的氧化膜11和控制閘極12連 緬形成在汲極區7和源極區8之間的矽基板1上,而且在此結構 中,控制閘極12堆叠結構中的上層並向源極區8延展。此延展的控 制閘極12下方的矽基板1則爲選擇閘極通道區9。 雖然堆叠閘極結構與分離閘極結構相較之下*可以縮小毎細胞 元的面積,具有提高元件密度的優點,在拭除時卻容易過度拭除。 但即使分離閘極結構可以克服堆疊閘楹結構的缺點,因爲它毎細胞 元的面積仍大於堆叠閘極型的結構,就無法提高元件的密度。 而且,無論是堆叠閘極型或分離閘楹型的快閃EEPROM細胞 元,進行程式化和拭除的功能時都必須對細胞元施以高壓。當使用 高壓進行程式化和拭除功能時,接面區和閘楹之間的重叠區域會形 成強烈的電場,引發出頻帶對頻帶的穿隧效應和次級熱電子。但因 睡道氧化膜通常厚度約100埃,頻帶對頻帶的穿隧效應和次級熱載 J--·-----ί I裝------訂-----線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS > Α4規格(210X297公釐) 經濟部中央樣準局員工消費合作社印裝 A7 __B7_
五、發明説明(二J 子會破壞這眉隨道氧化膜,而降低了元件的可靠性。 發明的籣要說明: 本發明的目的是要提出一種快閃EEPROM細胞元及其製法,可 以降低高壓對隧道氧化膜的破壞,同時解決細胞元拭除時過度拭除 的問題。 爲了達成以上的目的,本發明快閃EEPROM細胞元的方法,其 步驟係包含: 連續沈積第一氧化膜和氮化膜,然後以光阻圖案作爲蝕刻光 罩,透過触刻製程去除部份的第一氧化膜和氮化膜,並露出部份的 矽基板。 去除光阻圔案,然後氧化露出表面部份的矽基板,形成第二氧 化膜; 以去除部份後的氮化膜作爲蝕刻光罩,去除底下露出的第二氧 化膜,在所去除第二氧化膜之處的矽基板表面形成一凹陷部份,同 時由去除部份後留下的氮化膜所覆蓋的第二氧化膜則保留下來; 在矽基板的凹陷部份形成汲極區; 在矽基板的凹陷部份形成隨道氧化膜,然後在整個結構上形成 第一複晶矽雇; 以浮動閘棰的光罩,利用蝕刻製程連纜去除第一複晶砂層、已 除去部份留下的氣化膜、睡道氧化膜和已除去部份留下的第一氧化 膜,形成第一複晶砂製成的浮動閘棰; 植入控制臨界電壓的雜質,在浮動閘極一側的矽基板上形成選 擇閘楹通道區; 形成選擇閘極氧化膜和複晶矽之間的氧化膜,然後在整個結構 上形成第二複晶败雇;以及 本紙張尺度適用中國國家標準(CNS ) A4規格(210X.297公釐) ~ [--k-----( ·裝------訂------ {請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣隼局員工消費合作社印製 302549 五、發明説明(彡) 以控制閘極的光罩,利用蝕刻製程制定第二複晶矽層的圖案, 形成分離形的控制閘極結構,然後在控制閘極一邊露出的矽基板上 形成源極。 本發明之快閃EEPROM細胞元係包含: 一面矽基板,上有凹陷部份; 汲極區,位在矽基板的凹陷部份; 源極區,位在遠離汲極區的矽基板上; 浮動閘極,覆叠在汲極與源極區之間的部份破基板上,並覆叠 在部份的汲極區上,以一薄絕緣膜與汲極區電性隔離,而以一厚絕 緣膜與矽基板隔開;以及 控制閘極,延展至源極的邊緣部份,以氧化膜分別與浮動閘極 和砂基板隔開。 附圖的簡要說明: 爲了能夠更完全地瞭解本發明的內容和目的,底下將參照附圖 詳加說明,所附附圖分別爲: 圖1A是傳統堆疊閘極型快閃EEPROM細胞元的橫剖面圖。 圖1B是傳統分離閘極型快閃EEPROM細胞元的橫剖面圖。 圖2A至2H的元件橫剖面圓說明依據本發明製造快閃EEPROM 細胞元的方法。 圖3A和3B的狀態圈說明本發明之快閃EEPROM細胞元的操作 方式。 各附圖中相同的編號均代表相同的組件。 發明的詳細說明: 底下將參照附圖,詳細說明本發明。
圖2A至2H的元件橫剖面圖說明依據本發明製造快閃EEPROM 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) I---------f ·裝------訂------ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標率局員工消费合作社印装 五、發明説明(卜) 細胞元的方法。 圖2A中,先在矽基板1上連續形成第一氧化膜2和氮化膜 3,然後利用光阻圖案10作爲蝕刻光罩,透過蝕刻製程去除部份的 第一氧化膜2和氮化膜3,露出部份的矽基板1。第一氧化膜2在 矽基板1上的厚度約爲150至250埃,而氣化膜3在第一氧化膜2上 的厚度約爲400至600埃。 圖2B中,去除光阻圈案10後,氧化露出表面部份的矽基板1, 形成厚度約1500至2500埃的第二氧化膜4。 圈2C中,以去除部份後留下的泡化膜3作爲蝕刻光罩,利用乾 蝕刻製程去除第二氧化膜4露出的部份。當去除第二氧化膜4露出 的部份之後,會在矽基板〗的表面上留下一個凹陷部份,但氮化膜 3所覆蓋住的第二氧化膜4則被保留下來。 圖2D中,在矽基板1的凹陷部份植入高濃度的N型雜質離 子,並且進行回火,形成汲極區8A。 圖2E中,先在矽基板1露出的部份上形成厚度約80至120埃的 隆道氧化膜5A,然後在整個結構上形成第一複晶矽層16。 圖2F中,用浮動閘極的光罩,轔由乾蝕刻製程連鑕制定各眉的 圖案,包括第一複晶矽16、氮化膜3、隧道氧化膜5A和第一氧化 膜2。第一複晶矽16制定圖案後就成了浮動閘極16A。由圈2F還可 看到,以汲極區8A中心部份爲主的兩側各有一個浮動閘極16A。 圖2G中,在浮動閘極16A外側露出的矽基板1上植入控制臨界 電壓雜質離子,而形成選擇閘極通道9A。 圖2H的元件横剖面圖中,接著在形成選擇閘楹通道9A之後, 在整個結構上同時成長選擇閘楹氧化膜13和複晶矽之間的氧化膜 11A。然後形成第二複晶砂層,並用乾蝕刻製程以控制閘棰的光罩 (請先閱讀背面之注意事項再填寫本頁) •裝. ,ιτ 本紙張又度適用中國國家榡準(CNS ) Α4规格(210X297公釐) A7 B7 五、發明説明(y) 制定第二複晶矽眉的圖案,在兩個浮動閘極16A上各形成一個控制 閙極12。然後植入高濃度的N型雜質離子,在兩個控制閘極,12之外 的矽基板1上各形成一個源極區7A。 經由上述的製程步驟,即完成兩個共有汲極區8A的快閃 EEPROM細胞元。 根據本發明製造的快閃EEPROM細胞元,其結構包含:一面矽 基板1,上有凹陷部份;汲極區8A,位在矽基板1的凹陷部份; 源極區7A,位在遠離汲極區8A的矽基板1上;浮動閘極16A,覆 疊在汲極區8A和源極區7A之間的部份矽基板1上,並覆疊在部份 的汲極區8A上,同時以一薄絕緣膜與汲極區8A隔開,而以一厚絕 緣膜與矽基板1隔開;控制閘極12,覆蓋住浮動閘極16A,並延展 至源極7A和邊緣部份,以氧化膜分別與浮動閘極16A和矽基板1隔 開° 以上所述薄絕緣膜是隧道氧化膜,厚度約80至120埃,而厚絕 緣膜係由沈積厚度約150至1000埃的絕緣材料所形成。 現在將參照附圖3A和3B,說明本發明之快閃EEPROM細胞元 的操作原理。 圖3A和3B的狀態圖說明本發明之快閃EEPROM細胞元的操作 方式。 圖3A是快閃EEPROM細胞元進行程式化時的狀態圖。 若對矽基板1上的控制閘極12施加約12V的高壓,而使源極區 7A和汲極區8A接地,在汲極區8A和浮動閘極16A之間的隧道氧化 膜5A會因高電場而引發福勒一諾罕(fowler-nordheim)穿隧效應,致 使電子在浮動閘極16A充電,而完成了程式化的動作。 圖3B是快閃EEPROM細胞元拭除操作時的狀態圖。 (請先閲讀背面之注意事項再填寫本頁) : 、? 經濟部中央揉準局員工消费合作社印製 本紙張尺度遑用中國國家橾準(CNS ) A4规格(210X297公釐) A7 B7 五、發明説明(L) 若對矽基板1上的汲極區8A施加約12V的高壓,而使源極區7A 和控制閘極12接地,原先因汲極區8A和浮動閘極16A之間的高電場 引發福一諾罕穿隧效應而在浮動閘極16A充電的電子又會在隧道氧 化膜5A放電,而完成了拭除的動作。 正如以上說明,本發明之分離閘極型快閃EEPROM細胞元中, 隧道區由一厚絕緣膜與通道區隔開,當對結構施加高壓進行程式化 和拭除等操作時,接面區與閘極的重叠區域的高電場所引發的頻帶 對頻帶穿隧效應和次級熱載子,就不致破壞細胞元的隧道氧化膜, 也能避免驅動細胞元時的過度拭除。 以上雖然透過較佳實施例詳加說明,但僅爲了說明本發明的原 則與精神,不應視爲本發明只限於所揭露和說明的較佳實施例。因 此,所有在本發明範圍和精神之內所作細節上的修改都應視爲本發 明進一步的實施例。 1^1 ^^1 —I— n-i ^^1 ^ - (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央橾準局員工消费合作社印製 本紙浪尺度適用中國困家梂準(CNS ) A4规格(210 X 2的公釐)

Claims (1)

  1. A8 B8 C8 D8 六、申請專利範圍 — 1. 一種製造快閃電子拭除式可程式唯讀記憶体(EEPROM)的方法, 其步驟係包含: 在一面砂基板上連緬沈積第一氧化膜和氮化膜,然後以光阻 圖案作爲光罩,透過蝕刻製程去除部份的第一氧化膜和氮化膜, 並露出該矽基板的一部份; 去除該光阻圈案後,氧化該露出的矽基板部份,形成第二氧 化膜; 以該已部份去除所留下的氮化膜作爲蝕刻光罩,去除該第二 氧化膜露出的部份,在去除該第二氧化膜之處的矽基板表面上形 成一凹陷部份,而由該已部份去除所留下的箱化膜所覆蓋的第二 氧化膜則保留下來; 在該砂基板的凹陷部份形成汲極區; 在該矽基板的凹陷部份形成隧道氧化膜,然後在整個結構上 形成第一複晶矽層; 以浮動閘極的光罩,利用蝕刻製程連績去除該第一複晶砂 雇、該已部份去除所留下的氮化膜、該睡道氧化膜和該已部份去 除所留下的第一氧化膜,形成由該第一複晶败製成的浮動閘極; 經濟部中央揉芈局貝工消費合作社印装 (請先閲讀背面之注意事項再填寫本頁) 植入控制臨界電壓的雜質,在該浮動閘極一側的矽基板上形 成選擇閘極通道區; 形成選擇閘楹氧化膜的複晶矽之間的氧化膜,然後在整個結 構上形成第二複晶矽雇;以及 以控制閘極的光罩,利用蝕刻製程制定該第二複晶矽眉的圈 案,形成分離型的控制閘楹結構,然後在該控制閘極一側露出的 矽基板上形成源極〇 2. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 本紙張尺度逋用中國國家橾準(CNS ) A4规格(210X297公釐) 302549 cs ___ D8 六、申請專利範圍 法,其中該第一氧化膜厚度約150至250埃。 3. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 法,其中該第二氧化膜厚度約1500至2500埃。 4. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞元的方 法,其中該親化膜厚度約400至600埃。 5. 根據申請專利範圍第1項所述之製造快閃EEPROM細胞的方法, 其中該隊道氧化膜厚度約80至120埃。 6. _種快閃EEPROM細胞元,係包含: 一面砂基板,上有凹陷部份; 汲極區,位在該砂基板的凹陷部份; 源極區,位在遠離該汲極區的矽基板上; 浮動閘極,覆叠在該汲極與源極區之間的部份砂基板上,並覆叠 在該汲極區的一部份,該浮動閘極以一薄絕緣膜與該汲極區電性 隔離,而以一厚絕緣膜與該矽基板隔開;以及 控制閘極,覆蓋住該浮動閘極,並延屬至該源極的邊緣部份,並 以一氧化膜分別與該浮動閘極和矽基板隔開。 7. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其中 該薄絕緣膜係一隧道氧化膜。 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 8. 根據申請專利範園第7項所述之製造快閃EEPROM細胞元,其中 該隧道氧化膜厚度約80至120埃。 9. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其中 該厚絕緣膜係由沈積厚度約150至1000埃之絕緣材料所形成。 10. 根據申請專利範圍第6項所述之製造快閃EEPROM細胞元,其 中該厚絕緣膜是由氧化膜和氮化膜形成的褸合結構。 11. 根據申請專利範圍第10項所述之製造快閃EEPROM細胞元,其 本紙張尺度逋用中國团家標準(CNS > A4规格(210X297公釐〉 A8 B8 C8 D8 ττ、申請專利範圍 中該氧化膜厚度約150至250埃。 12.根據申請專利範圍第10項所述之製造快閃EEPROM細胞元,其 中該氮化膜厚度約400至600埃。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局負工消費合作社印製 本紙張尺度逋用中國國家橾準(CNS > Α4规格(210X297公釐)
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