TW300324B - - Google Patents

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TW300324B
TW300324B TW085102017A TW85102017A TW300324B TW 300324 B TW300324 B TW 300324B TW 085102017 A TW085102017 A TW 085102017A TW 85102017 A TW85102017 A TW 85102017A TW 300324 B TW300324 B TW 300324B
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dielectric material
organic dielectric
layer
material layer
item
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TW085102017A
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Hughes Aircraft Co
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0195Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0571Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0597Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/064Photoresists
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

A7 B7 五、發明説明(1) 本發明背景 本發明大體有關各種積體電路處理方法,尤其有關藉 形成一蝕刻阻斷層製作金屬化基質之方法Ο 習用蝕刻阻斷層材料舉例言之如光阻蝕刻材料典型上 係在飽刻後予以移除0本發明受讓人前曾開發一種使用蝕 刻阻斷有機層及將蝕刻狙斷層遺留於定位之後縝濕蝕刻步 騍之方法0此項本發明揭示於1993年九月10日提出之名稱 爲〜電子互連結構之相位光罩雷射製法"之美國專利申請 案第08/119,925號中〇 此一專利申請案中揭示之發明使用相位光罩雷射機製 (切削)法以製作一高密度精細圖案徵貌電互連結構,譬 如半導體晶圓、多晶片模組、及微電機元件〇相位光罩雷 射機製程序勾勒金屬導體圖案〇導體圖案係用一相位光罩 雷射製圖案之介電層作爲導體濕蝕刻遮罩層,或使用全像 相位光罩雷射微機製法減除金屬予以製作〇 經濟部中央標準局貝工消費合作社印製 使用本發明,有一第一介電材料層形成於基質上,一 金屬層形成於該第一介電材料層上,而且一第二介電材料 層形成於該金屬層上〇 —相位光罩置放於該第二介電材料 層面上,其內具有一預定相位圖案定義一與一互連結構對 應之金屬導體圖案〇然後用該相位光罩處理該第二介電材 料層以形成該互連結構0該第二介電材料層所形成之蝕刻 光罩無需在蝕刻金屬之後予以移除,而予製成足夠薄至不, 擾亂中間層介電層(一額外置放之介電層)之總厚度關係 ,從而將該中間介電層之電容保持於其所希冀之値上0 本紙張尺度適用中國國家標準(CNS ) A4規格( 210X297公釐) 經濟部中央標準局員工消費合作社印製 ^_;__ 五、發明説明(2) 然而,一懸垂突棚形成於該金屬層之上方,而此有可 能在置放中間層介電層時導致空$包陷且形成潛在破壞之 氣泡〇因此,本發明之一目的爲提供一種形成消除此等潛 在問題之供用於製作金屬化積體電路基質一類之蝕刻阻斷 層之改良方法0 本發明捺述 爲符合以上及其他目的,依據本發明之各項原理,在 一基質上沉積一金屬層,並在該金屬層面上沉積一較薄之 有機介電材料層0該有機介電材料薄層之沉積厚度爲夠薄 至當用作蝕刻阻斷層供底下之金屬層嗣後蝕刻圖案化時具 有蝕刻阻力,但夠厚至不具有針孔瑕疵〇該有機介電材料 薄層之沉積厚度典型爲例如一微米之譜〇然後使所沉積之 有機介電材料薄層乾燥或部份固化。固化之量視圖案蝕刻 環境及化學而定〇然後以該薄有機介電材料用作阻斷層而 用濕或乾反應離子蝕刻程序蝕刻底下之金餳層0由於該有 機介電材料薄層爲乾燥或僅部份固化,故其在後練以一額 外之較厚有機介電材料層被覆並兼將二層完全固化時依順 於已蝕刻之底下金屬層〇 更明確言之,在蝕刻底下之金屬層後留下極薄之乾燥 或部份固化有機介電層,並形成一懸垂之突棚。該懸垂之 突棚有可能在後續被覆以額外之有機介電材料時包住空氣 ,除非其變形而變成依順於已蝕刻金屬層之緣上〇藉由沉, 稹該有機材料薄層至一極小之厚度(約一微米)並故意不 將其完全固化,該有機介電材料薄層變成更具塑性故而變 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項寫本頁) -裝- 訂 泉 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明(3) 形俾於完全固化時依順於底下已蝕刻金屬層之緣〇此在將 厚層之有機介電材料沉稹於蝕刻阻斷層面上並兼使二層完 全固化時,防止形成空氣包陷及氣泡。 本發明可用於製作沉積型多晶片模組(MCM-D)大面板 高密度多層互連(HDMI)基質之類。 簡要圖說 本發明各種特色與優點可參考以下詳述連同附圖而更 迅即了解,其中相同之參考數字指示相同之構造元件,圖 中: 圖1 一 4例示依據本發明各項原理形成蝕刻阻斷層之 方法之各處理步驟;而 圖5爲詳述本發明處理流程之流程圖。 本發明詳述 請參考各圖式;圖1至4顯示依據本發明各項原理使 用一有機介電蝕刻阻斷層23製作金屬化基質21之方法10之 各處理步驟。亦請參考圖5,其乃一詳述本方法10之處理 流程之流程圖〇 請參考圖1;提供一基質21 (步驟11),並在基質21 上沉積一金屬層22 (步驟12) 〇基質21典型上包含一底層 ,可由金屬製成而在其上置放一介電層例如矽、聚亞醯胺 ,或撓性基質材料〇底下之金藺層22典型上包含例如鋁。 —較薄之有機介電材料層23沉積(步驟13)於先前沉積之 底下金藺層2 2之面上〇該較薄之有機介電材料層2 3係沉積‘ 成例如一微米左右之厚度。將該較薄有機介電材料層23乾 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -6- (請先閱讀背面之注意事項各¥'寫本頁) .裝· 訂 泉 經濟部中央梂準局員工消費合作社印製 A7 B7 五、發明説明(4 ) 燥(步驟14),但不予完全固化。固化之量視所採用之圖 案蝕刻環境及化學而定〇舉例言之,該有機介電材料薄層 2 3係固化至不溶於所用濕蝕刻流體內之點。此例如可能爲 以250 之溫度加熱該構造達小時之譜。 請參考圖2 ;該較薄之有機介電材料層23係以習用方 式圖案化(步驟15),譬如使用準分子雷射直接切除程序 或例如光石印程序〇圖案化步驟15將部份之較薄有機介電 材料層2 3去除,而將有機介電材料2 3留在需要金屬之處〇 然後通過已圖案化之有機介電材料薄層23蝕刻底下之金屬 層22 (步驟16),典型上係使用濕蝕刻程序或乾反應離子 蝕刻程序〇 請參考圖3 ;蝕刻步驟16將較薄之有機介電材料層23 固定遺留於底下金屬層22上〇該有機介電材料薄層23因蝕 刻步驟16而被下切。 請參考圖4 ;已蝕刻之薄層有機介電材料23及底下之 金屬層22於是被覆以一所需厚度之較厚有機介電材料層24 (步驟17) 〇該較厚有機介電材料層24之厚度典型爲例如 9-10微米之譜。然後使已蝕刻之有機介電材料薄層23及該 較厚之有機介電材料層24同時完全固化(步驟18),以使 該有機介電材料薄層23依順於底下之已圖案化金屬層22 〇 此固化步驟1 8消除空氣泡沬或氣泡之形成。 迄此,業已說明一新穎且改良之使用有機介電蝕刻阻 斷層將金賜化基質圖案化之方法〇應了解,所述具體形式 僅例示代表本發明各項原理應用之許多特定具體形式中之 ^紙張尺度適用中國國家標準(〇呢)人4規格(210’犬297公釐) ~ -7- ---------„---裝------訂.---^----(泉 (請先閱讀背面之注意事項4填寫本頁) A7 B7 五、發明説明(5 ) 一些〇顯然,有許多及其他之配置可迅即由業界技術熟練 人員設計出而不背離本發明之範疇〇 ---------„---裝-------訂----^----(泉 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐)

Claims (1)

  1. 經濟部中央橾準局属工消費合作社印装 A8 B8 C8 D8 六、申請專利範圍 1 .一種製作金溷化基質(21)之方法(1〇),係以下列各 步驟爲其特徵: 提供(11) 一基質(21); 沉稹(12) —金屬層(22)於該基質U1)上; 沉積(12)—較薄之有機介電材料層(23)於該金藺層 (22)上; 將該較薄之有機介電材料層(23)部份固化(14); 將該部份經固化之較薄有機介電材料層(23)圖案化 (15); 通過已圖案化之有機介電材料層(23)蝕刻(16)底下 之金屬層(22)以留下位於底下已圖案化金屬層(22)上方之 較薄有機介電材料層(23); 以一較厚之有機介電材料層(24)將已蝕刻之有機介 電材料層(23)及底下之金觴層(22)被覆至所需之厚度;以 及 使已蝕刻之有機介電材料層(23)及該較厚之有機介 電材料層(24)同時完全固化(18),以使該有機介電材料薄 層(23)依順於底下之已圖案化金屬層(22 )〇 2. 如申請專利範圍第1項之方法(10),其中將一金屬 層(22)沉積於基質(21)上之步驟之特徵爲於基質(21)上沉 積一鋁層〇 3. 如申請專利範圍第1項之方法(10),其中沉積一較 薄之有機介電材料層(23)之步驟之特徵爲將該有機介電材 料層(23)沉積成約一微米之厚度〇 本紙張尺度逋用中國國家標準(CNS > Μ規格.(210X297公在) ~ ' -----IΚ---裝------訂丨丨-----^ (請先閲讀背面之注意事項再填寫本頁) ABCD 經濟部中央梂準局貞工消费合作社印裝 々、申請專利範圍 4. 如申請專利範圍第1項之方法(10),其中將部份固 化之較薄有機介電材料層(23)圖案化之步驟係以使用光石 印程序將層(23)圖案化之步驟爲其特徵〇 5. 如申請專利範圍第1項之方法(10),其中將部份固 化之較薄有機介電材料層(23)圖案化之步驟係以使用準分 子雷射直接切除程序將層(23)圖案化之步驟爲其特徵〇 6. 如申請專利範圍第1項之方法(10),其中通過已圖 案化之有機介電材料層(23)蝕刻底下之金屬層(22)之步驟 係以使用濕蝕刻程序爲其特徵〇. 7. 如申請專利範圍第6項之方法(10),其中通過已圖 案化之有機介電材料層(23)蝕刻底下之金屬層(22)之步驟 將該有機介電材料薄層(23)下切。 8 .如申請專利範圍第1項之方法(1 0 ),其中通過已圖 案化之有機介電材料層(23)蝕刻底下之金屬層(22)之步驟 係以使用反應離子蝕刻程序爲其特徵。 9.如申請專利範圍第1項之方法(10),其中該較厚有 機介電材料層(24)之所需厚度約爲9-10微米。 10.如申請專利範圍第6項之方法(10),其中將該較薄 之有機介電材料層(23)部份固化之步驟(14)係以約250 *C 之溫度加熱該材料(23)約達0.5小時爲其特徵〇 本紙張尺度逋用中國國象標準(CNS ) A4規格(210X291 兮 — I I 裝 n 訂 -1 (請先閲讀背面之注意事項再填寫本頁)
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