TW499750B - Substrate strip and its manufacturing method - Google Patents

Substrate strip and its manufacturing method Download PDF

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Publication number
TW499750B
TW499750B TW90123850A TW90123850A TW499750B TW 499750 B TW499750 B TW 499750B TW 90123850 A TW90123850 A TW 90123850A TW 90123850 A TW90123850 A TW 90123850A TW 499750 B TW499750 B TW 499750B
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TW
Taiwan
Prior art keywords
substrate
strip
unit
frame
substrate strip
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TW90123850A
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Chinese (zh)
Inventor
Yi-Chuan Ding
Kun-Ching Chen
Yung-I Yeh
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A kind of substrate strip is provided with plural substrate units, and each substrate unit is capable of being used to package excellent semiconductor substrates. The substrate strip contains the followings: a frame, which is provided with at least one opening; at least one of the first substrate units, which is formed by integral molding with the frame; and at least one of the second substrate units arranged inside the opening, in which the second substrate unit is fixed and connected to the frame by using a glue adhesive. Additionally, the present invention provides a kind of method for manufacturing the substrate strip, in which bad substrate unit is taken away from a substrate strip and is replaced by the excellent substrate unit to fill up and be fixed to the substrate strip.

Description

499750 五、發明說明（1) 【發明領域】 本發明係有關於一種用於封裝半導體之基板條，尤其關 於一基板條具有複數個基板單位，且每一基板單位皆為良 好之基板單位。 【先前技術】 隨著在固定大小的半導體晶片（Chip)上製造大量電晶體 之能力增加，該晶片上的電路變得更複雜且需要大量的電 性外接點（external electrical connections)。為了達 成所需外接點的數目，半導體封裝構造從以導線架為基礎 (lead frame based)的封裝構造，如雙列直插式封裝構造 (dua卜in-line package，簡稱DIPs)或四方平坦封裝構造499750 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a substrate strip for packaging semiconductors, and particularly relates to a substrate strip having a plurality of substrate units, and each substrate unit is a good substrate unit. [Previous Technology] As the ability to manufacture a large number of transistors on a fixed-size semiconductor chip (chip) has increased, the circuits on the chip have become more complicated and require a large number of external electrical connections. In order to achieve the required number of external points, the semiconductor package structure is from a lead frame based package structure, such as a dual-in-line package (DIPs) or a square flat package. structure

Uuad-flat-pack，簡稱QFP)，發展至以層壓基板為基礎 (laminated substrate based)的封裝構造，如球格陣列 (ball grid arrays，簡稱BGA)封裝構造。 第1圖係一傳統BGA封裝構造之剖視圖。如圖所示，該封 裝構造包含一個由陶瓷或塑膠材質如環氧樹脂—玻璃 te^^y_glass)製造的層壓基板106。導電線路（未示於圖 & t i作該基板106的導電層。在該領域中製造導電線路 的方法係為已知。例如，微影技術（ph〇t〇_Hth〇graphic 二 個想要的圖形之影像形成在-個被塗佈 於该基板106導電層上的光阻材料中。該光阻 ，二i員影」，即是將不屬於該影像的光阻材料去除，因 ί =除光阻材料下，該基板上的導電層便暴露出來。暴 露出來的導電材料在鞋刻u二出來暴 Τ饭舌除。最後去除殘留下 麵 :\P01-115.ptc 第4頁 499750Uuad-flat-pack (referred to as QFP) has developed to a laminated substrate based package structure, such as a ball grid arrays (BGA) package structure. Figure 1 is a cross-sectional view of a conventional BGA package structure. As shown, the package structure includes a laminated substrate 106 made of a ceramic or plastic material such as epoxy-glass (te ^^ y_glass). Conductive circuits (not shown) are used as the conductive layer of the substrate 106. Methods of making conductive circuits in this field are known. For example, lithography technology (ph〇t〇_Hth〇graphic two The image of the pattern is formed in a photoresist material that is coated on the conductive layer of the substrate 106. The photoresist, the second member shadow, is to remove the photoresist material that does not belong to the image. Under the removal of photoresist material, the conductive layer on the substrate is exposed. The exposed conductive material is removed in the shoe engraving. Finally, the residue is removed: \ P01-115.ptc Page 4 499750

來的光阻材料’將具有所想要圖案的導電層留在該基板 曾層’、層之間的電性連接（electrical connections)由 ^電通孔（00]1(111(：1：^6¥45)形成，如通孔114。該基板中 之通孔係由已知技術製造，例如，機械或雷射式鑽孔。在該 通孔製作完成後，鍍上一導電材料以提供所欲之電性接 觸在該封裝基板的下表面（i〇wer surface)形成複數 個到該封裝構造之導電線路的接觸點。 以上為製作基板的基本過程。之後，一半導體晶片1〇2 藉適當晶片黏接材料（Chip attach material)110， 如環氧樹脂，接於該封裝基板1〇6之上表面（upper surface)。該晶片1〇2上之銲墊（bond pads)與該基板上之 $電線路之間的電性連接以接線（b〇nd wires)1〇4提供。 當然，除了如圖所示的接線外，在這個領域中也有數種不 同已熟知的方法提供從該晶片到該封裝構造之電性連接， 如線接法（wire bonding)或覆晶（fup —chip)技術。 最後，多個銲球108被黏接在各個接觸點上以允許該半 導體封裝構造與外部電子元件，如印刷線板（printed wire boards),連接。銲球108傳統上以及典型地以一種 錯-錫合金構成並以熟知的方法如回銲（re_f 1〇w soldering)黏接於該接觸點。當然，其它的傳統電性連接 物，如傳導針（conductive pins)，可替代該銲球1〇8黏接 於該基板106下表面之接觸點。 所有半導體封裝構造不只必須提供多個電性連接於晶片 上之銲墊與該封裝構造外在接觸點間，也必須提供該晶片The coming photoresistive material 'leaves the conductive layer with the desired pattern on the substrate layer', and the electrical connections between the layers are defined by ^ 电 通 孔 (00) 1 (111 (: 1: ^ 6 ¥ 45), such as through-hole 114. The through-holes in the substrate are made by known techniques, such as mechanical or laser drilling. After the through-holes are fabricated, a conductive material is plated to provide the desired The electrical contact forms a plurality of contact points to the conductive structure of the package structure on the lower surface of the package substrate. The above is the basic process of making a substrate. After that, a semiconductor wafer 102 borrows an appropriate wafer. A chip attach material 110, such as epoxy resin, is connected to the upper surface of the package substrate 106. The bond pads on the chip 102 and the $ 100 on the substrate The electrical connection between the electrical lines is provided by bond wires 104. Of course, in addition to the wiring shown in the figure, there are several different well-known methods in this field to provide from the chip to the Electrical connection of the package structure, such as wire bonding or Fup-chip technology. Finally, a plurality of solder balls 108 are adhered to various contact points to allow the semiconductor package structure to be connected to external electronic components such as printed wire boards. The solder ball 108 traditional It is typically made of a wrong-tin alloy and is adhered to the contact point by well-known methods such as re_f 10w soldering. Of course, other traditional electrical connectors such as conductive pins It can replace the contact points where the solder balls 108 are adhered to the lower surface of the substrate 106. All semiconductor package structures must not only provide multiple electrical pads electrically connected to the chip and the external contact points of the package structure, but also Must provide the chip

499750 曰 修正 案號 90123850 —~—------- - 五、發明說明（3) 保護以防止使用時的損傷。為了保覆該晶片102 11 ^ 1 f ^ ^ covering) „ t 板上。—般而t，該封裝構造上的鑄模製造 的包，體112係由一封膠製程製造而成。 、表绝 目前，為了同時裝配多個封裝構造，單獨基 條方式提#，該基板條包含多個基板單位，該多 =^ 程ί會被分離或單叫匕。該基板條之形式可在整個 封裝製程中使產率增加到最大，且相一 + 處操作的封裝製程，使用該基板條之；減：：； 域材料處理之耗費。 飞乜了減少其它區 ，用基板條形式之基板的難題之—， 供其上百分之百為良好基板單元之基板條m 裝廠商不至因此生產出不良之單元。 :使付封 =則會因生產出的不良單位導致其某 Γ因此基板條中若具有-個數目以 上，不良基板早π，連同該基板條上全部其 疋都必須被廠商淘汰。因此需要一個： 所生產的每-個良好基板單位都被充分利用：=;^商 之百為良好基板單元之基板條以提古 並k供百刀 低封裝廠商的成本。 h封裝製程的產率，降 【發明概要】 本發明之主要目的在於提供一種基 百為良好之基板單元，_此提古4 ”，其/、有百分之 裝的成本。 肖此“封裝製程的產率，降低封 m K:\POM15.ptc 麵 第6頁 499750 修正 案號 90123850 五、發明說明（4) 為達上述以及其他目的’本發明提供一種基板條，苴 徵在於包含複數個基板單元與一框架一體成型盆中該框架 具有至少一開口，以及至少一基板單元置於該開口 ^以二 膠黏劑固接於該框架。該基板條所具有之所有基板單元皆 為良好之基板條可使用於半導體封裝上，不會因不良之^ 板單元而製造出不良之封裝後半導體，以提高封裝製程之 產能。 、 本發明另提供製造該基板條之方法。首先，提供一基板 條其具有複數個基板單元與一框架一體成型，且該複&個 基，單元包含至少一不良基板單元。接著，將該不良之基 板單元自該基板條取下，因而於該框架上留下至少一開 口。之後，將一良好之基板單元置於該框架上之開口中。 最後以一膠黏劑將該開口中之良好基板單元固接於該框架 中。其中該良好基板單元係由淘汰之其他基板條取下，根 據此方法可使淘汰基板條上之良好基板單位獲得利用，而 節省基板製造廠商之支出。 本發明之上述和其它特徵、目的，從下文與圖示關聯的 詳細說明中將能更容易瞭解·· 【發明說明】 第2圖為根據本發明一較佳實施例基板條2〇 〇之上視圖。 基板條200包含兩個第一基板單元2〇2與一框架2〇4—體成 型，該基板條200上另有兩個開口2〇5。兩個第二基板單元 203各置於該開口 205中以一膠黏劑212固接於該框架204 上。該基板條2 0 〇較佳具有複數個去鑄洗道區2丨〇，自該框499750 Amendment No. 90123850 — ~ —--------5. Description of the invention (3) Protection to prevent damage during use. In order to cover the chip 102 11 ^ 1 f ^ ^ covering) „t plate. — In general, the package 112 made of a mold on the package structure is manufactured by a glue process. In order to assemble multiple package structures at the same time, a single base strip method is provided. The substrate strip contains multiple substrate units, and the multiple strips will be separated or called daggers. The form of the substrate strip can be used in the entire packaging process. Use the substrate strip to increase the yield to the maximum, and use the substrate strip in the packaging process; minus ::; the cost of domain material processing. Fei has reduced the problem of reducing substrates in the form of substrate strips in other areas— For the substrate strips that are 100% of the good substrate units, the packaging manufacturer will not produce defective units.: Make sub-packaging = will cause one of them because of the defective unit produced, so if there is a number in the substrate strip Above, the bad substrates must be eliminated by the manufacturer, as well as all the substrates on the substrate strip. Therefore, one: Every good substrate unit produced is fully utilized: =; ^ 100 of the good substrate units are good substrate units. Substrate strip The cost of the package is reduced by using Tigu and k. H packaging process yield is reduced. [Summary of the invention] The main purpose of the present invention is to provide a substrate unit with a good base. This Tigu 4 ", which /, There is a cost of installation. Xiao this "The yield of the packaging process, reduce the sealing m K: \ POM15.ptc surface, page 6 499750 Amendment No. 90123850 V. Description of the invention (4) In order to achieve the above and other objectives, the present invention provides a substrate strip, The frame includes a plurality of substrate units and a frame integrally formed in a pot. The frame has at least one opening, and at least one substrate unit is placed in the opening. The frame is fixed to the frame with two adhesives. Both are good substrate strips that can be used in semiconductor packaging, and will not produce defective post-packaged semiconductors due to defective ^ plate units, so as to increase the production capacity of the packaging process. The present invention also provides a method for manufacturing the substrate strip. First, A substrate strip is provided which has a plurality of substrate units integrally formed with a frame, and the plurality of base units includes at least one defective substrate unit. Then, the defective substrate unit is removed from the substrate strip, and thus At least one opening is left in the frame. After that, a good substrate unit is placed in the opening in the frame. Finally, an adhesive is used in the opening. The good substrate unit is fixed in the frame. The good substrate unit is removed from other substrate strips that are eliminated. According to this method, the good substrate units on the eliminated substrate strips can be used, and the expenditure of the substrate manufacturer is saved. The above and other features and objects of the invention will be easier to understand from the detailed descriptions associated with the illustrations below. [Explanation of the Invention] FIG. 2 is a top view of a substrate strip 200 according to a preferred embodiment of the present invention. The substrate strip 200 includes two first substrate units 200 and a frame 204, and the substrate strip 200 has two other openings 205. The two second substrate units 203 are respectively placed in the openings. An adhesive 212 is fixed to the frame 204 in 205. The substrate strip 2 0 0 preferably has a plurality of decasting washing channel areas 2 1 and 0 from the frame.

K:\POM15.ptc 第7頁 499750 __案號90123850 年月日 修正_^ 五、發明說明（5) 架204延伸至該第一及第二基板單位202、203，該去鑄澆 道區2 1 0恰能在該半導體晶片封膠時，將模具上之澆道以 及澆道口之邊緣完全密接在該去鑄澆道區中，在封膠之後 原在澆道中及澆道口的封膠塑料留在該去鑄澆道區2 1 〇 上。該去鑄澆道區2 1 0上係覆蓋有一層與封膠塑料結合的 能力較弱之金屬材質，因此有助於去除該去鑄澆道區21〇 上之封膠塑料。值得注意的是，將第二基板單元2 〇 3固接 於框架2 0 4之膠黏劑2 1 2係完全未覆蓋到該去鑄澆道區 210 ’以避免封膠後難以除去該去轉洗道區21〇上之封膠塑 料0 如第2圖所示，本發明之基板條2 〇 〇較佳具有有複數個狹 長縫20 6位於該第一及第二基板單元2〇2、2〇3的四周，使 得該第一及第二基板單元202、203僅部份連接於該框架 2 0 4。該狹長縫2 0 6係用以減輕作用於基板條之應力 (stress)，而有助於控制基板條不致因而皺曲變形 (warp)。本發明之基板條2〇〇較佳為一塑膠材質的層壓基 板條’用以同時大量地封裝半導體晶片。該基板條2 〇 〇較 佳地為矩形，其上之複數個基板單位較佳係為一球格陣列 基板。製造該基板條2 0 0之方法包括以下幾個步驟。如第3 圖所示，經過傳統製造過程的一基板條3〇〇經測試後包含 有兩個不良之基板單元302，隨即在該兩個不良基板單元 302上標上十字記號304以註明其為不良之基板單元。接著 將該不良基板單元302自該基板條3 00裁下，較佳地以衝切 (punch)的方式裁切下該不良基板單元3〇2。值得注意的K: \ POM15.ptc Page 7 499750 __Case No. 90123850 Rev. _ ^ V. Description of the invention (5) The frame 204 extends to the first and second substrate units 202 and 203, and the cast casting area 2 1 0 Just when the semiconductor wafer is sealed, the gate of the mold and the edge of the gate are completely sealed in the de-casting runner area. After sealing, the original plastic in the runner and the gate is sealed. Stay on this de-cast runner area 2 10. The de-casting runner area 2 10 is covered with a layer of metal material with weak ability to combine with the sealing plastic, so it is helpful to remove the sealing plastic on the de-casting runner area 21. It is worth noting that the adhesive 2 1 2 that fixes the second substrate unit 2 03 to the frame 2 0 is not covered at all in the de-cast runner area 210 ′ to avoid the difficulty in removing the de-rotation after sealing. Sealing plastic 0 on the washing channel area 21 as shown in FIG. 2, the substrate strip 200 of the present invention preferably has a plurality of slits 20 6 located on the first and second substrate units 202 and 2 Around 〇3, the first and second substrate units 202 and 203 are only partially connected to the frame 204. The slits 206 are used to reduce the stress acting on the substrate strip and help to control the substrate strip from warping. The substrate strip 2000 of the present invention is preferably a laminated substrate strip of plastic material, for packaging a large number of semiconductor wafers at the same time. The substrate strip 2000 is preferably rectangular, and the plurality of substrate units thereon is preferably a ball grid array substrate. The method for manufacturing the substrate strip 2000 includes the following steps. As shown in Figure 3, a substrate strip 300 that has undergone the traditional manufacturing process is tested and contains two defective substrate units 302, and then the two defective substrate units 302 are marked with a cross mark 304 to indicate that they are Defective substrate unit. Then, the defective substrate unit 302 is cut from the substrate strip 300, and the defective substrate unit 30 is preferably cut by punching. worth taking note of

K:\POM15.ptcK: \ POM15.ptc

499750 案號 9012385(1 五、發明說明（6) 疋’在本發明中將基板單元裁切下時，僅需裁切基板單元 與框架204部份連接之處，而在該框架204開口留下複數個 裁切邊緣4 02 (參見第4圖），並且在裁切下之基板單元上 之相對位置留下複數個連接邊緣502 (參見第5圖）。僅裁 切基板單元與框架204部份連接之處，不但可以使裁切的 步驟谷易進行’而且也避免在裁切的過程中使該基板條受 到過大的應力影響而產生扭曲變形。該基板條上較佳地另 具有複數個裁切孔208位於該第一及第二基板單元2〇2、 2〇3之角落處。該裁切孔2〇8能在將單一基板單元或封裝好 之封裝構造單元自該基板條2〇〇分離下來之時，幫助該基 板單元或封狀構造單元保有平整切面。因此本發明中，為 了提鬲裁切下之單一基板單元的一致性，將基板單元自基 板條裁切下時，其切面較佳地通過該裁切孔2〇8，以得到 一平整且固定之裁切邊緣4〇2及連接邊緣502，而幫助單一 良好基板單元5 0 0吻合該框架2 〇 4之開口 2 0 5。 該基板條300在其上之不良基板單元3〇2被取下後，留下 =個開口 205。然後將如第5圖所示之良好基板單元5 0 0 , =別置於該開口2〇5中。最後塗上膠黏劑21 2使該良好基板 f元500固接於該基板條2〇〇之框架2〇4上。值得注意的 疋’該膠黏劑21 2之塗覆應完全避開該去鑄澆道區2 1 〇 ,以 避免封膠後難以除去該去铸澆道區21〇上之封膠塑料。 第5圖所示之良好基板單元5 〇〇較佳係自一淘汰之基板條 裁下’裁切的方式較佳與將不良基板單元302自該基板 條2 0 〇裁下的方式相同，以得到大小形狀大致相同於該裁 切下之不良基板單元302。499750 Case No. 9012385 (1 V. Description of the invention (6) 时 'In the present invention, when the substrate unit is cut, only the portion where the substrate unit is connected to the frame 204 needs to be cut, and the opening of the frame 204 is left. A plurality of cutting edges 4 02 (see FIG. 4), and a plurality of connecting edges 502 (see FIG. 5) are left at the relative positions on the cut substrate unit. Only the substrate unit and the frame 204 are cut The connection place can not only make the cutting step easier, but also avoid distorting the substrate strip from being subjected to excessive stress during the cutting process. The substrate strip preferably has a plurality of cuttings. The cutting hole 208 is located at the corner of the first and second substrate units 202, 203. The cutting hole 208 can be used to separate a single substrate unit or a packaged packaging structure unit from the substrate strip 200. When separated, it helps the substrate unit or the sealed structural unit to maintain a flat cutting surface. Therefore, in the present invention, in order to improve the consistency of a single substrate unit that is cut, when the substrate unit is cut from the substrate strip, its cutting surface Preferably by the tailor Hole 208 to obtain a flat and fixed cutting edge 402 and connecting edge 502, and to help a single good substrate unit 500 match the opening 205 of the frame 204. The substrate strip 300 is After the bad substrate unit 302 is removed, there are = openings 205. Then, a good substrate unit 5 0 0 as shown in FIG. 5 is not placed in the opening 2 05. Finally, it is coated Adhesive 21 2 fixes the good substrate 500 to the frame 200 of the substrate strip 200. It is worth noting that the coating of the adhesive 21 2 should completely avoid the casting. The channel area 2 1 0, to avoid the difficult to remove the sealing plastic on the de-cast runner area 21 0 after sealing. The good substrate unit 500 shown in Figure 5 is preferably cut from a discarded substrate strip. The method of cutting is preferably the same as the method of cutting the defective substrate unit 302 from the substrate strip 200 to obtain the defective substrate unit 302 having the same size and shape as the cut.

499750 千 茶號！JU123850 五、發明說明（7) 將以上述方法獲得之該良好基板單元5 0 〇置入基板條2 〇 〇 之框架204上之開口 205時，由於該良好基板單元5〇〇大小 形狀，裁切下之不良基板單元3〇2大致一致，因此該良好 基板早TC500能大致吻合該開口 2〇5，且使該良好基板單元 500之連接邊緣5〇2恰對準相對位置之該框架2〇4上之裁切 邊緣4 02，再於連接處塗上膠黏劑212將該良好基板單元 500固接於該基板條2〇〇，因此在裁下—再固接上的過程中 仍能保持基板條200上之各個基板單元具有大致一致之相 對位置，不會有額外校正或對準的困難。 根據本發明較佳實施例之基板條2〇〇 為良好基板單元，因此皆可用於之後的封裝製程而不至因 之基板導致封裝材料及時間的浪費’特別適用於以基 3ίίί封裝構造如球格陣列封裝構造，可有效地提高 二# 之產率，降低封裝廠商的成本。此外對基板製 製造此種基板條既可使用原有之基板條生產 ίίϋ ί 又不必放棄具有多個不良基板單元之 :提好基板單元’亦可節省基板製造廠商之成本 雖然本發明已以前數較伟音始/丨_ 定本發明，任何熟習此技,4=:二!其並非用以限 範圍内，當可作各種之；；ί修；明之精神1° 圍當視後附之令請專利範圍所界定者為準。《明之保4犯 K:\P01-H5.ptc 麵 第10頁 499750 修正 案號 90123850 圖式簡單說明 【圖示說明】 第1圖 第2圖 第3圖 第4圖 傳統球格陣列板導體封裝構造之剖視圖； 根據本發明一較佳實施例之基板條之上視圖 具有兩個不良基板基板早元條之上視圖， 具有兩個開口基板條之上視圖； 第5圖 單 —- 良 好 基板單元 之上視圖< 【圖號說明】 102 晶 片 104 接 線 106 基 板 108 銲 球 110 黏 貼 材 料 112 包 覆 體 114 通 孔 200 基 板 條 202 第 一 基 板 單 203 第 二 基 板 單 元 204 框 架 205 開 σ 206 狹 長 縫 208 裁 切 孔 210 去 鑄 澆 道 區 212 膠 黏 劑 300 基 板 條 302 不 良 基 板 單 元 304 十 字 記 號 402 裁 切 邊 緣 500 良 好 基 板 單 元 502 連接 邊 緣499750 thousand tea number! JU123850 V. Description of the invention (7) When the good substrate unit 500 obtained by the above method is placed in the opening 205 on the frame 204 of the substrate strip 2000, the good substrate unit 500 is cut due to the size and shape of the substrate The lower defective substrate unit 302 is approximately the same, so the good substrate TC500 can roughly match the opening 205, and the connecting edge 502 of the good substrate unit 500 is aligned with the frame 204 at the opposite position. The cutting edge 4 02 on the top, and then apply the adhesive 212 to the connection to fix the good substrate unit 500 to the substrate strip 200, so the substrate can be maintained during the cutting-re-fixing process. Each substrate unit on the strip 200 has a substantially uniform relative position, and there is no difficulty in additional calibration or alignment. The substrate strip 200 according to the preferred embodiment of the present invention is a good substrate unit, so it can be used for subsequent packaging processes without wasting packaging materials and time due to the substrate. It is particularly suitable for packaging structures such as balls with a base 3 The grid array package structure can effectively increase the yield of the two ## and reduce the cost of the packaging manufacturer. In addition, for the production of such substrate strips by substrates, it is possible to use the original substrate strips to produce ίϋϋ ί without having to give up having multiple defective substrate units: improving the substrate unit 'can also save the cost of substrate manufacturers although the present invention has been counted Beginning of the invention / 丨 _ Defining the present invention, anyone who is familiar with this technique, 4 =: two! It is not intended to be used within a limited range; it can be used for various purposes; 修 repair; the spirit of Ming 1 ° encircled when you see the order The patent scope shall prevail. "Mingzhibao 4 Criminals K: \ P01-H5.ptc Surface Page 10 499750 Amendment No. 90123850 Schematic Description [Illustration] Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 4 Traditional ball grid array board conductor package A sectional view of the structure; a top view of a substrate strip according to a preferred embodiment of the present invention has a top view of two bad substrate substrate early strips and a top view of two open substrate strips; FIG. 5 Single --- Good substrate unit Top view < [Illustration of drawing number] 102 Wafer 104 Wiring 106 Substrate 108 Solder ball 110 Adhesive material 112 Cover 114 Through hole 200 Substrate strip 202 First substrate single 203 Second substrate unit 204 Frame 205 Open σ 206 Slit 208 Cutting hole 210 De-cast runner area 212 Adhesive 300 Substrate strip 302 Bad substrate unit 304 Cross mark 402 Cutting edge 500 Good substrate unit 502 Connection edge

K:\POM15.ptc 第11頁K: \ POM15.ptc Page 11

Claims (1)

499750499750 基板單元 、一種基板條，具有複數個基板單元，該每一 用於封裝一半導體晶片，該基板條包含··〜一 框架’其具有至少一開口，· 至少一第一基板單元與該框架一體成型； 。至少一第二基板單元設於該開口之内，並且該 早7G係利用一膠黏劑固接於該框架；以及 弟一土板 複數個狹長縫設於該第一基板單元以及該一 ，圍而大致將該第-基板單元及第二基板單。該：： 隔開，其中該複數個狹長縫係界定複數個連接部傕^ 基板單元僅藉由該複數個連接部份而連接於該框于各 其中該膠黏劑係僅設於該第二基板單元與該框架^被談 數個狹長縫所界定之連接部份。 ^ 1 2、 依申請專利範圍第1項之基板條，其中該基板條 複數個去鑄潦道區設於該基板條之一表面使得在讀導$ 晶片封膠時’用以將该半導體晶片封於封膠塑料之模 模具洗道以及洗道口之邊緣係完全密接在該道巴 中’其中將第二基板單元固接於柩架之膠黏』二= 蓋到該去鑄洗道區。 3、 依申請專利範圍第1項之基板條，丨中該基板條係為塑 膠基板。 4、依申請專利範圍第1項之基板條，其中每一基板單元係A substrate unit, a substrate strip, having a plurality of substrate units, each of which is used to package a semiconductor wafer, the substrate strip includes a frame 'which has at least one opening, and at least one first substrate unit is integrated with the frame Molding; At least one second substrate unit is disposed within the opening, and the early 7G system is fixed to the frame with an adhesive; and a small soil plate is provided with a plurality of slits in the first substrate unit and the one, The first substrate unit and the second substrate unit are roughly singled. The :: separated, wherein the plurality of slits define a plurality of connection portions 傕 ^ The substrate unit is connected to the frame only by the plurality of connection portions, wherein the adhesive is provided only on the second The base unit and the frame are connected by a plurality of slits. ^ 1 2. The substrate strip according to item 1 of the scope of the patent application, wherein the substrate strip is provided with a plurality of decasting lanes on one surface of the substrate strip so that the semiconductor wafer is sealed when the wafer is sealed. The edges of the washing channel of the mold and the sealing channel of the sealing plastic are completely tightly sealed in the road bar. 'The adhesive for fixing the second substrate unit to the stent.' Second = Cover the de-casting channel area. 3. According to the substrate strip of item 1 of the scope of patent application, the substrate strip is a plastic substrate. 4. The substrate strip according to item 1 of the scope of patent application, wherein each substrate unit is K:\P0M15.ptc 第12頁 499750 案號 90123850 六、申請專利範圍 為一球格陣列基板 月 日 修正 5、一種製造基板條之方法，其包含： (a) ^供具有複數個基板單元、一框架以及複數個狹 長縫=第一基板條，其中該複數個狹長縫係設在該複數個 基板單元的周圍將各基板單元與該框架分開使得各基板單 元僅有部份連結於框架，並且該複數個基板單元至少有一 個疋不良基板單元（defective substrate unit); (b) 裁切該第一基板條上之不良基板單位與該框架之該 部分連接部份，將該不良基板單元自該第一基板條分離取 下並於該第一基板條上留下一開口； (c) 提供一良好的基板單元； (d) 將ό亥良好单位基板置入該第一基板條之開口中，·以 及 (e) 將該良好基板單元固接於於該第一基板條之框架。 6、 依申請專利範圍第5項之製造基板條之方法，其中該良 好的基板單元係由一第二基板條上分離取下。 7、 依申請多利範圍第6項之製造基板條之方法，其中自第 一基板條取下之該不良基板單元與該良好基板單元大小形 狀大致一致。 8、 依申請專利範圍第5項之製造基板條之方法，另提供複 K:\P0M15.ptc 第13頁 499750K: \ P0M15.ptc Page 12 499750 Case No. 90123850 6. The scope of the patent application is a one-day grid array substrate correction on the day of the day 5. A method of manufacturing a substrate strip, which includes: (a) ^ for a plurality of substrate units, A frame and a plurality of slits = a first substrate strip, wherein the plurality of slits are provided around the plurality of substrate units to separate each substrate unit from the frame so that each substrate unit is only partially connected to the frame, and The plurality of substrate units have at least one defective substrate unit; (b) cutting the defective substrate unit on the first substrate strip and the connecting portion of the part of the frame, and removing the defective substrate unit from the The first substrate strip is separated and removed and an opening is left on the first substrate strip; (c) providing a good substrate unit; (d) placing a good unit substrate into the opening of the first substrate strip, And (e) fixing the good substrate unit to a frame of the first substrate strip. 6. The method for manufacturing a substrate strip according to item 5 of the scope of patent application, wherein the good substrate unit is separated and removed from a second substrate strip. 7. The method for manufacturing a substrate strip according to item 6 of the application, in which the size of the defective substrate unit and the good substrate unit that are removed from the first substrate strip are substantially the same. 8. According to the method of manufacturing the substrate strip according to item 5 of the scope of patent application, another copy K: \ P0M15.ptc page 13 499750 is provided. 案號 90123850 六、t請專利範® 數個去鑄澆道 於該基寺反{冬之_.主 Η科朦拄田LV從兮*、首” 表面上使得在該半導體晶 ί晶片封於封膠塑料之模具的模 η緣係完全密接在該去鑄洗道區之 :中，驟(e)包含一步驟將_膠黏劑塗佈於該良好 基板：兀，、該第一基板條之框架之間之介面四 但不塗佈到該去鑄澆道區之區域。 找 9、依申請專利範圍第5項之製造基板條之方法，盆 (b)係使用衝切方式達成分離。 ，、驟 1 0、依申請專利範圍第5項之製造基板條之方法，其 基板條係為塑膠基板。 、以 ?柘：申:!專利範圍第5項之製造基板條之方法，1中各 基板早疋係為球格陣列基板。 八中各Case No. 90123850 VI. Please ask for patents. A number of casting gates are placed on the base of the temple. {Winter of _. Main Department of Science and Technology 拄 LV from Xi *, First "on the surface of the semiconductor wafer The mold edge of the mold for sealing the plastic is completely in close contact with the decasting and washing channel area: step (e) includes a step of applying the adhesive to the good substrate: the first substrate strip, The interface 4 between the frames is not applied to the area of the de-cast runner area. Find 9. According to the method of manufacturing substrate strips in the scope of patent application No. 5, the pot (b) is separated by punching. Step 10: The method of manufacturing a substrate strip according to item 5 of the scope of patent application, the substrate strip is a plastic substrate. The method of manufacturing a substrate strip according to item 5 of the patent scope, 1 Each substrate is a ball grid array substrate.
TW90123850A 2001-09-26 2001-09-26 Substrate strip and its manufacturing method TW499750B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7445944B2 (en) 2006-08-23 2008-11-04 Ase (Shanghai) Inc. Packaging substrate and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7445944B2 (en) 2006-08-23 2008-11-04 Ase (Shanghai) Inc. Packaging substrate and manufacturing method thereof

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