A7 B7 m4.c^r/f^S 五、發明説明（ί ) 本發明是有關於一種微細線路製作及轉印方法，且特 別是有關於一種具有微細線路之單面板（Single-Sided Board)的製作方法。 積體電路之封裝（Package)，其目的在於提供晶片（Die) 與印刷電路板（Printed Circuit Board, PCB)或其他適當元件 之間電性連接的媒介、以及保護晶片，爲製作積體電路成 品的最後步驟。 近年來，爲因應電子產品日益輕、薄、短、小之趨勢， 已發展出許多不同的封裝技術。Tessera公司開發出一種 利用單面板進行小而薄的單晶片封裝，稱爲微型球格陣列 (Micro Ball Grid Array, pBGA)，可應用於製作動態隨機存 取記憶體（Dynamic Random Access Memory, DRAM)、 Rambus 連線記憶體模組(Rambus In-Line Memory Module, RIMM)等。 請參照第1圖，其所繪示的是微型球格陣列封裝基板 '之剖面示意圖。如圖所示，微型球格陣列係使用聚亞醯胺 (Polyimide)軟質基板100進行封裝，軟質基板100之表面 覆有具所需線路圖案的導線102。而聚亞醯胺基板100中， 則具有巳定義之基板圖案，以配合焊接球（Solder Bail)與 導線102的電性連接、及焊接球之間的電性阻絕等需求= 傳統之線路製作，主要是在表面覆有銅質金屬層的電 路基板上。先塗佈光阻層（Photoresist, PR)，經曝光、顯影 後，將所需之線路圖案轉移至光阻層中。再以圖案化之光 阻層爲罩幕（Mask)，對銅質金屬層進行蝕刻，於電路基板 本紙张尺度適州肀國國家標準（CNS ) Α4規格（210Χ 297公嫠） (-"先閱讀背面之注意事項再"艿本页)A7 B7 m4.c ^ r / f ^ S V. Description of the Invention The invention relates to a method for making and transferring a fine circuit, and in particular to a single-Sided Board with a fine circuit. Production method. Package of integrated circuit, the purpose of which is to provide a medium for the electrical connection between the die and the printed circuit board (PCB) or other appropriate components, and to protect the chip. Last step. In recent years, many different packaging technologies have been developed in response to the trend of electronic products becoming lighter, thinner, shorter, and smaller. Tessera has developed a small and thin single-chip package using a single panel, called a Micro Ball Grid Array (pBGA), which can be used to make Dynamic Random Access Memory (DRAM) , Rambus In-Line Memory Module (RIMM), etc. Please refer to FIG. 1, which illustrates a schematic cross-sectional view of a miniature ball grid array package substrate ′. As shown in the figure, the miniature ball grid array is packaged with a polyimide flexible substrate 100, and the surface of the flexible substrate 100 is covered with a conductive wire 102 having a desired circuit pattern. The polyurethane substrate 100 has a substrate pattern defined by 巳 to match the electrical connection between Solder Bail and wire 102, and electrical resistance between solder balls. Traditional circuit production, It is mainly on a circuit substrate covered with a copper metal layer on the surface. First apply a photoresist (PR) layer, and after exposure and development, transfer the required circuit pattern to the photoresist layer. Then the patterned photoresist layer is used as a mask to etch the copper metal layer, and the paper size of the circuit board is in accordance with the national standard (CNS) A4 specification (210 × 297 mm) of the paper (-" (Read the precautions on the back before quoting this page)
*1T 418469 A7 Γ ^t.o/oo.s B7 五、發明説明（> ) 上形成具有所需線路圖案的導線。 第2A圖至第2C圖，其所繪示的是以習知蝕刻方法 製作之線路的剖面示意圖。以具有線路圖案之光阻層爲罩 幕，對硬質封裝基板表面之銅質金屬層進行蝕刻，於封裝 基板上形成導線。請參照第2A圖，一般而言，於硬質封 裝基板2〇〇上形成之導線202a，其剖面輪廓（Profile)如圖 所示。請參照第2B圖，對第2A圖中之結構進行蝕刻以 縮減其導線之線寬時，將使位於硬質封裝基板200上導線 2〇2b的剖面輪廓里上窄f寬之梯形。若繼續進行蝕刻，則 會產生如第2C圖所示之導線202c的構型，位於封裝基板 200上之導線202c，其線寬雖已縮小，然其輪廓則略呈三 角形。因此，使用習知蝕刻形成線路之方法所製作之導線， 其線寬最小僅可達75微米（Micron)。若繼續以蝕刻縮減線 寬’將造成導線剖面輪鄭改變，並;導致電阻値升高等，進 而影響導線本身之電性特性及封裝成品之品質和工作效 率。而以圖案化之光阻層爲罩幕，使用加成法製程(Additi ve Process)，於封裝基板上沈積形成導線，其所需之生產時 間較長，因IW無法降低生產工時及提高產能。 因此本發明提供一種微細線路製作及轉印方法，利用 具有所需線路圇案之光阻餍爲罩幕，以電鍍方式於光阻層 圖案之間的線路載板上形成導線。其次將封裝基板與導線 壓含，再使線路載板、導線及封裝基板之疊合結構與剝離 基板分離：然後移除線路載板，即可將導線轉印至封裝基 板上，得到由封裝基板及導線之疊合結構，完成具有微細 4 *-"先閱讀背面之注意事項再填艿本頁j* 1T 418469 A7 Γ ^ t.o / oo.s B7 V. Description of the invention (>) A wire having a desired wiring pattern is formed on the invention. Figures 2A to 2C are schematic cross-sectional views of a line made by a conventional etching method. Using a photoresist layer with a circuit pattern as a mask, the copper metal layer on the surface of the rigid package substrate is etched to form a lead on the package substrate. Please refer to FIG. 2A. Generally, the cross-section profile of the lead 202a formed on the rigid package substrate 2000 is as shown in FIG. Please refer to FIG. 2B. When the structure in FIG. 2A is etched to reduce the line width of the wires, a trapezoid with a narrow f width in the cross-sectional profile of the wires 202b on the rigid package substrate 200 will be made. If the etching is continued, the configuration of the lead 202c shown in FIG. 2C will be generated. Although the lead 202c on the package substrate 200 has a reduced line width, its outline is slightly triangular. Therefore, the minimum wire width of a wire made using a conventional etching method to form a circuit is only 75 micrometers (Micron). If you continue to reduce the line width by etching, it will cause a change in the profile of the wire, and lead to an increase in resistance 値, which will affect the electrical characteristics of the wire itself and the quality and efficiency of the packaged product. The patterned photoresist layer is used as a mask and the additive process is used to deposit and form wires on the packaging substrate, which requires a longer production time, because IW cannot reduce the production man-hours and increase the production capacity. . Therefore, the present invention provides a method for manufacturing and transferring a fine circuit, using a photoresist having a desired circuit scheme as a cover, and forming a conductive line on a circuit carrier board between the photoresist layer patterns by electroplating. Secondly, the package substrate and the wire are pressed, and the circuit carrier, the superposed structure of the wire and the package substrate are separated from the peeling substrate: Then the circuit carrier is removed, and the wires can be transferred to the package substrate to obtain the package substrate And wire superimposed structure, complete with fine 4 *-" Read the precautions on the back before filling in this page j
,1T 本紙张尺度適州十國國家標準（CNS ) Λ4規格（210X297公釐） 4 4 A7 B7 4 37(uwi' d〇c/(U)i； 五、發明说明（3 ) 線路之單面板的製作。 -誚先閲讀背面之注意事項再填荇本頁) 根據本發明之上述及其他目的，提出一種微細線路製 作及轉印方法，使用表靣覆有剝離層之剝離基板，於剝離 基板上電鍍形成線路載板，用以承載後續製作之導線^在 線路載板上塗佈光阻層，經曝光、顯影後，將所需之線路 圖案轉移至光阻層。以具有線路圖案之光阻層爲罩幕，於 線路載板上電鍍形成導線，再將光阻層移除。其次，以硬 質封裝基板與線路載板上之導線壓合，然後將線路載板、 導線及硬質封裝基板之疊合結構，由剝離層表面剝離。而 後再把線路載板移除，將微細線路轉印至封裝基板、以及 完成具有微細線路之單面板的製作。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示微型球格陣列之封裝基板的剖面示意圖 第2A圖至第2C圖繪示以習知方法製作之線路的剖 面示意圖；以及 :Α 部 t il 尤) ii .1 消 f, 印 t 第3A圖至第3H圖繪示依照本發明之較佳實施例， 一種微細線路製作及轉印方法’其製作流程之剖面示意 圖 圖式之檫記說明： 1〇〇 :聚亞醯胺基板 102、202a、202b、202c、310 :導線 本紙張尺度適州中國國家樣隼（CNS ) Λ4規格{ 210X297公楚） ίίΑΜ3η^ ΑΊ ___ _ B7 五、發明説明（4 ) 200 :硬質封裝基板 3 0 0 :剝離模板 3 02 :剝離層 304 :剝離基板 3 0 6 :線路載板 308 :具線路圖案之光阻層 312 :具基板圖案之封裝基板 實施例 第3A圖至第3H圖，其所繪示的是依照本發明之較 佳實施例，-種微細線路製作及轉印方法，其製作流程之 剖面示意圖。 請參照第3A圖，首先提供剝離基板304，以供製作 線路之用，此剝離基板304係由剝離模板300及剝離層 (Release Film)302所疊合而成。其中剝離模板300之材質 包括不銹鋼（Stainless Steel)等，而剝離層302則是位於剝 離模板300之表面。形成剝離層302之方法例如是電鍍法 (Plating)，而其付質則包括鉻（Cr)、鈦(Ti)等非銅金屬。 其次請參照第3B圖，在剝離基板304之表面，形成 線路載板（CarrieOSOG，作爲承載後續步驟製作之線路所需 的載台。形咴線路載板3 06之方法例如是電鍍法，其材質 包括銅（Cn).而線路載板306之厚度約爲0·5微米（Micron) 至20微米，較佳的厚度範圍約爲5微米至〗5微米。 円:請參照第3C圖，於線路載板306之表面’形成具 有所需線路圖案之光阻層308，並且使線路載板306之部 6 本紙ΪΡ·尺度適;U中國國家標率（CNS ) Λ4規格（210X297公釐） --:---L-------^------訂------产 I - -(-誚九間讀背面之注意事項再：^寫本頁) 418469, 1T This paper is the national standard of the 10 countries in China (CNS) Λ4 specification (210X297 mm) 4 4 A7 B7 4 37 (uwi 'doc / (U) i; 5. Description of the invention (3) Single panel of the circuit -诮 Read the precautions on the back before filling this page) According to the above and other purposes of the present invention, a method for making and transferring a fine circuit is proposed. A release substrate covered with a release layer is used on the release substrate. A circuit carrier board is formed by electroplating, which is used to carry the wires produced later. A photoresist layer is coated on the circuit carrier board. After exposure and development, the required circuit pattern is transferred to the photoresist layer. A photoresist layer with a circuit pattern is used as a mask, and a conductive line is formed on the circuit carrier plate by electroplating, and then the photoresist layer is removed. Second, the hard package substrate and the wires on the circuit carrier board are pressed together, and then the laminated structure of the circuit carrier board, the wires and the hard package board is peeled off from the surface of the release layer. Then, the circuit carrier board is removed, the fine circuits are transferred to the package substrate, and the production of the single panel with the fine circuits is completed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 A schematic cross-sectional view of a package substrate of a miniature ball grid array is shown in Figs. 2A to 2C, which are schematic cross-sectional views of a circuit made by a conventional method; and: A part t il especially) ii .1 f, printed t 3A FIG. 3 to FIG. 3H illustrate a method for manufacturing and transferring a fine circuit according to a preferred embodiment of the present invention, and a description of a schematic cross-sectional view of the manufacturing process: 100: Polyurethane substrates 102, 202a, 202b, 202c, 310: Paper size of wire: China National Sample (CNS) Λ4 specification {210X297 Gongchu) ίίΑΜ3η ^ Α _ _ B7 V. Description of the invention (4) 200: Hard package substrate 3 0 0: Stripping template 3 02: peeling layer 304: peeling substrate 3 06: circuit carrier board 308: photoresist layer with circuit pattern 312: package substrate with substrate pattern Examples 3A to 3H, which are shown in accordance with A preferred embodiment of the present invention, a fine line Production and transfer method, which is a cross-sectional schematic view of the production process. Referring to FIG. 3A, a peeling substrate 304 is first provided for use in making a circuit. The peeling substrate 304 is formed by stacking a release template 300 and a release film 302. The material of the peeling template 300 includes stainless steel, and the peeling layer 302 is located on the surface of the peeling template 300. The method of forming the peeling layer 302 is, for example, a plating method, and its properties include non-copper metals such as chromium (Cr) and titanium (Ti). Secondly, referring to FIG. 3B, a circuit carrier board (CarrieOSOG) is formed on the surface of the peeled substrate 304 as a carrier required for carrying the circuits produced in the subsequent steps. The method of forming the circuit carrier board 306 is, for example, an electroplating method and its material Including copper (Cn). The thickness of the circuit carrier board 306 is about 0.5 micron to 20 micrometers, and the preferred thickness range is about 5 micrometers to 5 micrometers. 円: Please refer to Figure 3C for the circuit The surface of the carrier plate 306 is formed with a photoresist layer 308 having a desired circuit pattern, and the portion of the circuit carrier plate 306 is made of paper. The size is appropriate; U China National Standards (CNS) Λ4 specification (210X297 mm)- : --- L ------- ^ ------ Order ------ Production I--(-Notes on the back of Jiu Jianjian Re: ^ Write this page) 418469
Α Λ 761\\ r.doc/OON A7 B7 部 it r.} 五、發明説明（（） 份表面曝露出來。其步驟則包括：於線路載板306上塗佈 光阻層，再進行曝光及顯影，將所需之線路圖案轉移至光 阻層中。 接著請參照第3D圖，以具有線路圖案之光阻層308 爲罩幕，於線路載板3〇6未覆有光阻層308之表面上，按 所需線路圖案形成導線：no。其製作方法係以選擇性方式， 於線路載板3〇6曝露部份之表面上形成導線310 ,較佳的 方法是電鍍法。而導線310之線寬及線距（Pitch)則約爲25 微米。 請參照第3E圖，將具有已定義之線路圖案的光阻層(第 3E圖中之3〇8)移除，使線路載板306上僅覆有具所需線 路圖案之導線310，以利後續步驟的進行，將導線3 10轉 印（Transfer)至其他基板上。 然後請參照第3F圖，以封裝基板312與導線310壓 合（Compression)。其中封裝基板3 I2係使用樹脂片（Prepreg) 製成’例如是以玻璃環氧基樹脂爲材質之FR-4基板、以 雙順]丨布—酸酷亞胺（Bisma丨eimide-Triazine, BT)樹脂爲材 質之BT基板等所製作而成。此外，爲符合焊接球與導線 3 10之間電性連接、以及焊接球之間的電性阻絕等需求， 在封裝基板312中還具有已定義之基板圖案。而形成基板 圖案之方法包括使用機械鈷孔、雷射鑽孔等。 再請參照第3G圖，使覆於剝離基板（第3F圖中之304) 表面的線路載板306、導線310及封裝樹脂片312所構成 之#台結構，山剝離基板的剝離層(第3F圖中之302)分離。 本紙張尺度通财图國家標準（CNS ) M規格（21〇χ297公楚） t先閱讳背面之注意事項"'试巧本頁) 4 184 6 9 a7 — _ —~~~一 五、發明说明（〔） 使用非銅質剝離層與銅質線路載板306 ’可利用其材質不 同，以便於將其分離。 最後請參照第3Η圖，使用例如濕式蝕刻等方法，移 除第3G圖中覆於導線310上之線路載板3〇6，將導線310 轉印至封裝基板3丨2，並獲得由具有定義圖案之封裝基板 312與具有所需線路圖案之導線31〇疊合而成之單面板結 構，π:ί以應用於例如球格陣列封裝基板等，亦可作爲微型 球格陣列WBGA)之封裝基板。 由上述本發明較佳實施例可知，本發明係利用光阻層 爲罩幕，以電鍍方式於光阻層之間、線路載板上形成導線。 電鍍形成之銅質導線的電性特性佳，而且其與線路載板之 間的附著性亦佳。由於可以製作線寬及線距較小之導線， 因而得以提高佈線密度（Layout Density)，並可縮小封裝基 板所需之面積及封裝成品之體積，減少封裝成品之厚度和 重量。此外，電鍍形成銅質導線所需的時間較短，故可縮 減生產工時、降低生產成本及提高產能。本發明所述之微 細線路製作及轉印方法，可應用於製作輸入/輸出接點較 少之封裝基板（單面板應用本發明，可設計及製作數層 不同電路之屮间板，並利用適當的界面接合（Interconnect) 將运哄單向彳咬暫合’即司構成雙面基板或積層（Laminate) 基板’故亦π]‘適闬於製作輸入/輸出接點較多之封裝基板。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’仟何熟習此技藝者，在不脫離本發明之精神 和範圍內，常呵作各種之更動與潤飾，因此本發明之保護 ' ί-ϊί先閱讀背面之注意事項再禎κ本頁) 訂 -Ί· 1- 本纸乐尺度述/11屮國國家標準（CNS ) Λ4規格（2]〇X297公楚> A7 B7 ^^•部屮呔枒^^^厂^消爹^竹^印"·'1-^ 4 18469Α Λ 761 \\ r.doc / OON A7 B7 Section it r.} 5. The description of the invention (()) The surface is exposed. The steps include: coating a photoresist layer on the circuit substrate 306, and then exposing and Develop and transfer the required circuit pattern to the photoresist layer. Then refer to Figure 3D, using the photoresist layer 308 with the line pattern as a mask, and the circuit carrier board 306 is not covered with the photoresist layer 308. On the surface, a conductive wire is formed according to a desired circuit pattern: no. The manufacturing method is to selectively form a conductive wire 310 on the surface of the exposed part of the circuit carrier board 306. The preferred method is electroplating. The conductive wire 310 The line width and pitch are about 25 microns. Please refer to Figure 3E to remove the photoresist layer (308 in Figure 3E) with a defined circuit pattern to make the circuit carrier board 306 It is covered only with the wires 310 with the required circuit pattern to facilitate the subsequent steps to transfer the wires 3 to 10 on other substrates. Then refer to Figure 3F and press the package substrate 312 and the wires 310 together. (Compression). The package substrate 3 I2 is made of resin sheet (Prepreg). Epoxy resin is made of FR-4 substrate, and bis]] cloth-acimide-triimine (BT) resin is made of BT substrate. In addition, it is compatible with solder balls The electrical connection with the wires 3 and 10, and the electrical resistance between the solder balls, etc., also have a defined substrate pattern in the package substrate 312. The method of forming the substrate pattern includes using mechanical cobalt holes, laser drills Holes, etc. Please refer to FIG. 3G again to make the #mount structure composed of the circuit board 306, the lead 310, and the encapsulating resin sheet 312 covering the surface of the release substrate (304 in FIG. 3F), and the release layer of the release substrate (302 in Fig. 3F). National paper standard (CNS) M standard (21〇297297) of this paper standard t Please read the precautions on the back of the paper " 'Testing this page） 4 184 6 9 a7 — _ — ~~~ 15. Description of the invention ([) Use of non-copper peeling layer and copper circuit carrier board 306 'can use different materials to facilitate their separation. Finally, referring to Figure 3, using a method such as wet etching, remove the circuit carrier 3006 overlaid on the wire 310 in Figure 3G, transfer the wire 310 to the packaging substrate 3, and obtain A single-panel structure in which a package substrate 312 defining a pattern is superposed with a wire 31 having a desired circuit pattern, and π: is used in, for example, a ball grid array package substrate, etc., and can also be used as a package of a miniature ball grid array (WBGA). Substrate. It can be known from the foregoing preferred embodiments of the present invention that the present invention uses a photoresist layer as a mask to form a conductive line between the photoresist layer and a circuit board by electroplating. The copper wire formed by electroplating has good electrical characteristics and good adhesion to the circuit carrier. Because it is possible to make wires with smaller line widths and spacings, it is possible to increase the layout density (Layout Density), reduce the area required for the packaging substrate and the volume of the packaged product, and reduce the thickness and weight of the packaged product. In addition, the time required to form copper wires by electroplating is shorter, which can reduce production man-hours, reduce production costs, and increase production capacity. The micro circuit manufacturing and transfer method described in the present invention can be applied to the production of packaging substrates with fewer input / output contacts. (Single-panel application of the present invention can design and fabricate interlayer boards with several layers of different circuits. Interconnect will cope with one-way interlocking, which means that it constitutes a double-sided substrate or a laminated substrate. Therefore, it is suitable for making packaging substrates with many input / output contacts. Although The present invention has been disclosed as above with a preferred embodiment, but it is not intended to limit the present invention. Anyone skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. Therefore, the present invention Protection 'ί-ϊί Read the precautions on the back first, and then 祯 本页 this page) Ί-Ί · 1- The scale of this paper / 11 National Standards (CNS) Λ4 Specifications (2) 〇297297 > A7 B7 ^^ • 部 屮 呔 桠 ^^^ 厂 ^ 消 消 ^ 竹 ^ 印 " · '1- ^ 4 18469
-1 3 7M u Γ. doc / (}() S 五、發明説明（9 ) 範圍當視後附之申請專利範圍所界定者爲準 -"先閱讀背面之注意事項再禎寫本頁j-1 3 7M u Γ. Doc / (} () S V. Description of invention (9) The scope shall be determined by the scope of the attached patent application-" Read the precautions on the back before writing this page j
，1T 1 本紙张尺度適用中囤國家標準（CNS ) Λ4規格（210X297公釐）， 1T 1 This paper size is applicable to the national standard (CNS) Λ4 specification (210X297 mm)