KR970019795A - 다층 회로기판 및 그 제조방법 - Google Patents

다층 회로기판 및 그 제조방법 Download PDF

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KR970019795A
KR970019795A KR1019950029688A KR19950029688A KR970019795A KR 970019795 A KR970019795 A KR 970019795A KR 1019950029688 A KR1019950029688 A KR 1019950029688A KR 19950029688 A KR19950029688 A KR 19950029688A KR 970019795 A KR970019795 A KR 970019795A
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insulating material
circuit board
substrate
conductive ink
multilayer circuit
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KR1019950029688A
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KR0155877B1 (ko
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류재철
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이대원
삼성항공산업 주식회사
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Priority to KR1019950029688A priority Critical patent/KR0155877B1/ko
Priority to JP25779996A priority patent/JP3765627B2/ja
Priority to TW85110973A priority patent/TW304323B/zh
Priority to DE1996136735 priority patent/DE19636735B4/de
Priority to US08/712,117 priority patent/US5747222A/en
Priority to CN96113395A priority patent/CN1107336C/zh
Publication of KR970019795A publication Critical patent/KR970019795A/ko
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Publication of KR0155877B1 publication Critical patent/KR0155877B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0568—Resist used for applying paste, ink or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Inks, Pencil-Leads, Or Crayons (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

다층 회로기판 및 그 제조방법이 개시되어있다.
이 다층 회로기판은 기판(10)과, 이 기판(10)상에 도포되고 소정 패턴을 가지는 포토마스크를 위치시켜 형성된 소정 패턴의 여백(22)를 가지는 감광성 절연물질(20)과, 이 감광성 절연물질(20)의 여백(22) 내부에 주입 및 경화되어 형성된 전도성 잉크(30)를 구비하고, 상기 전도성 잉크(30)가 여백(22) 내부에 주입된 감광성 절연물질(20)이 다수 적층되고, 그 상부에 금속박막(40)을 구비하여 부품 장착 부위가 평평하도록 된 것을 특징으로 한다. 또한, 그 제조방법은 기판상에 감광성 절연물질(20)을 도포하고, 소정패턴을 가지는 포토마스크를 위치시키고, 노광 및 현상을 통하여 감광성 절연물질(20)에 소정 형상의 여백(22)을 마련하고, 이 여백(22)에 전도성 잉크(30)를 프린트한후 경화시켜 단층의 기판을 완성하고, 그 상부에 다른 감광성 절연물질(20)을 도포, 패턴형성 및 전도성 잉크(30) 프린트 공정을 반복 수행한 후, 한층의 소정 패턴이 금속박막(40)을 형성하여 다층회로기판을 제조하는 방법이다.

Description

다층 회로기판 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 다층 회로기판을 나타낸 측단면도,
제2도는 본 발명에 따른 다층 회로기판 제조방법의 일실시예를 나타낸 공정도,
제3도는 본 발명에 따른 다층 회로기판 제조방법의 다른 실시예를 나타낸 공정도.

Claims (10)

  1. 기판과, 이 기판상 다층으로 적층되고 소정 패턴을 가지는 포토마스크를 위치시켜 형성된 소정 패턴의 여백을 가지는 감광성 절연물질과, 상기 여백 내부에 주입 및 경화되어 형성된 전도성 잉크(30)와, 상기 감광성 절연물질의 최상부에 접착성 절연물질에 의해 부착되고 식각에 의해 소정 패턴이 형성된 금속박막이 구비되고, 상기 기판과, 절연물질과, 금속박물을 관통하며 그 내부에 전도성 잉크가 내재된 관통공이 형성된 것을 특징으로 하는 다층 회로기판.
  2. 제1항에 있어서, 상기 전도성 잉크는 전기전달 및 프린트 된 후 쉽게 경화될 수 있도록 미세 금속분말과, 중합 반응물질과, 용매를 포함하는 것을 특징으로 하는 다층 회로기판.
  3. 제1항에 있어서, 상기 기판은 얼로이 42, 구리 얼로이 등의 금속 및/또는 세라믹 소재로 된 것을 특징으로 하는 다층 회로기판.
  4. 제3항에 있어서, 상기 기판이 금속으로 된 경우 이 기판을 감싸도록 절연물질이 도포된 것을 특징으로 하는 다층 회로기판.
  5. 제1항에 있어서, 상기 금속박막은 구리(cu) 박막인 것을 특징으로 하는 다층 회로기판.
  6. 기판을 준비하는 제1단계; 이 상부에 감광성 절연물질을 도포하는 제2단계; 상기 감광성 절연물질의 상부에 소정 패턴이 형성된 포토마스크를 위치시킨후 상기 감광성 절연물질에 상기 포토마스크의 패턴이 형성되도록 노광하는 제3단계; 상기 패턴이 형성된 감광성 절연물질을 현상하여 감광된 부분을 제거하여 여백을 형성하는 제4단계; 제거된 여백에 전기 전도성 잉크를 도포하는 제5단계;를 통하여 한층의 회로기판을 형성하고, 상기 한층의 회로기판상에 상기 제2단계에서 제5단계의 공정 단계를 순서대로 반복하여 복수층의 회로기판을 제조하고, 그 상부에 접착성 절연물질을 도포한후 금속박막을 열압착하여 부착하고, 소정 패턴이 형성되도록 식각하는 제6단계; 상기 기판, 다층의 회로기판 및 금속박막을 관통하며, 내부에 전도성 잉크가 주입된 관통공을 형성하는 제7단계;의 공정을 포함하는 것을 특징으로 하는 다층 회로기판 제조방법.
  7. 제6항에 있어서, 상기 전도성 잉크는 도포시 액체 상태를 유지하고, 가열에 의해 경화되도록 미세 금속분말, 중합 반응물질 및 용매를 포함하는 것을 특징으로 하는 다층 회로기판 제조방법.
  8. 제6항에 있어서, 상기 적층된 다층의 감광성 절연물질중 일부충의 절연물질에 대하여 제3단계 및 제4단계의 공정을 생략하고, 제7단계의 공정을 통하여 각 층이 전기적으로 관통되도록 형성된 것을 특징으로 하는 다층 회로기판 제조방법.
  9. 제6항에 있어서, 상기 기판은 구리 얼로이, 얼로이 42등의 금속, 세라믹 또는 절연물질로 이루어진 것을 특징으로 하는 다층 회로기판 제조방법.
  10. 제9항에 있어서, 상기 기판이 금속소재등의 전도성 물질로 이루어진 경우 제1단계와 제2단계 공정 사이에 상기 기판을 감싸도록 절연물질을 도포하는 단계를 더 포함하는 것을 특징으로 하는 다층 회로기판 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950029688A 1995-09-12 1995-09-12 다층 회로기판 및 그 제조방법 KR0155877B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950029688A KR0155877B1 (ko) 1995-09-12 1995-09-12 다층 회로기판 및 그 제조방법
JP25779996A JP3765627B2 (ja) 1995-09-12 1996-09-06 多層回路基板及びその製造方法
TW85110973A TW304323B (ko) 1995-09-12 1996-09-07
DE1996136735 DE19636735B4 (de) 1995-09-12 1996-09-10 Mehrschichtiges Schaltungssubstrat und Verfahren zu seiner Herstellung
US08/712,117 US5747222A (en) 1995-09-12 1996-09-11 Multi-layered circuit substrate and manufacturing method thereof
CN96113395A CN1107336C (zh) 1995-09-12 1996-09-12 多层电路基片及其制造方法

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KR1019950029688A KR0155877B1 (ko) 1995-09-12 1995-09-12 다층 회로기판 및 그 제조방법

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KR0155877B1 KR0155877B1 (ko) 1998-12-15

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JP (1) JP3765627B2 (ko)
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CN (1) CN1107336C (ko)
DE (1) DE19636735B4 (ko)
TW (1) TW304323B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483609B1 (ko) * 2002-07-27 2005-04-15 삼성전기주식회사 노이즈 차폐형 적층 기판의 제조방법

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* Cited by examiner, † Cited by third party
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JP2836616B2 (ja) * 1997-03-05 1998-12-14 日本電気株式会社 導体配線パターンの形成方法
US6021050A (en) * 1998-12-02 2000-02-01 Bourns, Inc. Printed circuit boards with integrated passive components and method for making same
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