TW202213693A - 半導體晶片之內連接結構以及包括其之半導體封裝 - Google Patents

半導體晶片之內連接結構以及包括其之半導體封裝 Download PDF

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TW202213693A
TW202213693A TW110113586A TW110113586A TW202213693A TW 202213693 A TW202213693 A TW 202213693A TW 110113586 A TW110113586 A TW 110113586A TW 110113586 A TW110113586 A TW 110113586A TW 202213693 A TW202213693 A TW 202213693A
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Taiwan
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pad
pads
semiconductor wafer
width
interconnect
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TW110113586A
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English (en)
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馬金希
張喆容
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南韓商三星電子股份有限公司
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Publication of TW202213693A publication Critical patent/TW202213693A/zh

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Abstract

一種半導體晶片之內連接結構可包括內連接通孔、下部接墊、導電凸塊及上部接墊。內連接通孔可佈置於半導體晶片中。下部接墊可佈置於穿過半導體晶片的下表面暴露出的內連接通孔的下端上。導電凸塊可佈置於下部接墊上。上部接墊可佈置於穿過半導體晶片的上表面暴露出的內連接通孔的上端上。上部接墊可具有較內連接通孔的寬度寬且較下部接墊的寬度窄的寬度。因此，在具有薄的厚度的內連接結構中導電凸塊之間可不產生電短路。

Description

半導體晶片之內連接結構與內連接結構之製造方法以及包括其之半導體封裝與其製造方法
示例性實施例是有關於一種半導體晶片之內連接結構與內連接結構之製造方法以及包括其之半導體封裝與半導體封裝之製造方法。更具體而言，示例性實施例是有關於一種被配置成將堆疊的半導體晶片彼此電性連接的內連接結構與內連接結構之製造方法以及包括其之半導體封裝與半導體封裝之製造方法。
半導體封裝可包括多個堆疊的半導體晶片。半導體晶片可經由內連接結構彼此電性連接。內連接結構可包括導電凸塊、接墊、內連接通孔（例如矽穿孔（through silicon via，TSV））等。
根據相關技術，由於堆疊的半導體晶片的數目可增加，因此導電凸塊之間的節距可被減小且內連接通孔的寬度亦可被減小。因此，可能需要在防止導電凸塊之間的電短路的同時減小內連接結構的厚度。
示例性實施例提供一種可能夠利用內連接結構的薄的厚度防止導電凸塊之間的電短路的半導體晶片的內連接結構。
示例性實施例亦提供一種製造上述的內連接結構的方法。
示例性實施例亦提供一種包括具有上述內連接結構的堆疊的半導體晶片的半導體封裝。
示例性實施例亦提供一種製造上述的半導體封裝的方法。
根據示例性實施例，可提供一種半導體晶片的內連接結構。所述內連接結構可包括內連接通孔、下部接墊、導電凸塊及上部接墊。所述內連接通孔可佈置於所述半導體晶片中。所述下部接墊可佈置於穿過所述半導體晶片的下表面暴露出的所述內連接通孔的下端上。所述導電凸塊可佈置於所述下部接墊上。所述上部接墊可包括主體接墊及內連接接墊。所述主體接墊可佈置於穿過所述半導體晶片的上表面暴露出的所述內連接通孔的上端上。所述內連接接墊可佈置於所述主體接墊上。所述主體接墊可具有與所述下部接墊的寬度實質上相同的寬度。所述內連接接墊可具有較所述內連接通孔的寬度寬且較所述下部接墊的所述寬度窄的寬度。
根據示例性實施例，可提供一種半導體晶片之內連接結構。所述內連接結構可包括內連接通孔、下部接墊、導電凸塊及上部接墊。所述內連接通孔可佈置於所述半導體晶片中。所述下部接墊可佈置於穿過所述半導體晶片的下表面暴露出的所述內連接通孔的下端上。所述導電凸塊可佈置於所述下部接墊上。所述上部接墊可佈置於穿過所述半導體晶片的上表面暴露出的所述內連接通孔的上端上。所述上部接墊可具有較所述內連接通孔的寬度寬且較所述下部接墊的寬度窄的寬度。
根據示例性實施例，可提供一種半導體封裝。所述半導體封裝可包括封裝基底、第一半導體晶片、第一內連接通孔、第一下部接墊、第一導電凸塊、第一上部接墊、第二半導體晶片、絕緣膜、第二內連接通孔、第二下部接墊、第二導電凸塊及第二上部接墊。所述第一半導體晶片可佈置於所述封裝基底的上表面上。所述第一內連接通孔可佈置於所述第一半導體晶片中。所述第一下部接墊可佈置於穿過所述第一半導體晶片的下表面暴露出的所述第一內連接通孔的下端上。所述第一導電凸塊可佈置於所述第一下部接墊上。所述第一導電凸塊可與所述封裝基底電性連接。所述第一上部接墊可包括第一主體接墊及第一內連接接墊。所述第一主體接墊可佈置於穿過所述第一半導體晶片的上表面暴露出的所述第一內連接通孔的上端上。所述第一內連接接墊可佈置於所述第一主體接墊上。所述第二半導體晶片可佈置於所述第一半導體晶片之上。所述絕緣膜可夾置於所述第一半導體晶片與所述第二半導體晶片之間。所述第二內連接通孔可佈置於所述第二半導體晶片中。所述第二下部接墊可佈置於穿過所述第二半導體晶片的下表面暴露出的所述第二內連接通孔的下端上。所述第二導電凸塊可佈置於所述第二下部接墊上。所述第二導電凸塊可與所述第一上部接墊電性連接。所述第二上部接墊可包括第二主體接墊及第二內連接接墊。所述第二主體接墊可佈置於穿過所述第二半導體晶片的上表面暴露出的所述第二內連接通孔的上端上。所述第二內連接接墊可佈置於所述第二主體接墊上。所述第一主體接墊可具有與所述第一下部接墊的寬度實質上相同的寬度。所述第一內連接接墊可具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的所述寬度窄的寬度。所述第二主體接墊可具有與所述第二下部接墊的寬度實質上相同的寬度。所述第二內連接接墊可具有較所述第二內連接通孔的寬度寬且較所述第二下部接墊的所述寬度窄的寬度。
根據示例性實施例，可提供一種半導體封裝。所述半導體封裝可包括封裝基底、第一半導體晶片、第一內連接通孔、第一下部接墊、第一導電凸塊、第一上部接墊、第二半導體晶片、第二內連接通孔、第二下部接墊、第二導電凸塊及第二上部接墊。所述第一半導體晶片可佈置於所述封裝基底的上表面上。所述第一內連接通孔可佈置於所述第一半導體晶片中。所述第一下部接墊可佈置於穿過所述第一半導體晶片的下表面暴露出的所述第一內連接通孔的下端上。所述第一導電凸塊可佈置於所述第一下部接墊上。所述第一導電凸塊可與所述封裝基底電性連接。所述第一上部接墊可佈置於穿過所述第一半導體晶片的上表面暴露出的所述第一內連接通孔的上端上。所述第一上部接墊可具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的寬度窄的寬度。所述第二半導體晶片可佈置於所述第一半導體晶片之上。所述第二內連接通孔可佈置於所述第二半導體晶片中。所述第二下部接墊可佈置於穿過所述第二半導體晶片的下表面暴露出的所述第二內連接通孔的下端上。所述第二導電凸塊可佈置於所述第二下部接墊上。所述第二導電凸塊可與所述第一上部接墊電性連接。所述第二上部接墊可佈置於穿過所述第二半導體晶片的上表面暴露出的所述第二內連接通孔的上端上。所述第一主體接墊可具有與所述第一下部接墊的寬度實質上相同的寬度。所述第一內連接接墊可具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的所述寬度窄的寬度。所述第二上部接墊可具有較所述第二內連接通孔的寬度寬且較所述第二下部接墊的寬度窄的寬度。
根據示例性實施例，可提供一種製造半導體晶片的內連接結構的方法。在所述製造半導體晶片的內連接結構的方法中，可在所述半導體晶片中形成內連接通孔。可在穿過所述半導體晶片的下表面暴露出的所述內連接通孔的下端上形成下部接墊。可在所述下部接墊上形成導電凸塊。可在穿過所述半導體晶片的上表面暴露出的所述內連接通孔的上端上形成上部接墊。所述上部接墊可具有較所述內連接通孔的寬度寬且較所述下部接墊的寬度窄的寬度。
根據示例性實施例，可提供一種製造半導體封裝的方法。在所述製造半導體封裝的方法中，可在封裝基底的上表面上佈置第一半導體晶片，以經由第一導電凸塊將所述第一半導體晶片與所述封裝基底電性連接。所述第一半導體晶片可包括第一內連接結構。所述第一內連接結構可包括第一內連接通孔、第一下部接墊、所述第一導電凸塊及第一上部接墊。可在所述第一半導體晶片中佈置所述第一內連接通孔。可在穿過所述第一半導體晶片的下表面暴露出的所述第一內連接通孔的下端上佈置所述第一下部接墊。可在所述第一下部接墊上佈置所述第一導電凸塊。可在穿過所述第一半導體晶片的上表面暴露出的所述第一內連接通孔的上端上佈置所述第一上部接墊。所述第一上部接墊可具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的寬度窄的寬度。可在所述第一半導體晶片的上表面上佈置第二半導體晶片。所述第二半導體晶片可包括第二內連接結構。所述第二內連接結構可包括第二內連接通孔、第二下部接墊、第二導電凸塊及第二上部接墊。可在所述第二半導體晶片中佈置所述第二內連接通孔。可在穿過所述第二半導體晶片的下表面暴露出的所述第二內連接通孔的下端上佈置所述第二下部接墊。可在所述第二下部接墊上佈置所述第二導電凸塊。可在穿過所述第二半導體晶片的上表面暴露出的所述第二內連接通孔的上端上佈置所述第二上部接墊。所述第二上部接墊可具有較所述第二內連接通孔的寬度寬且較所述第二下部接墊的寬度窄的寬度。可將所述第二導電凸塊熱壓至所述第一上部接墊，以將所述第一半導體晶片與所述第二半導體晶片電性連接。
根據示例性實施例，可提供一種半導體封裝。所述半導體封裝可包括封裝基底、中介層、至少一個第一半導體晶片及至少兩個半導體晶片。所述中介層可佈置於封裝基板的上表面上。所述第一半導體晶片可佈置於所述中介層的上表面上。所述第二半導體晶片可堆疊於所述中介層的所述上表面上。所述第二半導體晶片中的每一者可包括內連接通孔、下部接墊、導電凸塊及上部接墊。所述內連接通孔可佈置於所述第二半導體晶片中。所述下部接墊可佈置於穿過所述第二半導體晶片的下表面暴露出的所述內連接通孔的下端上。所述導電凸塊可佈置於所述下部接墊上。所述上部接墊可佈置於穿過所述第二半導體晶片的上表面暴露出的所述內連接通孔的上端上。所述上部接墊可具有較所述內連接通孔的寬度寬且較所述下部接墊的寬度窄的寬度。
根據示例性實施例，可提供一種半導體封裝。所述半導體封裝可包括封裝基底、邏輯晶片、至少一個第一半導體晶片及至少兩個半導體晶片。所述邏輯晶片可佈置於所述封裝基板的上表面上。所述第一半導體晶片可佈置於所述中介層的上表面上。所述第二半導體晶片可堆疊於所述中介層的所述上表面上。所述第二半導體晶片中的每一者可包括內連接通孔、下部接墊、導電凸塊及上部接墊。所述內連接通孔可佈置於所述第二半導體晶片中。所述下部接墊可佈置於穿過所述第二半導體晶片的下表面暴露出的所述內連接通孔的下端上。所述導電凸塊可佈置於所述下部接墊上。所述上部接墊可佈置於穿過所述第二半導體晶片的上表面暴露出的所述內連接通孔的上端上。所述上部接墊可具有較所述內連接通孔的寬度寬且較所述下部接墊的寬度窄的寬度。
根據示例性實施例，所述上部接墊的所述寬度可較所述內連接通孔的所述寬度寬且較所述下部接墊的所述寬度窄，以改善所述上部接墊與所述導電凸塊之間的電性連接可靠性。因此，在具有薄的厚度的所述內連接結構中所述導電凸塊之間可不產生電短路。
下文中，將參照附圖詳細闡述示例性實施例。在附圖中，相同的數字始終指代相同的元件。
圖1是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
參照圖1，根據示例性實施例的半導體晶片的內連接結構100可包括內連接通孔120、下部接墊130、導電凸塊132及上部接墊140。
半導體晶片110可具有上表面及下表面。在半導體晶片110的上表面上可形成有上部絕緣層114。在半導體晶片110的下表面上可形成有下部絕緣層112。
內連接通孔120可佈置於半導體晶片110中。內連接通孔120可垂直穿透過半導體晶片110。因此，內連接通孔120可包括穿過半導體晶片110的上表面暴露出的上端及穿過半導體晶片110的下表面暴露出的下端。內連接通孔120的上端可藉由穿過上部絕緣層114形成的開口暴露出。內連接通孔120的下端可藉由穿過下部絕緣層112形成的開口暴露出。舉例而言，內連接通孔120的上端可與上部絕緣層114的上表面共面，且內連接通孔120的下端可與下部絕緣層112的下表面共面。內連接通孔120可包括矽穿孔（TSV）。內連接通孔120可包括多個內連接通孔120。
本文中在提及定向、佈局、位置、形狀、大小、量或其他度量時所使用的例如「相同」、「相等」、「平面」或「共面」等用語未必意指完全相同的定向、佈局、位置、形狀、大小、量或其他度量，而是旨在囊括在可能例如由於製造製程而出現的可接受變動內幾乎相同的定向、佈局、位置、形狀、大小、量或其他度量。除非上下文或其他陳述另有指示，否則本文中可使用用語「實質上」來強調此種含義。舉例而言，被闡述為「實質上相同」、「實質上相等」或「實質上平面」的用語可為完全相同、相等或平面的，或者可在可能例如由於製造製程而出現的可接受變動內為相同、相等或平面的。
在示例性實施例中，內連接通孔120可具有約4微米至約5微米的寬度。當內連接通孔120具有圓形橫截面形狀時，內連接通孔120的寬度可為內連接通孔120的直徑。
下部接墊130可佈置於半導體晶片110的下表面上。下部接墊130可位於穿過半導體晶片110的下表面暴而露出的內連接通孔120的下端上。舉例而言，下部接墊130可接觸內連接通孔120的下端。因此，下部接墊130可電性連接至內連接通孔120的下端。下部接墊130可包含鎳，不限制在特定材料內。
下部接墊130可藉由電鍍覆製程在晶種層136上形成。因此，晶種層136可形成在內連接通孔120的下端。晶種層136可包含銅，不限制在特定材料內。下部接墊130可包括多個下部接墊130。
在示例性實施例中，下部接墊130可具有寬度WL及厚度TL。下部接墊130的寬度WL可為約15微米至約20微米。然而，下部接墊130的寬度WL可不限制在上述範圍內。當下部接墊130可具有圓形橫截面形狀時，下部接墊130的寬度WL可為下部接墊130的直徑。下部接墊130的厚度TL可為約10微米至約17微米。然而，下部接墊130的厚度TL可不限制在上述範圍內。如本文所用，厚度可指在垂直於基底的頂表面的方向上測量的厚度或高度。
導電凸塊132可佈置於下部接墊130的下表面上。導電凸塊132的上表面可接觸下部接墊130的下表面。導電凸塊132可包括焊料。在示例性實施例中，導電凸塊132可不藉由迴流製程形成。用於形成導電凸塊132的製程可稍後示出。導電凸塊132可包括多個導電凸塊132。
為了防止導電凸塊132中的焊料滲透至半導體晶片110中，在晶種層136與半導體晶片110的下表面之間、特別是在晶種層136與下部絕緣層112之間可夾置有阻擋層134。阻擋層134可包含鈦，不限制在特定材料內。
上部接墊140可佈置於半導體晶片110的上表面上。上部接墊140可位於穿過半導體晶片110的上表面暴露出的內連接通孔120的上端上。舉例而言，上部接墊140可接觸內連接通孔120的上端。因此，上部接墊140可電性連接至內連接通孔120的上端。因此，上部接墊140與下部接墊130可經由內連接通孔120彼此電性連接。上部接墊140可具有較下部接墊130的厚度TL薄的厚度。上部接墊140可包括多個上部接墊140。上部接墊140可藉由電鍍覆製程在晶種層138上形成。因此，晶種層138可形成在內連接通孔120的上端上。晶種層138可包含銅，不限制在特定材料內。
在示例性實施例中，上部接墊140可包括主體接墊142及內連接接墊144。
主體接墊142可佈置於內連接通孔120的上端上。主體接墊142可具有寬度WUB及厚度TUB。主體接墊142的寬度WUB可為約15微米至約20微米。舉例而言，主體接墊142的寬度WUB可與下部接墊130的寬度WL實質上相同。然而，主體接墊142的寬度WUB可不限制在上述範圍內。舉例而言，主體接墊142的寬度WUB可較下部接墊130的寬度WL寬或窄。當主體接墊142具有圓形橫截面形狀時，主體接墊142的寬度WUB可為主體接墊142的直徑。此外，主體接墊142的厚度TUB可為約2微米至約3微米。然而，主體接墊142的厚度TUB可不限制在上述範圍內。主體接墊142可包含鎳，不限制在特定材料內。
內連接接墊144可佈置於主體接墊142的上表面上。內連接接墊144的下表面可接觸主體接墊142的上表面。具體而言，內連接接墊144可位於主體接墊142的上表面的中心部分上。內連接接墊144可具有寬度WUI及厚度TUI。內連接接墊144的寬度WUI可為約5微米至約8微米。舉例而言，內連接接墊144的寬度WUI可較主體接墊142的寬度WUB窄。如上所述，當主體接墊142的寬度WB與下部接墊130的寬度WL實質上相同時，內連接接墊144的寬度WUI可較下部接墊130的寬度WL窄。相反，內連接接墊144的寬度WUI可較內連接通孔120的寬度寬。然而，內連接接墊144的寬度WUI可不限制在上述範圍內。當內連接接墊144具有圓形橫截面形狀時，內連接接墊144的寬度WUI可為內連接接墊144的直徑。
此外，內連接接墊144的厚度TUI可較主體接墊142的厚度TUB厚。在示例性實施例中，內連接接墊144的厚度TUI可為約4微米至約5微米。然而，內連接接墊144的厚度TUI可不限制在上述範圍內。
在示例性實施例中，內連接接墊144可穿透夾置於堆疊的半導體晶片之間的絕緣膜。內連接接墊144可與上部半導體晶片的導電凸塊電性接觸。由於具有較主體接墊142的寬度WUB窄的寬度WUI的內連接接墊144可自主體接墊142突出，因此內連接接墊144可容易地穿透絕緣膜以與上部半導體晶片的導電凸塊接觸。然而，當內連接接墊144的寬度WUI不大於內連接通孔120的寬度時，內連接接墊144可能不容易與內連接通孔120對準。因此，內連接接墊144的寬度WUI可較主體接墊142的寬度WUB窄且較內連接通孔120的寬度寬。
此外，內連接接墊144可包含相對於導電凸塊132具有潤濕性的材料。舉例而言，內連接接墊144可包含金，不限制在特定材料內。
圖2至圖11是示出製造圖1中的內連接結構的方法的剖視圖。
參照圖2，可穿過半導體晶片110的下表面暴露出內連接通孔120的下端。相反，可不穿過半導體晶片110的上表面暴露出內連接通孔120的上端。
可在半導體晶片110的下表面上依序形成阻擋層134與晶種層136。可在晶種層136的上表面上形成光阻圖案160。光阻圖案160可包括多個開口，所述多個開口被配置成暴露出位於內連接通孔120的上端之上的晶種層136的一部分。
可對晶種層136的藉由光阻圖案160的開口暴露出的部分執行電鍍覆製程，以在晶種層136的下表面上形成下部接墊130。可對下部接墊130執行電鍍覆製程，以在下部接墊130的下表面上形成導電凸塊132。舉例而言，根據示例性實施例的製造內連接結構100的方法可不包括用於形成導電凸塊132的迴流製程。
參照圖3，可部分地移除光阻圖案160及導電凸塊132，以提供具有實質上彼此共面的上表面的光阻圖案160與導電凸塊132。因此，導電凸塊132可具有實質上相同的厚度。可藉由使用研磨機、刀片等的機械製程來移除光阻圖案160及導電凸塊132。
當導電凸塊132具有實質上相同的厚度時，即當導電凸塊132的上表面位於相同的水平平面上時，可省略用於移除光阻圖案160及導電凸塊132的製程。
參照圖4，然後可移除光阻圖案160。光阻圖案160可藉由剝離製程及/或灰化製程移除。可藉由蝕刻製程移除導電凸塊132之間的阻擋層134及晶種層136。
參照圖5，可將載體基底150貼附至半導體晶片110的下表面。因此，半導體晶片110可由載體基底150支撐。
參照圖6，可部分地移除半導體晶片110的上表面，以藉由半導體晶片110的上表面暴露出內連接通孔120的上端。
參照圖7，可在半導體晶片110的上表面上形成上部絕緣層114。上部絕緣層114可包括被配置成暴露出內連接通孔120的上端的開口。
參照圖8，可在上部絕緣層114的上表面上形成晶種層138。可在晶種層138的上表面上形成光阻圖案162。光阻圖案162可包括被配置成暴露出位於內連接通孔120的上端之上的晶種層138的一部分的開口。
參照圖9，可對晶種層138的被暴露出的部分執行電鍍覆製程，以在晶種層138的上表面上形成主體接墊142。主體接墊142的寬度WUB可與下部接墊130的寬度WL實質上相同。然而，主體接墊142的寬度WUB可較下部接墊130的寬度WL寬或窄。在形成主體接墊142之後，然後可移除光阻圖案162。
參照圖10，可在晶種層138及主體接墊142的上表面上形成光阻圖案164。光阻圖案164可包括被配置成暴露出主體接墊142的上表面的中心部分的開口。光阻圖案164的開口可界定內連接接墊144的形狀。
參照圖11，可對主體接墊142的上表面的被暴露出的中心部分執行電鍍覆製程，以在主體接墊142的上表面的中心部分上形成內連接接墊144。如上所述，內連接接墊144的寬度WUI可較主體接墊142的寬度WUB窄且較內連接通孔120的寬度寬。在形成內連接接墊144之後，然後可移除光阻圖案164及晶種層138。
可自半導體晶片110分離載體基底150，以完成圖1中的半導體晶片110的內連接結構100。
圖12是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
除了上部接墊的內連接接墊之外，本示例性實施例的內連接結構100a可包括與圖1中的內連接結構100的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖12，上部接墊140a的內連接接墊144a可佈置於主體接墊142的上表面及側表面上。具體而言，內連接接墊144a可被配置成環繞主體接墊142的上表面及側表面。舉例而言，本示例性實施例的內連接接墊144a可包括自圖1中的內連接接墊144的下表面沿著主體接墊142的上表面及側表面延伸的部分。內連接接墊144a可接觸主體接墊142的上表面及側表面以及上部絕緣層114的上表面。
圖13及圖14是示出製造圖12中的內連接結構的方法的剖視圖。
根據本示例性實施例的製造內連接結構100a的方法可包括與參照圖2至圖9所示的製程實質上相同的製程。
參照圖13，可在晶種層138及主體接墊142的上表面上形成光阻圖案166。光阻圖案166可包括被配置成暴露出主體接墊142的上表面及側表面的開口。
參照圖14，可對主體接墊142的被暴露出的上表面及側表面執行無電鍍覆製程，以在主體接墊142的上表面及側表面上形成內連接接墊144a。在形成內連接接墊144a之後，然後可移除光阻圖案166。
可自半導體晶片110分離載體基底，以完成圖12中的半導體晶片的內連接結構100a。
圖15是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
除了上部接墊之外，本示例性實施例的內連接結構100b可包括與圖1中的內連接結構100的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖15，上部接墊140b可具有傾斜的側表面。舉例而言，當在橫截面觀察時，上部接墊140b可具有等腰梯形形狀。具體而言，上部接墊140b可包括具有下部寬度的下表面、具有上部寬度的上表面以及連接上表面與下表面之間的傾斜的側表面。此外，在上部接墊140b中，傾斜的側表面可具有自下表面至上表面逐漸減小的寬度。因此，下部寬度可較上部寬度寬。舉例而言，上部接墊140b的下表面可具有較上部接墊140b的上表面的面積大的面積。
除了使用負性光阻圖案代替圖8中使用的光阻圖案之外，根據本示例性實施例的製造內連接結構100b的方法可包括與參照圖2至圖9所示的製程實質上相同的製程。因此，本文中為了簡潔起見，可省略製造內連接結構100b的方法。
圖16是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
除了上部接墊之外，本示例性實施例的內連接結構100c可包括與圖1中的內連接結構100的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖16，上部接墊140c可具有均勻的寬度。具體而言，上部接墊140c可包括下表面、上表面及連接下表面與上表面之間的側表面。下表面與上表面可具有實質上相同的寬度。因此，側表面可為垂直形狀。上部接墊140c中的下表面及上表面的寬度可與圖1中的內連接接墊144的寬度實質上相同。因此，本文中為了簡潔起見，可省略關於上部接墊140c中的下表面及上表面的寬度的任何例示。
根據本示例性實施例的製造內連接結構100c的方法可包括與參照圖2至圖9所示的製程實質上相同的製程。因此，本文中為了簡潔起見，可省略製造內連接結構100c的方法。
圖17是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
參照圖17，本示例性實施例的半導體封裝200可包括封裝基底210、多個半導體晶片、絕緣膜220、模製構件230及外部端子240。
半導體晶片可堆疊於封裝基底210的上表面上。在示例性實施例中，半導體晶片可包括第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4。然而，半導體晶片的堆疊數目可不限制在特定數目內。舉例而言，半導體晶片的堆疊數目可為八個、十二個等。
第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者可包括圖1中的內連接結構100。因此，當第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4依序堆疊於封裝基底210的上表面上時，第一半導體晶片110-1的第一導電凸塊132-1可被定向為朝向封裝基底210。第一導電凸塊132-1可與封裝基底210電性連接。舉例而言，第一導電凸塊132-1可接觸封裝基底210。第二半導體晶片110-2的第二導電凸塊132-2可被定向為朝向第一半導體晶片110-1的第一上部接墊140-1。第三半導體晶片110-3的第三導電凸塊132-3可被定向為朝向第二半導體晶片110-2的第二上部接墊140-2。第四半導體晶片110-4的第四導電凸塊132-4可被定向為朝向第三半導體晶片110-3的第三上部接墊140-3。
絕緣膜220可夾置於第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4之間。具體而言，絕緣膜220可夾置於第一半導體晶片110-1與第二半導體晶片110-2之間、第二半導體晶片110-2與第三半導體晶片110-3之間以及第三半導體晶片110-3與第四半導體晶片110-4之間。舉例而言，絕緣膜220可貼附至第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者的下表面。具體而言，絕緣膜220可包括位於較第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的任一者的導電凸塊132的上表面低的平面上的下表面。因此，絕緣膜220可被配置成覆蓋導電凸塊132。絕緣膜220可包括非導電膜（non-conductive film，NCF）。
第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4可藉由熱壓製程彼此結合。舉例而言，可向下按壓第二半導體晶片110-2，以將第二半導體晶片110-2熱壓至第一半導體晶片110-1。第一半導體晶片110-1的第一內連接接墊144-1可穿透絕緣膜220以與第二半導體晶片110-2的第二導電凸塊132-2接觸。如上所述，由於具有較第一主體接墊142-1的寬度窄的寬度的第一內連接接墊144-1可自第一主體接墊142-1突出，因此第一內連接接墊144-1可容易地穿透絕緣膜220以精確地與第二半導體晶片110-2的第二導電凸塊132-2接觸。
具體而言，第一內連接接墊144-1可插入至第二導電凸塊132-2的下表面的中心部分中，以形成被配置成接納第一內連接接墊144-1的接納槽133。因此，圍繞接納槽133的第二導電凸塊132-2的邊緣部分可與第一主體接墊142-1的上表面接觸。
模製構件230可形成在封裝基底210的上表面上，以覆蓋第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4。模製構件230可包括環氧模製化合物（epoxy molding compound，EMC）。
外部端子240可安裝在封裝基底210的下表面上。外部端子240可包括焊球。
圖18至圖21是示出製造圖17中的半導體封裝的方法的剖視圖。
參照圖18，可將絕緣膜220貼附至第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者的下表面。可依序佈置具有絕緣膜220的第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4。
參照圖19，可藉由熱壓製程將第二半導體晶片110-2結合至第一半導體晶片110-1。可藉由熱壓製程將第三半導體晶片110-3結合至第二半導體晶片110-2。可藉由熱壓製程將第四半導體晶片110-4結合至第三半導體晶片110-3。舉例而言，當第二半導體晶片110-2可被向下壓至第一半導體晶片110-1時，第一半導體晶片110-1的第一內連接接墊144-1可穿透絕緣膜220以與第二半導體晶片110-2的第二導電凸塊132-2接觸。具體而言，第一內連接接墊144-1可插入至第二導電凸塊132-2的下表面的中心部分中，以形成被配置成接納第一內連接接墊144-1的接納槽133。因此，圍繞接納槽133的第二導電凸塊132-2的邊緣部分可與第一主體接墊142-1的上表面接觸。
參照圖20，可在封裝基底210的上表面上佈置堆疊的第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4。第一半導體晶片110-1的第一導電凸塊132-1可與封裝基底210電性連接。
參照圖21，可在封裝基底210的上表面上形成模製構件230，以覆蓋第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4。
可在封裝基底210的下表面上安裝外部端子240，以完成半導體封裝200。
圖22是示出包括圖12中的內連接結構的半導體封裝的剖視圖。
除了內連接結構之外，本示例性實施例的半導體封裝200a可包括與圖17中的半導體封裝200的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖22，半導體封裝200a可包括圖12中的內連接結構100a。舉例而言，第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者的內連接接墊144可被配置成環繞主體接墊142的上表面及側表面。
因此，第一內連接接墊144-1可插入至第二導電凸塊132-2的下表面的中心部分中，以形成被配置成接納第一內連接接墊144-1的接納槽133a。因此，圍繞接納槽133a的第二導電凸塊132-2的邊緣部分可與第一主體接墊142-1的上表面接觸。
圖23是示出包括圖15中的內連接結構的半導體封裝的剖視圖。
除了內連接結構之外，本示例性實施例的半導體封裝200b可包括與圖17中的半導體封裝200的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖23，半導體封裝200b可包括圖15中的內連接結構100。舉例而言，第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者的上部接墊140b可具有傾斜的側表面。
因此，傾斜的上部接墊140b可插入至第二導電凸塊132-2的下表面的中心部分中，以形成被配置成接納第一上部接墊140-1的接納槽133b。
圖24是示出包括圖16中的內連接結構的半導體封裝的剖視圖。
除了內連接結構之外，本示例性實施例的半導體封裝200c可包括與圖17中的半導體封裝200的元件實質上相同的元件。因此，本文中為了簡潔起見，相同的參考編號可指代相同的元件且可省略關於相同元件的任何進一步的例示。
參照圖24，半導體封裝200c可包括圖16中的內連接結構100。舉例而言，第一半導體晶片110-1、第二半導體晶片110-2、第三半導體晶片110-3及第四半導體晶片110-4中的每一者的上部接墊140可具有均勻的寬度。
第一上部接墊140-1的均勻寬度可較第二導電凸塊132-2的寬度窄，使得第一上部接墊140-1可插入至第二導電凸塊132-2的下表面的中心部分中，以形成被配置成接納第一上部接墊140-1的接納槽133c。
圖25是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
參照圖25，本示例性實施例的半導體封裝300可包括2.5D堆疊型半導體封裝。因此，半導體封裝300可包括封裝基底310、中介層320、至少一個第一半導體晶片350、多個第二半導體晶片110、模製構件330及外部端子340。
中介層320可佈置於封裝基底310的上表面上。中介層320可經由多個導電凸塊322與封裝基底310電性連接。
第一半導體晶片350可佈置於中介層320的上表面上。第一半導體晶片350可經由導電凸塊352與中介層320電性連接。第一半導體晶片350可包括中央處理器（central processing unit，CPU）、圖形處理單元（graphic processing unit，GPU）等。
第二半導體晶片110可佈置於中介層320的上表面上。第二半導體晶片110可對應於圖17中的半導體晶片110。舉例而言，第二半導體晶片110可經由圖1中的內連接結構100彼此電性連接。作為另外一種選擇，半導體封裝300可包括圖12中的內連接結構100a、圖15中的內連接結構100b或圖16中的內連接結構100c。第二半導體晶片110可包括高帶寬記憶體（high bandwidth memory，HBM）晶片。
模製構件330可形成在封裝基底310的上表面上，以覆蓋第一半導體晶片350及第二半導體晶片110。模製構件330可包括環氧模製化合物（EMC）。
外部端子340可安裝在封裝基底310的下表面上。外部端子340可包括焊球。
圖26是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
參照圖26，本示例性實施例的半導體封裝400可包括3.0D堆疊型半導體封裝。因此，半導體封裝400可包括封裝基底410、邏輯晶片420、至少一個第一半導體晶片450、多個第二半導體晶片110、模製構件430及外部端子440。
邏輯晶片420可佈置於封裝基底410的上表面上。邏輯晶片420可經由多個導電凸塊422與封裝基底410電性連接。
第一半導體晶片450可佈置於邏輯晶片420的上表面上。第一半導體晶片450可經由導電凸塊452與邏輯晶片420電性連接。第一半導體晶片450可包括靜態隨機存取記憶體（Static Random Access Memory，SRAM）晶片。
第二半導體晶片110可佈置於邏輯晶片420的上表面上。第二半導體晶片110可對應於圖17中的半導體晶片110。舉例而言，第二半導體晶片110可經由圖1中的內連接結構100彼此電性連接。作為另外一種選擇，半導體封裝300可包括圖12中的內連接結構100a、圖15中的內連接結構100b或圖16中的內連接結構100c。第二半導體晶片110可包括高帶寬記憶體（HBM）晶片。
模製構件430可形成在封裝基底410的上表面上，以覆蓋第一半導體晶片450及第二半導體晶片110。模製構件430可包括環氧模製化合物（EMC）。
外部端子440可安裝在封裝基底410的下表面上。外部端子440可包括焊球。
根據示例性實施例，上部接墊的寬度可較內連接通孔的寬度寬且較下部接墊的寬度窄，以改善上部接墊與導電凸塊之間的電性連接可靠性。因此，在具有薄的厚度的內連接結構中導電凸塊之間可不產生電短路。
前述內容是對示例性實施例的例示，且不應被視為對示例性實施例進行限制。儘管已闡述了幾個示例性實施例，然而熟習此項技術者將易於理解，可在不實際上背離本發明的新穎教示內容及優點的條件下在示例性實施例中作出諸多潤飾。因此，所有此類潤飾皆旨在包含於如在申請專利範圍中所界定的本發明的範圍內。在申請專利範圍中，方式加功能條款旨在涵蓋本文中所述的用於執行所敍述功能的結構、且不僅涵蓋結構性等效形式而且亦涵蓋等效結構。因此，應理解，前述內容是對各種示例性實施例的例示且不應被視為僅限於所揭露的具體示例性實施例，且對所揭露示例性實施例所作的潤飾以及其他示例性實施例皆旨在包含於隨附申請專利範圍的範圍內。
100、100a、100b、100c:內連接結構 110:半導體晶片/第二半導體晶片 110-1、350、450:第一半導體晶片 110-2:第二半導體晶片 110-3:第三半導體晶片 110-4:第四半導體晶片 112:下部絕緣層 114:上部絕緣層 120:內連接通孔 130:下部接墊 132、322、352、422、452:導電凸塊 132-1:第一導電凸塊 132-2:第二導電凸塊 132-3:第三導電凸塊 132-4:第四導電凸塊 133、133a、133b、133c:接納槽 134:阻擋層 136、138:晶種層 140、140a、140b、140c:上部接墊 140-1:第一上部接墊 140-2:第二上部接墊 140-3:第三上部接墊 142:主體接墊 142-1:第一主體接墊 144、144a:內連接接墊 144-1:第一內連接接墊 150:載體基底 160、162、164、166:光阻圖案 200、200a、200b、200c、300、400:半導體封裝 210、310、410:封裝基底 220:絕緣膜 230、330、430:模製構件 240、340、440:外部端子 320:中介層 420:邏輯晶片 TL、TUB、TUI:厚度 WL、WUB、WUI:寬度
結合附圖閱讀以下詳細說明將更清楚地理解示例性實施例。圖1至圖26表示本文所述的非限制性的示例性實施例。
圖1是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
圖2至圖11是示出製造圖1中的內連接結構的方法的剖視圖。
圖12是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
圖13及圖14是示出製造圖12中的內連接結構的方法的剖視圖。
圖15是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
圖16是示出根據示例性實施例的半導體晶片的內連接結構的剖視圖。
圖17是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
圖18至圖21是示出製造圖17中的半導體封裝的方法的剖視圖。
圖22是示出包括圖12中的內連接結構的半導體封裝的剖視圖。
圖23是示出包括圖15中的內連接結構的半導體封裝的剖視圖。
圖24是示出包括圖16中的內連接結構的半導體封裝的剖視圖。
圖25是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
圖26是示出包括圖1中的內連接結構的半導體封裝的剖視圖。
100:內連接結構
110:半導體晶片/第二半導體晶片
112:下部絕緣層
114:上部絕緣層
120:內連接通孔
130:下部接墊
132:導電凸塊
134:阻擋層
136、138:晶種層
140:上部接墊
142:主體接墊
144:內連接接墊
TL、TUB、TUI:厚度
WL、WUB、WUI:寬度

Claims (20)

  1. 一種半導體晶片之內連接結構，所述內連接結構包括： 內連接通孔，佈置於所述半導體晶片中； 下部接墊，佈置於穿過所述半導體晶片的下表面而暴露出的所述內連接通孔的下端上； 導電凸塊，佈置於所述下部接墊上；以及 上部接墊，包括主體接墊以及佈置於所述主體接墊的上表面上的內連接接墊，所述主體接墊佈置於穿過所述半導體晶片的上表面而暴露出的所述內連接通孔的上端上， 其中所述主體接墊具有與所述下部接墊的寬度實質上相同的寬度，且所述內連接接墊具有較所述內連接通孔的寬度寬且較所述下部接墊的所述寬度窄的寬度。
  2. 如請求項1所述的內連接結構，其中所述內連接接墊被定位於所述主體接墊的所述上表面的中心部分上。
  3. 如請求項1所述的內連接結構，其中所述內連接接墊被佈置於所述主體接墊的上表面及側表面上。
  4. 如請求項1所述的內連接結構，其中所述下部接墊的所述寬度為約15微米至約20微米，所述內連接通孔的所述寬度為約4微米至約5微米，且所述內連接接墊的所述寬度為約5微米至約8微米。
  5. 如請求項1所述的內連接結構，其中所述上部接墊具有較所述下部接墊的厚度薄的厚度。
  6. 如請求項1所述的內連接結構，其中所述內連接接墊具有較所述主體接墊的厚度厚的厚度。
  7. 如請求項6所述的內連接結構，其中所述主體接墊的所述厚度為約2微米至約3微米，且所述內連接接墊的所述厚度為約4微米至約5微米。
  8. 如請求項1所述的內連接結構， 其中所述主體接墊包含鎳，且 其中所述內連接接墊包含金。
  9. 一種半導體封裝，包括： 封裝基底； 第一半導體晶片，佈置於所述封裝基底的上表面上； 第一內連接通孔，佈置於所述第一半導體晶片中； 第一下部接墊，佈置於穿過所述第一半導體晶片的下表面而暴露出的所述第一內連接通孔的下端上； 第一導電凸塊，佈置於所述第一下部接墊上且與所述封裝基底電性連接； 第一上部接墊，包括第一主體接墊以及佈置於所述第一主體接墊的上表面上的第一內連接接墊，所述第一主體接墊佈置於穿過所述第一半導體晶片的上表面而暴露出的所述第一內連接通孔的上端上； 第二半導體晶片，佈置於所述第一半導體晶片之上； 絕緣膜，夾置於所述第一半導體晶片與所述第二半導體晶片之間； 第二內連接通孔，佈置於所述第二半導體晶片中； 第二下部接墊，佈置於穿過所述第二半導體晶片的下表面而暴露出的所述第二內連接通孔的下端上； 第二導電凸塊，佈置於所述第二下部接墊上且與所述第一上部接墊電性連接；以及 第二上部接墊，包括第二主體接墊以及佈置於所述第二主體接墊的上表面上的第二內連接接墊，所述第二主體接墊佈置於穿過所述第二半導體晶片的上表面而暴露出的所述第二內連接通孔的上端上， 其中所述第一主體接墊具有與所述第一下部接墊的寬度實質上相同的寬度，且所述第一內連接接墊具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的所述寬度窄的寬度，且 其中所述第二主體接墊具有與所述第二下部接墊的寬度實質上相同的寬度，且所述第二內連接接墊具有較所述第二內連接通孔的寬度寬且較所述第二下部接墊的所述寬度窄的寬度。
  10. 如請求項9所述的半導體封裝，其中所述第二導電凸塊包括被配置成接納所述第一內連接接墊的接納槽。
  11. 如請求項9所述的半導體封裝， 其中所述第一內連接接墊被定位於所述第一主體接墊的所述上表面的中心部分上，且 其中所述第二內連接接墊位於所述第二主體接墊的所述上表面的中心部分上。
  12. 如請求項9所述的半導體封裝， 其中所述第一內連接接墊被佈置於所述第一主體接墊的上表面及側表面上，且 其中所述第二內連接接墊被佈置於所述第二主體接墊的上表面及側表面上。
  13. 如請求項9所述的半導體封裝， 其中所述第一內連接接墊具有較所述第一主體接墊的厚度厚的厚度，且 其中所述第二內連接接墊具有較所述第二主體接墊的厚度厚的厚度。
  14. 一種半導體封裝，包括： 封裝基底； 第一半導體晶片，佈置於所述封裝基底的上表面上； 第一內連接通孔，佈置於所述第一半導體晶片中； 第一下部接墊，佈置於穿過所述第一半導體晶片的下表面而暴露出的所述第一內連接通孔的下端上； 第一導電凸塊，佈置於所述第一下部接墊上且與所述封裝基底電性連接； 第一上部接墊，佈置於穿過所述第一半導體晶片的上表面而暴露出的所述第一內連接通孔的上端上，所述第一上部接墊具有較所述第一內連接通孔的寬度寬且較所述第一下部接墊的寬度窄的寬度； 第二半導體晶片，佈置於所述第一半導體晶片之上； 絕緣膜，夾置於所述第一半導體晶片與所述第二半導體晶片之間； 第二內連接通孔，佈置於所述第二半導體晶片中； 第二下部接墊，佈置於穿過所述第二半導體晶片的下表面而暴露出的所述第二內連接通孔的下端上； 第二導電凸塊，佈置於所述第二下部接墊上且與所述第一上部接墊電性連接；以及 第二上部接墊，佈置於穿過所述第二半導體晶片的上表面而暴露出的所述第二內連接通孔的上端上，所述第二上部接墊具有較所述第二內連接通孔的寬度寬且較所述第二下部接墊的寬度窄的寬度。
  15. 如請求項14所述的半導體封裝，其中所述第二導電凸塊包括被配置成接納所述第一內連接接墊的接納槽。
  16. 如請求項14所述的半導體封裝， 其中所述第一上部接墊包括： 第一主體接墊，佈置於所述第一內連接通孔的所述上端上；以及 第一內連接接墊，佈置於所述第一主體接墊上以與所述第二導電凸塊電性接觸，所述第一內連接接墊具有較所述第一內連接通孔的所述寬度寬且較所述第一主體接墊的寬度窄的寬度，且 其中所述第二上部接墊包括： 第二主體接墊，佈置於所述第二內連接通孔的所述上端上；以及 第二內連接接墊，佈置於所述第二主體接墊上，所述第二內連接接墊具有較所述第二內連接通孔的所述寬度寬且較所述第二主體接墊的寬度窄的寬度。
  17. 如請求項16所述的半導體封裝， 其中所述第一內連接接墊被定位於所述第一主體接墊的所述上表面的中心部分上，且 其中所述第二內連接接墊被定位於所述第二主體接墊的所述上表面的中心部分上。
  18. 如請求項16所述的半導體封裝， 其中所述第一內連接接墊被佈置於所述第一主體接墊的上表面及側表面上，且 其中所述第二內連接接墊被佈置於所述第二主體接墊的上表面及側表面上。
  19. 如請求項16所述的半導體封裝， 其中所述第一內連接接墊具有較所述第一主體接墊的厚度厚的厚度，且 其中所述第二內連接接墊具有較所述第二主體接墊的厚度厚的厚度。
  20. 如請求項14所述的半導體封裝， 其中所述第一上部接墊包括： 第一下表面，具有下部寬度；以及 第一上表面，具有自所述下部寬度逐漸減小的上部寬度，且 其中所述第二上部接墊包括： 第二下表面，具有下部寬度；以及 第二上表面，具有自所述下部寬度逐漸減小的上部寬度。
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