TW202141738A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202141738A
TW202141738A TW109113152A TW109113152A TW202141738A TW 202141738 A TW202141738 A TW 202141738A TW 109113152 A TW109113152 A TW 109113152A TW 109113152 A TW109113152 A TW 109113152A TW 202141738 A TW202141738 A TW 202141738A
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Taiwan
Prior art keywords
pads
chip
semiconductor package
carrier substrate
redistribution layer
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TW109113152A
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English (en)
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TWI715486B (zh
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羅欽元
張智豪
沈澤旻
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瑞昱半導體股份有限公司
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Priority to TW109113152A priority Critical patent/TWI715486B/zh
Application granted granted Critical
Publication of TWI715486B publication Critical patent/TWI715486B/zh
Priority to US17/192,909 priority patent/US11322474B2/en
Publication of TW202141738A publication Critical patent/TW202141738A/zh

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Abstract

一種半導體封裝，包含第一晶片和第二晶片，並排在載體基板上。第一晶片在鄰近第二晶片的第一側邊上設置有高速訊號接墊，第二晶片包含重佈線層，重佈線層在鄰近第一晶片的第二側邊上設置有數據（DQ）接墊，複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個DQ接墊。第二晶片的重佈線層，相對於第二側邊的第三側邊上，設置有第一指令/位址（CA）接墊以及對應於第一CA接墊的複數個虛設接墊，該複數個虛設接墊經由重佈線層的內連線連接至設置於第二晶片的第四側邊上的第二CA接墊。

Description

半導體封裝
本發明係有關於半導體封裝技術領域，更具體地說，本發明係有關於一種系統級封裝（System-in-Package，SiP）。
隨著便攜式電子設備變得更小，電子設備中的半導體封裝的尺寸也必須減小。為了實現這一點，系統級封裝（SiP）技術被廣泛使用，因為它可以增加半導體封裝的容量。
以電視晶片為例，通常在系統級封裝中至少會有系統單晶片和記憶體晶片，例如，低壓雙倍數據速率LPDDR動態隨機存取記憶體（DRAM）晶片或已知合格晶粒（known-good-die或kgd），而由於DRAM晶片上的接墊排列是固定規格，故通常需要額外形成重佈線層（redistribution layer或RDL）以因應不同電視晶片的效能需求。
然而，過去針對不同的電視晶片的DRAM晶片上需有不同的重佈線層設計的作法，會讓成本增加，且管理上變得複雜。
本發明的主要目的即在提供一種改良的半導體封裝，可以改善上述先前技藝的不足與缺點。
根據本發明實施例，其係公開一種半導體封裝，包含一載體基板，包含相對的一第一表面和一第二表面；一第一晶片和一第二晶片，以並排方式安裝在該載體基板的該第一表面上，其中該第一晶片在鄰近該第二晶片的一第一側邊上設置有複數個高速訊號接墊，該第二晶片包含一重佈線層，該重佈線層在鄰近該第一晶片的一第二側邊上設置有複數個數據（DQ）接墊，在相對於該第二側邊的一第三側邊上設置有複數個第一指令/位址（CA）接墊以及對應於該複數個第一CA接墊的複數個虛設接墊，又其中該複數個虛設接墊經由該重佈線層的內連線連接至設置於鄰接該第三側邊的一第四側邊上的複數個第二CA接墊；以及複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個數據（DQ）接墊。
根據本發明實施例，其中該半導體封裝另包含複數條第二打線，直接電連接該複數個第一CA接墊至該複數個虛設接墊。
根據本發明實施例，其中該半導體封裝另包含複數條第三打線，直接電連接該複數個第二CA接墊至該載體基板的該第一表面上相應的金手指。
根據本發明實施例，其中該第二晶片在該第四側邊上設置有複數個電源或接地（P/G）接墊。
根據本發明實施例，其中另包含複數條第四打線，直接電連接該複數個P/G接墊至該載體基板的該第一表面上相應的金手指。
根據本發明實施例，其中部分該複數條第四打線與部分該複數條第三打線構成GSG或GSSG打線組態。
根據本發明實施例，其中各該複數個第一CA接墊與各該複數個虛設接墊的距離小於200微米。
根據本發明實施例，其中各該複數個第一CA接墊與各該複數個虛設接墊的距離介於100-200微米之間。
根據本發明實施例，其中該第一晶片和該第二晶片係以黏著層固定在該載體基板的該第一表面上。
根據本發明實施例，其中該載體基板的該第二表面上設置有複數個焊球，其中該複數個焊球為球型格柵陣列錫球。
根據本發明實施例，其中該第一晶片包含系統單晶片，該第二晶片包含記憶體晶片。
根據本發明實施例，其中在該載體基板的該第一表面上，另設置有複數個被動元件。
根據本發明實施例，其中該複數個數據（DQ）接墊係形成在該重佈線層上。
根據本發明實施例，其中另包含一模封塑料，包覆該第一晶片和該第二晶片。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
應當理解，儘管這裡可以使用術語“第一”、“第二”等描述各元件、區域、層和/或部分，但是這些元件、區域、層和/或部分不應受限於這些術語。這些術語僅用於將一個元件、區域、層或部分與另一元件、區域、層或部分區別開。因此，以下討論的第一元件、區域、層或部分可以被稱為第二元件、區域、層或部分而不背離示例性實施例的教導。
下文中，用語“系統級封裝”或“SiP”係指複數個具有不同功能的IC晶片或晶粒模封在單一封裝體內。用語“打線接合系統級封裝”或“WBSiP”涉及將複數個晶片封裝在一起，且其中至少一晶片通過打線接合的方式彼此連接。用語“系統單晶片”或“SoC”係指將電腦或其他電子系統的各種元件整合在單一顆晶片中的積體電路。用語“known-good-die”或“kgd”係指已知合格晶粒。
請參閱第1圖及第2圖，其中，第1圖為依據本發明一實施例所繪示的半導體封裝的上視示意圖，第2圖為第1圖中沿著切線I-I’所示的剖面結構示意圖。如第1圖及第2圖所示，半導體封裝1包含一載體基板（carrier substrate）10，具有相對的一第一表面10a和一第二表面10b。根據本發明實施例，半導體封裝1可以是系統級封裝或打線接合系統級封裝。根據本發明實施例，於載體基板10的第一表面10a上至少設置有一第一晶片20和一第二晶片30。例如，第一晶片20和第二晶片30可以分別以黏著層210和310固定在載體基板10的第一表面10a上。
在載體基板10的第二表面10b上設置有複數個焊球150，例如，球型格柵陣列（BGA）錫球。後續可以對焊球150進行回焊，以將半導體封裝1附著至印刷電路板（Printed Circuit Board，PCB）或母板（未示出）上。根據本發明一實施例，載體基板10可以是多層電路板或封裝基板。例如，載體基板10可以是兩層、三層或四層電路板，但不限於此。
舉例而言，載體基板10可以為有機封裝基板，包含金屬導線和樹脂，例如BT（bismalemide triazene）環氧樹脂等。熟習該項技藝者應能理解，可以使用其他材料來形成載體基板10，例如，陶瓷或塑料。為簡化說明，第2圖中載體基板10的內部佈線（routing）僅示意的顯示出部分的金手指102、106和部分連通至錫球焊墊110的導通孔122，其中內部佈線可以將半導體晶粒的訊號電性耦接至第二表面10b上的焊球150。
根據本發明實施例，例如，第一晶片20可以是系統單晶片（SoC），而第二晶片30可以是記憶體晶片，例如動態隨機存取記憶體（DRAM）封裝，具有一個以上的DRAM晶粒（或DRAM kdg）31，例如，雙倍數據速率3（double data rate 3，DDR3）晶粒或雙倍數據速率4（double data rate 4，DDR4）晶粒等。例如，第二晶片30可以包含多個上、下堆疊的DRAM晶粒31，其中DRAM晶粒之間可以設置一絕緣膜（圖未示），例如，以膜包線（Film Over Wire，FOW）技術形成的絕緣層。當然，在其他實施例中，DRAM晶粒也可以採用階梯形式堆疊。為簡化說明，圖中僅例示第二晶片30中的一個DRAM晶粒31。
根據本發明實施例，第一晶片20和第二晶片30係以並排方式安裝在載體基板10的上表面10a上。根據本發明一實施例，例如，第一晶片20和第二晶片30彼此的距離d可以介於約0.5mm至4.0mm之間。在其他實施例中，第一晶片20和第二晶片30彼此的距離d可以超過4.0mm。
根據本發明實施例，在載體基板10的第一表面10a上，可以另設置複數個被動元件140，例如電容（capacitor）、電感（inductor）或電阻（resistor）等。根據本發明一實施例，例如，被動元件140可以是01005尺寸（0.4mm×0.2mm）的去耦電容（decoupling capacitor），但不限於此。此外，第一晶片20和第二晶片30可以被模封塑料（encapsulant）60包覆而與外界隔離。
根據本發明實施例，例如，第一晶片20包含四個側邊E1 ～E4 ，第一晶片20在側邊E1 上設置有複數個高速訊號接墊（high-speed signal pad）201。例如，高速訊號接墊201可以是數據（DQ）接墊，用來傳輸第一晶片20和第二晶片30之間的高速數據訊號，例如，2133MT/s、2400MT/s、2666MT/s或更高的資料傳輸速率，但不限於此。
根據本發明實施例，例如，第二晶片30包含四個側邊E5 ～E8 。根據本發明一實施例，在DRAM晶粒31上可以設置有重佈線層RDL。重佈線層RDL的結構及材料均屬該領域周知技藝，例如，包括至少一絕緣層和至少一導線層，其細節不另贅述。重佈線層RDL將DRAM晶粒31主動面上的接墊位置P0 扇出至重佈線層RDL上的接墊位置P01 ，並且形成接墊301。根據本發明一實施例，在重佈線層RDL上，沿著側邊E5 所佈設的接墊301主要是對應於高速訊號接墊201的數據（DQ）接墊。
根據本發明實施例，例如，重佈線層RDL將DRAM晶粒31主動面上的接墊位置P1 扇出至重佈線層RDL上的接墊位置P11 ，並且形成接墊302。根據本發明一實施例，側邊E5 和側邊E6 是相對的兩邊。根據本發明一實施例，例如，在重佈線層RDL上，沿著側邊E6 形成的接墊302可以是用於傳輸指令/位址（Command/Address，CA）訊號的接墊（以下又稱CA接墊）。此外，在重佈線層RDL上，沿著側邊E7 和E8 處，可以分別形成電源或接地（Power/Ground，P/G）接墊305和306。
根據本發明實施例，例如，在重佈線層RDL上，相對應於CA接墊302另設置有複數個虛設接墊303，其中CA接墊302和虛設接墊303係一對一設置，且CA接墊302和虛設接墊303之間的距離s小於200微米，例如，介於100至200微米之間，但不限於此。如第1圖所示，虛設接墊303分別透過重佈線層RDL的內連線322連接到沿著側邊E8 佈設的複數個CA接墊304。
根據本發明實施例，例如，在沿著第一晶片20的側邊E2 上的載體基板10的第一表面10a上設置有金手指102，而在沿著第二晶片30的側邊E6 、E8 上的載體基板10的第一表面10a上分別設置有金手指106、108。第一晶片20上沿著側邊E2 設置的輸入/輸出（input/output，I/O）接墊202係透過打線WB2 電連接至金手指102。根據本發明一實施例，打線WB2 可以是金線或銅線，但不限於此。
根據本發明實施例，第一晶片20在側邊E1 上設置的複數個高速訊號接墊201係分別透過打線WB15 直接連接至第二晶片30的重佈線層RDL上靠近側邊E5 所設置的DQ接墊301。第一晶片20的高速訊號接墊201與第二晶片30的重佈線層RDL上的DQ接墊301係以打線WB15 直接連接，而不經過載體基板10，因此可以改善訊號失真問題。
根據本發明實施例，第二晶片20上沿著側邊E6 設置的CA接墊302係透過打線WB6 電連接至相對應的金手指106，再經由載體基板10的走線112連接至相對應的金手指102，其訊號傳遞距離約略為L1 。根據本發明一實施例，例如，第二晶片20上沿著側邊E8 設置的P/G接墊305可以透過打線WB8 電連接至相對應的金手指108。
在此實施例中，虛設接墊303和CA接墊302之間不會電性連接，沿著第二晶片20的側邊E8 佈設的複數個CA接墊304也不會電線連接至載體基板10的第一表面10a，故在操作時，沿著第二晶片20的側邊E8 佈設的複數個CA接墊304是電性浮置的。
第3圖是第1圖中第二晶片30的部分重佈線層RDL的上視透視示意圖，其中，相同的元件、區域、材料或層仍沿用相同的符號來表示。如第3圖所示，第二晶片30上沿著側邊E6 設置的CA接墊302係透過打線WB6 電連接至相對應的金手指106。重佈線層RDL另包含至少一接地接墊302g，位於CA接墊302之間，並與CA接墊302並列在同一排上。接地墊302g分別透過重佈線層RDL的內連線322g連接到沿著側邊E8 佈設的複數個接地接墊304g，使得傳遞指令/位址（CA）訊號的內連線322被接地的內連線322g圍繞，構成GSG或GSSG組態（G代表接地，S代表CA訊號），如此可改善訊號的完整性。此外，在各內連線322g上設置接地接墊303g，並以打線WB6g 將接地接墊303g接合至相對應的金手指106g，如此同樣使得傳遞CA訊號的打線WB6 被接地的打線WB6g 圍繞，構成上述GSG或GSSG打線組態。
請參閱第4圖及第5圖，其中，第4圖為依據本發明另一實施例所繪示的半導體封裝的上視示意圖，第5圖為第4圖中沿著切線II-II’所示的剖面結構示意圖，其中相同或類似的元件、區域、層或材料仍沿用相同的符號來表示。如第4圖及第5圖所示，與前一實施例（第1圖及第2圖）的差異在於，半導體封裝1a的第一晶片20a可以是效能較高的SoC晶片。前一實施例（第1圖及第2圖）的第二晶片30上的CA接墊302經由載體基板10的走線112連接至相對應的金手指102，其訊號傳遞距離約略為L1 ，這樣的路徑過長，訊號阻抗過高，並不適合。此時，可將第二晶片30上的CA接墊302以打線WB6d 電連接至虛設接墊303，再將沿著第二晶片30的側邊E8 佈設的複數個CA接墊304以打線WB8 電連接至相對應的金手指108，經由載體基板10的走線114連接至相對應的金手指102，其訊號傳遞距離約略為L2 （L2 >L1 ），這樣的路徑較短，訊號阻抗較低，故適用於效能需求較高的晶片。
第6圖是第4圖中第二晶片30的部分重佈線層RDL的上視透視示意圖，其中，相同的元件、區域、材料或層仍沿用相同的符號來表示。如第6圖所示，第二晶片30上沿著側邊E6 設置的CA接墊302係透過打線WB6d 電連接至相對應的虛設接墊303。同樣的，重佈線層RDL另包含至少一接地接墊302g，位於CA接墊302之間，並與CA接墊302並列在同一排上。接地接墊302g分別透過重佈線層RDL的內連線322g連接到沿著側邊E8 佈設的複數個接地接墊304g，使得傳遞CA訊號的內連線322被接地的內連線322g圍繞，構成GSG或GSSG組態（G代表接地，S代表CA訊號），如此可改善訊號的完整性。此外，在側邊E8 ，CA接墊304和接地接墊304g分別以打線WB8 和WB8g 接合至相對應的金手指108和108g，如此使得傳遞CA訊號的打線WB8 被接地的打線WB8g 圍繞，構成上述GSG或GSSG打線組態。
從以上揭露內容可知，本發明主要係於第二晶片20的重佈線層RDL上對應第二晶片20的側邊E6 的CA接墊302設置虛設接墊303，再透過內連線322、322g於第二晶片20的側邊E8 佈設複數個CA接墊304和接地接墊304g，如此即可彈性的適用於不同效能需求的第一晶片20，兼顧了第二晶片20的重佈線層RDL的共用性和彈性，並使得管理上更為容易。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1、1a:半導體封裝 10:第一表面 10a:第二表面 20、20a:第一晶片 30:第二晶片 31:DRAM晶粒 60:模封塑料 102、106、106g、108、108g:金手指 110:錫球焊墊 112、114:走線 122:導通孔 140:被動元件 150:焊球 201:高速訊號接墊 202:I/O接墊 301:（DQ）接墊 302:（CA）接墊 302g、303g、304g:接地接墊 303:虛設接墊 304:CA接墊 305:P/G接墊 210、310:黏著層 322、322g:內連線 d:距離 E1 ～E8 :側邊 L1 、L2 :訊號傳遞距離 P0 、P1 、P01 、P11 : 接墊位置 RDL:重佈線層 s:距離 WB2 、WB15 、WB6 、WB6d 、WB6g 、WB8 、WB8g :打線
第1圖為依據本發明一實施例所繪示的半導體封裝的上視示意圖。 第2圖為第1圖中沿著切線I-I’所示的剖面結構示意圖。 第3圖是第1圖中第二晶片的部分重佈線層的上視透視示意圖。 第4圖為依據本發明另一實施例所繪示的半導體封裝的上視示意圖。 第5圖為第4圖中沿著切線II-II’所示的剖面結構示意圖。 第6圖是第4圖中第二晶片的部分重佈線層的上視透視示意圖
1a:半導體封裝
10:第一表面
20a:第一晶片
30:第二晶片
102、106、108:金手指
114:走線
140:被動元件
201:高速訊號接墊
202:I/O接墊
301:(DQ)接墊
302:(CA)接墊
303:虛設接墊
304:CA接墊
305:P/G接墊
322:內連線
E1 ~E8 :側邊
L2 :訊號傳遞距離
WB2 、WB15 、WB6d 、WB8 :打線

Claims (10)

  1. 一種半導體封裝，包含： 一載體基板，包含相對的一第一表面和一第二表面； 一第一晶片和一第二晶片，以並排方式安裝在該載體基板的該第一表面上，其中該第一晶片在鄰近該第二晶片的一第一側邊上設置有複數個高速訊號接墊，該第二晶片包含一重佈線層，該重佈線層在鄰近該第一晶片的一第二側邊上設置有複數個數據（DQ）接墊，在相對於該第二側邊的一第三側邊上設置有複數個第一指令/位址（CA）接墊以及對應於該複數個第一CA接墊的複數個虛設接墊，又其中該複數個虛設接墊經由該重佈線層的內連線連接至設置於鄰接該第三側邊的一第四側邊上的複數個第二CA接墊；以及 複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個數據（DQ）接墊。
  2. 如請求項1所述的半導體封裝，其中該半導體封裝另包含複數條第二打線，直接電連接該複數個第一CA接墊至該複數個虛設接墊。
  3. 如請求項2所述的半導體封裝，其中該半導體封裝另包含複數條第三打線，直接電連接該複數個第二CA接墊至該載體基板的該第一表面上相應的金手指。
  4. 如請求項3所述的半導體封裝，其中該第二晶片在該第四側邊上設置有複數個電源或接地（P/G）接墊。
  5. 如請求項4所述的半導體封裝，其中另包含複數條第四打線，直接電連接該複數個P/G接墊至該載體基板的該第一表面上相應的金手指。
  6. 如請求項5所述的半導體封裝，其中部分該複數條第四打線與部分該複數條第三打線構成GSG或GSSG打線組態。
  7. 如請求項1所述的半導體封裝，其中各該複數個第一CA接墊與各該複數個虛設接墊的距離小於200微米。
  8. 如請求項1所述的半導體封裝，其中各該複數個第一CA接墊與各該複數個虛設接墊的距離介於100-200微米之間。
  9. 如請求項1所述的半導體封裝，其中該第一晶片和該第二晶片係以黏著層固定在該載體基板的該第一表面上。
  10. 如請求項1所述的半導體封裝，其中該載體基板的該第二表面上設置有複數個焊球，其中該複數個焊球為球型格柵陣列錫球。
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