TWI732647B - 半導體封裝件 - Google Patents

半導體封裝件 Download PDF

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Publication number
TWI732647B
TWI732647B TW109126586A TW109126586A TWI732647B TW I732647 B TWI732647 B TW I732647B TW 109126586 A TW109126586 A TW 109126586A TW 109126586 A TW109126586 A TW 109126586A TW I732647 B TWI732647 B TW I732647B
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Taiwan
Prior art keywords
substrate
semiconductor wafer
semiconductor package
metal wire
package according
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TW109126586A
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English (en)
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TW202143404A (zh
Inventor
楊吳德
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南亞科技股份有限公司
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Publication of TWI732647B publication Critical patent/TWI732647B/zh
Publication of TW202143404A publication Critical patent/TW202143404A/zh

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Abstract

一種半導體封裝件包括第一半導體晶圓、第一基板、第二半導體晶圓以及第二基板。第一基板設置於第一半導體晶圓上。第一基板包括複數個第一金屬線層彼此垂直地間隔開，且每一個第一金屬線層電性連接至以下其中一者：接地源及不同類型的電源。第二半導體晶圓設置於第一基板上。第二基板設置於第二半導體晶圓上。第二基板包括複數個第二金屬線層彼此垂直地間隔開，且每一個第二金屬線層電性連接至以下其中一者：接地源及不同類型的電源。

Description

半導體封裝件
本揭露內容是有關於一種半導體封裝件。
雙晶片封裝(dual-die packaging)技術被廣泛地應用於將兩個積體電路晶片封裝於單一封裝模組中，使得單一封裝模組能夠提供雙倍的功能或數據存儲容量。如動態隨機存取存儲(dynamic random access memory，DRAM)晶片的記憶晶片通常以此方式封裝，以允許單一封裝模組提供雙倍的功能或數據存儲容量。近年來，各種雙晶片封裝技術已被開發及利用於半導體產業中。
一般而言，DRAM晶片的運作通常需要接地源及多個電源，且金線及重分佈層常被用以在電源/接地源與DRAM晶片之間傳輸電流。然而，當DRAM晶片於操作過程中(例如，高頻率操作過程中)需要瞬間大電流時，在高頻率操作下的金線會形成大的電阻，從而限制瞬間大電流的傳輸。如此一來，在DRAM晶片中將產生瞬間電壓降，並最終導致晶片的誤操作。因此，期望開發出一種具有改善之功能性的半導體裝置以克服上述問題。
本揭露是有關於一種半導體封裝件。
根據本揭露一些實施方式，半導體封裝件可包括第一半導體晶圓、第一基板、第二半導體晶圓以及第二基板。第一基板設置於第一半導體晶圓上。第一基板包括複數個第一金屬線層彼此垂直地間隔開，且每一個第一金屬線層電性連接至以下其中一者：接地源以及不同類型的電源。第二半導體晶圓設置於第一基板上。第二基板設置於第二半導體晶圓上。第二基板包括複數個第二金屬線層彼此垂直地間隔開，且每一個第二金屬線層電性連接至以下其中一者：接地源以及不同類型的電源。
在本揭露一些實施方式中，半導體封裝件更包括複數個導線，將第一半導體晶圓連接至第一金屬線層。
在本揭露一些實施方式中，半導體封裝件更包括複數個導線，將第二半導體晶圓連接至第二金屬線層。
在本揭露一些實施方式中，半導體封裝件更包括複數個導線，分別將多個第一金屬線層連接至以下其中一者：接地源及不同類型的電源。
在本揭露一些實施方式中，半導體封裝件更包括複數個導線，分別將多個第二金屬線層連接至以下其中一者：接地源及不同類型的電源。
在本揭露一些實施方式中，半導體封裝件更包括複數個第一重分佈層，垂直地設置於第一半導體晶圓與第一基板之間。
在本揭露一些實施方式中，半導體封裝件更包括至少一導線，將第一重分佈層的至少一者連接至訊號源。
在本揭露一些實施方式中，半導體封裝件更包括複數個導電墊，水平地相鄰於第一重分佈層，其中導電墊的至少一者接觸第一重分佈層的至少一者。
在本揭露一些實施方式中，半導體封裝件更包括複數個第二重分佈層，垂直地設置於第二半導體晶圓與第二基板之間。
在本揭露一些實施方式中，半導體封裝件更包括至少一導線，將第二重分佈層的至少一者連接至訊號源。
在本揭露一些實施方式中，半導體封裝件更包括複數個導電墊，水平地相鄰於第二重分佈層，其中導電墊的至少一者接觸第二重分佈層的至少一者。
在本揭露一些實施方式中，半導體封裝件更包括複數個導通結構，嵌入至第一基板中，且垂直地連接第一金屬線層的其中兩者。
在本揭露一些實施方式中，半導體封裝件更包括複數個導通結構，嵌入至第二基板中，且垂直地連接第二金屬線層的其中兩者。
在本揭露一些實施方式中，半導體封裝件更包括第一黏膠層，垂直地設置於第一半導體晶圓與第一基板之間。
在本揭露一些實施方式中，半導體封裝件更包括第二黏膠層，垂直地設置於第二半導體晶圓與第二基板之間。
在本揭露一些實施方式中，半導體封裝件更包括第三黏膠層，垂直地設置於第二半導體晶圓與第一基板之間。
在本揭露一些實施方式中，半導體封裝件更包括第三基板，設置於第一半導體晶圓背對第一基板的表面。
在本揭露一些實施方式中，半導體封裝件更包括複數個焊球，安裝於第三基板背對第一半導體晶圓的表面。
在本揭露一些實施方式中，半導體封裝件更包括成型模料，封裝第一半導體晶圓、第一基板、第二半導體晶圓以及第二基板。
在本揭露一些實施方式中，成型模料穿過第一基板及第二基板。
根據本揭露上述實施方式，由於包括第一金屬線層的第一基板設置在第一半導體晶圓上，因此第一半導體晶圓可透過第一基板電性連接至接地源及複數個電源。類似而言，由於包括第二金屬線層的第二基板設置在第二半導體晶圓上，因此第二半導體晶圓可透過第二基板電性連接至接地源及複數個電源。如此一來，可以避免引起半導體封裝件中之瞬間電壓降的大電阻，且當即使需要瞬間大電流時，來自外部電子裝置之電源供給仍可被穩定地提供至半導體封裝件中。藉此，即使在需要瞬間大電流的情形下，半導體封裝件仍可良好地執行其功能。
以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的，因此不應用以限制本揭露。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。另外，為了便於讀者觀看，圖式中各元件的尺寸並非依實際比例繪示。
第1圖繪示根據本揭露一些實施方式之半導體封裝件100的上視示意圖。第2圖繪示根據本揭露一些實施方式之半導體封裝件100沿線段2-2'的剖面示意圖。請參閱第1圖及第2圖，半導體封裝件100包括第一半導體晶圓110、第二半導體晶圓120、第一基板130及第二基板140。第一基板130設置於第一半導體晶圓110上方，第二半導體晶圓120設置於第一基板130上方，且第二基板140設置於第二半導體晶圓120上方。換句話說，第一基板130、第二半導體晶圓120以及第二基板140依序堆疊於第一半導體晶圓110上。
第一基板130包括複數個第一金屬線層132(例如具有橫向延伸之金屬線的層)垂直地堆疊並彼此間隔開(例如藉由第一半導體基板中的介電材料間隔開)，且每個第一金屬線層132透過第一基板130中之一個或多個垂直延伸的導通結構電性連接至以下其中一者：接地源及多個不同類型的電源(如第3至6圖所示)。舉例而言，第一基板130包括第一金屬線層132-1、132-2、132-3及132-4，第一金屬線層132-1電性連接接地源，第一金屬線層132-2電性連接VDD電源，第一金屬線層132-3電性連接VDD2電源，且第一金屬線層132-4電性連接VDDQ電源。然而，第一金屬線層132-1、132-2、132-3及132-4與接地源/電源(亦即接地源以及VDD、VDD2與VDDQ電源)之間的連接關係不限於此，且可根據設計者的需求設置其他連接關係。
第二基板140包括複數個第二金屬線層142垂直地堆疊並彼此間隔開，且每個第二金屬線層142透過第二基板140中之一個或多個垂直延伸的導通結構電性連接至以下其中一者：接地源以及多個不同類型的電源(如第3至6圖所示)。舉例而言，第二基板140包括第二金屬線層142-1、142-2、142-3及142-4，第二金屬線層142-1電性連接至接地源，第二金屬線層142-2電性連接至VDD電源，第二金屬線層142-3電性連接至VDD2電源，第二金屬線層142-4電性連接至VDDQ電源。然而，第二金屬線層142-1、142-2、142-3及142-4與接地源/電源(亦即接地源以及VDD、VDD2與VDDQ電源)之間的連接關係不限於此，且可根據設計者的需求設置其他連接關係。
應瞭解到，為了清楚起見及方便說明，在以下敘述中，第一金屬線層132-1及第二金屬線層142-1被視為電性連接至接地源，第一金屬線層132-2及第二金屬線層142-2被視為電性連接至VDD電源，第一金屬線層132-3及第二金屬線層142-3被視為電性連接至VDD2電源，且第一金屬線層132-4及第二金屬線層142-4被視為電性連接至VDDQ電源。
在一些實施方式中，半導體封裝件100更包括第三基板150，設置在第一半導體晶圓110背對第一基板130的表面111。在一些實施方式中，第一基板130及第二基板140各自於第三基板150的垂直投影面積小於第一半導體晶圓110及第二半導體晶圓120各自於第三基板150的垂直投影面積。在一些實施方式中，第一基板130於第三基板150的垂直投影面積等於第二基板140於第三基板150的垂直投影面積，且第一半導體晶圓110於第三基板150的垂直投影面積等於第二半導體晶圓120於第三基板150的垂直投影面積。
在一些實施方式中，半導體封裝件100更包括複數個第一導電墊160、複數個第二導電墊162及複數個第三導電墊164。第一導電墊160設置於第一半導體晶圓110面對第一基板130的表面113，第二導電墊162設置於第二半導體晶圓120面對第二基板140的表面，且第三導電墊164設置於第三基板150面對第一半導體晶圓110的表面153。第一導電墊160、第二導電墊162以及第三導電墊164配置以用於導線的接合。
在一些實施方式中，半導體封裝件100更包括複數個焊球170，安裝在第三基板150背對第一半導體晶圓110的表面151。換句話說，第三導電墊164與焊球170設置在第三基板150的相對表面。在一些實施方式中，半導體封裝件100更包括在第三基板150中之複數個互連結構180(例如金屬線及金屬導通結構)，使得第一半導體晶圓110及第二半導體晶圓120可進一步電性連接至外部接地源及電源，此將於下文中進行更詳細的說明。
在一些實施方式中，半導體封裝件100更包括複數個第一導線190及複數個第二導線200。第一導線190將第一半導體晶圓110連接至第一基板130，且第二導線200將第一基板130連接至第三基板150，使得第一半導體晶圓110可進一步透過互連結構180及焊球170而電性連接至接地源及電源。在一些實施方式中，半導體封裝件100更包括複數個第三導線210及複數個第四導線220。第三導線210將第二半導體晶圓120連接至第二基板140，且第四導線220將第二基板140連接至第三基板150，使得第二半導體晶圓120可進一步透過互連結構180及焊球170而電性連接至接地源及電源。在以下敘述中，將藉由第2圖至第5圖進一步說明上述電性連接關係。
如第1圖及第2圖所示，至少一個第一導線190將第一半導體晶圓110連接至第一基板130的第一金屬線層132-1，且至少一個第二導線200將第一基板130的第一金屬線層132-1連接至第三基板150，使得第一半導體晶圓110可進一步電性連接至接地源。類似地，至少一個第三導線210將第二半導體晶圓120連接至第二基板140的第二金屬線層142-1，且至少一個第四導線220將第二金屬線層142-1連接至第三基板150，使得第二半導體晶圓120可進一步電性連接至接地源。如此一來，透過第一金屬線層132-1以及第二金屬線層142-1的配置，第一半導體晶圓110及第二半導體晶圓120可電性連接至接地源。
在一些實施方式中，半導體封裝件100更包括第一黏膠層310、第二黏膠層290及第三黏膠層300。第一黏膠層310垂直地(在垂直方向上)設置於第一半導體晶圓110與第一基板130之間，第二黏膠層290垂直地設置於第二半導體晶圓120與第二基板140之間，且第三黏膠層300垂直地設置於第一基板130與第二半導體晶圓120之間。在一些實施方式中，第一黏膠層310於第三基板150的垂直投影完全地重疊於第二黏膠層290於第三基板150的垂直投影。在一些實施方式中，第三黏膠層300於第三基板150的垂直投影面積大於第一黏膠層310於第三基板150的垂直投影面積。
第3圖繪示根據本揭露一些實施方式之半導體封裝件100沿線段3-3'的剖面示意圖。如第1圖及第3圖所示，半導體封裝件100更包括嵌入第一基板130及第二基板140中的複數個導通結構230。至少一個第一導線190透過至少一個導通結構230將第一半導體晶圓110連接至第一基板130的第一金屬線層132-2，且至少一個第二導線200透過至少一個導通結構230將第一基板130的第一金屬線層132-2連接至第三基板150，使得第一半導體晶圓110可進一步電連接至VDD電源。類似而言，至少一個第三導線210透過至少一個導通結構230將第二半導體晶圓120連接至第二基板140的第二金屬線層142-2，且至少一個第四導線220透過至少一個導通結構230將第二基板140的第二金屬線層142-2連接至第三基板150，使得第二半導體晶圓120可進一步電連接至VDD電源。藉此，透過第一金屬線層132-2及第二金屬線層142-2的配置，第一半導體晶圓110及第二半導體晶圓120可電性連接至VDD電源。
第4圖繪示根據本揭露一些實施方式之半導體封裝件100沿線段4-4'的剖面示意圖。如第1圖及第4圖所示，至少一個第一導線190透過至少一個導通結構230將第一半導體晶圓110連接至第一基板130的第一金屬線層132-3，且至少一個第二導線200透過至少一個導通結構230將第一基板130的第一金屬線層132-3連接至第三基板150，使得第一半導體晶圓110可進一步電連接至VDD2電源。類似地，至少一個第三導線210透過至少一個導通結構230將第二半導體晶圓120連接至第二基板140的第二金屬線層142-3，且至少一個第四導線220透過至少一個導通結構230將第二基板140的第二金屬線層142-3連接至第三基板150，使得第二半導體晶圓120可進一步電連接至VDD2電源。藉此，透過第一金屬線層132-3及第二金屬線層142-3的配置，第一半導體晶圓110及第二半導體晶圓120可電性連接至VDD2電源。
第5圖繪示根據本揭露一些實施方式之半導體封裝件100沿線段5-5'的剖面示意圖。如第1圖及第5圖所示，至少一個第一導線190透過至少一個導通結構230將第一半導體晶圓110連接至第一基板130的第一金屬線層132-4，且至少一個第二導線200透過至少一個導通結構230將第一基板130的第一金屬線層132-4連接至第三基板150，使得第一半導體晶圓110可進一步電連接至VDDQ電源。類似地，至少一個第三導線210透過至少一個導通結構230將第二半導體晶圓120連接至第二基板140的第二金屬線層142-4，且至少一個第四導線220透過至少一個導通結構230將第二基板140的第二金屬線層142-4連接至第三基板150，使得第二半導體晶圓120可進一步電連接至VDDQ電源。藉此，透過第一金屬線層132-4及第二金屬線層142-4的配置，第一半導體晶圓110及第二半導體晶圓120可電性連接至VDDQ電源。
應瞭解到，雖未繪示於各圖式中，但第一半導體晶圓110以及第二半導體晶圓120可在單一剖面圖中電連接至不同類型的接地源/電源。舉例而言，在單一剖面圖中，第一半導體晶圓110可電性連接至接地源，而第二半導體晶圓120可電性連接至VDD電源。又舉例而言，在單一剖面圖中，第一半導體晶圓110可電性連接至VDD電源，而第二半導體晶圓120可電性連接至VDDQ電源。
由於第一半導體晶圓110透過第一基板130的第一金屬線層132-1、132-2、132-3及132-4電性連接至接地源及電源，且第二半導體晶圓120透過第二基板140的第二金屬線層142-1、142-2、142-3及142-4電性連接至接地源及電源，因此可避免引起半導體封裝件100中之瞬間電壓降的大電阻，使得來自外部電子裝置之電源供給仍可被穩定地提供至半導體封裝件100中。
第6圖繪示根據本揭露一些實施方式之半導體封裝件100沿線段6-6'的剖面示意圖。如第1圖及第6圖所示，半導體封裝件100更包括複數個第一重分佈層240及複數個第二重分佈層250。第一重分佈層240在第一半導體晶圓110的表面113，並垂直地位於第一半導體晶圓110與第一基板130之間。第二重分佈層250位於第二半導體晶圓120的表面123，並垂直地位於第二半導體晶圓120與第二基板140之間。在一些實施方式中，部分之第一重分佈層240及部分之第二重分佈層250分別由第一基板130及第二基板140裸露。
在一些實施方式中，半導體封裝件100更包括至少一個第五導線260以及至少一個第六導線270。第五導線260可將至少一個第一重分佈層240連接至第三基板150， 使得第一半導體晶圓110得以電性連接至外部訊號源。第六導線270將至少一個第二重分佈層250連接至第三基板150，使得第二半導體晶圓120得以電性連接至訊號源。 如此一來，透過第一重分佈層240、第二重分佈層250、第五導線260及第六導線270的配置，第一半導體晶圓110及第二半導體晶圓120可電性連接至訊號源。
如第1圖至第6圖所示，如前所述，半導體封裝件100包括第一導電墊160、第二導電墊162、第一重分佈層240及第二重分佈層250。在一些實施方式中，第一導電墊160水平地相鄰於第一重分佈層240，且第二導電墊162水平地相鄰於第二重分佈層250。如第1圖至第5圖所示，連接至第一基板130及第二基板140的第一導電墊160及第二導電墊162分別與第一重分佈層240及第二重分佈層250間隔開。如第6圖所示，未連接至第一基板130及第二基板140的第一導電墊160及第二導電墊162分別與第一重分佈層240及第二重分佈層250接觸。
在一些實施方式中，半導體封裝件100更包括成型模料280，配置以封裝第一半導體晶圓110、第一基板130、第二半導體晶圓120以及第二基板140。成型模料280用以使半導體封裝件100中的元件不被過度暴露。在一些實施方式中，成型模料280進一步穿透第一基板130及第二基板140。
根據本揭露上述實施方式，半導體封裝件透過第一及第二基板電性連接至接地源及電源，並透過第一及第二重新分佈層電性連接至訊號源。如此一來，可以避免引起半導體封裝件中之瞬間電壓降的大電阻，且即使當需要瞬間大電流時，來自外部電子裝置之電源供給仍可被穩定地提供至半導體封裝件中。藉此，即使在需要瞬間大電流的情形下，半導體封裝件仍可良好地執行其功能。
雖然本揭露已以實施方式揭露如上，然其並非用以限定本揭露，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100:半導體封裝件 110:第一半導體晶圓 111:表面 113:表面 120:第二半導體晶圓 123:表面 130:第一基板 132,132-1,132-2,132-3,132-4:第一金屬線層 140:第二基板 142,142-1,142-2,142-3,142-4:第二金屬線層 150:第三基板 151:表面 153:表面 160:第一導電墊 162:第二導電墊 164:第三導電墊 170:焊球 180:互連結構 190:第一導線 200:第二導線 210:第三導線 220:第四導線 230:導通結構 240:第一重分佈層 250:第二重分佈層 260:第五導線 270:第六導線 280:成型模料 290:第二黏膠層 300:第三黏膠層 310:第一黏膠層 2-2', 3-3', 4-4', 5-5', 6-6':線段
為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖繪示根據本揭露一些實施方式之半導體封裝件的上視示意圖； 第2圖繪示根據本揭露一些實施方式之半導體封裝件沿線段2-2'的剖面示意圖； 第3圖繪示根據本揭露一些實施方式之半導體封裝件沿線段3-3'的剖面示意圖； 第4圖繪示根據本揭露一些實施方式之半導體封裝件沿線段4-4'的剖面示意圖； 第5圖繪示根據本揭露一些實施方式之半導體封裝件沿線段5-5'的剖面示意圖；以及 第6圖繪示根據本揭露一些實施方式之半導體封裝件沿線段6-6'的剖面示意圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:半導體封裝件
110:第一半導體晶圓
111:表面
113:表面
120:第二半導體晶圓
123:表面
130:第一基板
132,132-1,132-2,132-3,132-4:第一金屬線層
140:第二基板
142,142-1,142-2,142-3,142-4:第二金屬線層
150:第三基板
151:表面
153:表面
160:第一導電墊
162:第二導電墊
164:第三導電墊
170:焊球
180:互連結構
190:第一導線
200:第二導線
210:第三導線
220:第四導線
240:第一重分佈層
250:第二重分佈層
280:成型模料
290:第二黏膠層
300:第三黏膠層
310:第一黏膠層

Claims (19)

  1. 一種半導體封裝件，包括：一第一半導體晶圓；一第一基板，設置於該第一半導體晶圓上並電性連接該第一半導體晶圓，其中該第一基板包括一第一金屬線層與一第三金屬線層彼此垂直地間隔開，且每一該些第一金屬線層電性連接至以下其中一者：一接地源及不同類型之複數個電源；一第二半導體晶圓，設置於該第一基板上；以及一第二基板，設置於該第二半導體晶圓上並電性連接該第二半導體晶圓，其中該第二基板包括一第二金屬線層與一第四金屬線層彼此垂直地間隔開，且每一該些第二金屬線層電性連接至以下其中一者：該接地源及不同類型之該些電源；以及一第一導通結構，嵌入至該第二基板中，連接至該第四金屬線層並被該第二金屬線層包圍。
  2. 如請求項1所述的半導體封裝件，更包括複數個導線，將該第一半導體晶圓連接至該第一金屬線層與該第三金屬線層。
  3. 如請求項1所述的半導體封裝件，更包括複數個導線，將該第二半導體晶圓連接至該第二金屬線層與該第四金屬線層。
  4. 如請求項1所述的半導體封裝件，更包括複數個導線，分別將該第一金屬線層與該第三金屬線層連接至以下其中一者：該接地源及不同類型之該些電源。
  5. 如請求項1所述的半導體封裝件，更包括複數個導線，分別將該第二金屬線層與該第四金屬線層連接至以下其中一者：該接地源及不同類型之該些電源。
  6. 如請求項1所述的半導體封裝件，更包括複數個第一重分佈層，垂直地設置於該第一半導體晶圓與該第一基板之間。
  7. 如請求項6所述的半導體封裝件，更包括至少一導線，將該些第一重分佈層的至少一者連接至一訊號源。
  8. 如請求項6所述的半導體封裝件，更包括複數個導電墊，水平地相鄰於該些第一重分佈層，其中該些導電墊的至少一者接觸該些第一重分佈層的至少一者。
  9. 如請求項1所述的半導體封裝件，更包括複數個第二重分佈層，垂直地設置於該第二半導體晶圓與該第二基板之間。
  10. 如請求項9所述的半導體封裝件，更包括至少一導線，將該些第二重分佈層的至少一者連接至一訊號源。
  11. 如請求項9所述的半導體封裝件，更包括複數個導電墊，水平地相鄰於該些第二重分佈層，其中該些導電墊的至少一者接觸該些第二重分佈層的至少一者。
  12. 如請求項1所述的半導體封裝件，更包括一第二導通結構，嵌入至該第一基板中，且垂直地連接該第三金屬線層。
  13. 如請求項1所述的半導體封裝件，更包括一第一黏膠層，垂直地設置於該第一半導體晶圓與該第一基板之間。
  14. 如請求項1所述的半導體封裝件，更包括一第二黏膠層，垂直地設置於該第二半導體晶圓與該第二基板之間。
  15. 如請求項1所述的半導體封裝件，更包括一第三黏膠層，垂直地設置於該第二半導體晶圓與該第一基板之間。
  16. 如請求項1所述的半導體封裝件，更包括一第三基板，設置於該第一半導體晶圓背對該第一基板的表面。
  17. 如請求項16所述的半導體封裝件，更包括複數個焊球，安裝於該第三基板背對該第一半導體晶圓的表面。
  18. 如請求項1所述的半導體封裝件，更包括一成型模料，封裝該第一半導體晶圓、該第一基板、該第二半導體晶圓以及該第二基板。
  19. 如請求項18所述的半導體封裝件，其中該成型模料穿過該第一基板及該第二基板。
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