TW202127549A - 堆疊式矽封裝之扇出型整合 - Google Patents
堆疊式矽封裝之扇出型整合 Download PDFInfo
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- TW202127549A TW202127549A TW109137264A TW109137264A TW202127549A TW 202127549 A TW202127549 A TW 202127549A TW 109137264 A TW109137264 A TW 109137264A TW 109137264 A TW109137264 A TW 109137264A TW 202127549 A TW202127549 A TW 202127549A
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Abstract
本公開的實施例涉及堆疊式矽封裝元件的扇出整合。提供了一種晶片封裝元件及其製造方法,其利用模制化合物中的多個柱來提高抗分層性。在一個實例中,提供了一種晶片封裝元件,該晶片封裝元件包括第一積體電路(IC)裸片、襯底、再分佈層、模制化合物、以及多個柱。再分佈層提供第一IC裸片的電路系統與襯底的電路系統之間的電連接。模制化合物被設置為與第一IC裸片接觸並且經由再分佈層與襯底隔開。多個柱被佈置在模制化合物中並且與第一IC裸片橫向隔開。多個接線柱沒有電連接到第一IC裸片的電路系統。
Description
本發明的各個實施例總體涉及晶片封裝元件,並且具體涉及一種包括多個柱的晶片封裝元件,該多個柱設置在模制化合物中,這些柱與至少一個積體電路(IC)裸片橫向隔開,這些柱被配置為減少製造晶片封裝元件期間模制化合物分層或開裂的可能性。
諸如平板電腦、電腦、影印機、數碼相機、智慧型電話、控制系統和自動櫃員機等之類的電子設備經常採用利用晶片封裝元件的電子構件來增加功能並且提高構件密度。傳統裸片封裝方案通常利用封裝襯底(通常與矽通孔(TSV)插入襯底結合)來使得多個積體電路(IC)裸片能夠安裝到單個封裝襯底。IC裸片可以包括記憶體、邏輯或其他IC設備。
在許多下一代晶片封裝元件中,諸如再分佈層之類的扇出被用於將IC裸片連接到安裝有IC裸片的襯底。IC裸片通常設置在模制化合物中,以向晶片封裝元件提供改善的結構完整性。然而,模制化合物的裂紋和/或模制化合物與IC裸片分層經常傳播到扇出中,這會導致扇出內的導體(即,電跡線)斷裂或變壞。扇出內的斷裂和/或損壞導體會導致效能下降、使用壽命縮短甚至導致設備發生故障。
因此,需要一種晶片封裝元件,該晶片封裝元件具有對IC裸片與安裝有IC裸片的襯底之間設置的扇出內的導體的損壞和/或斷裂的抗性。
提供了一種晶片封裝元件及其製造方法,其抑制對至少一個積體電路(IC)裸片與諸如插入襯底或封裝襯底之類的底襯底之間設置的扇出(即,再分佈層)內的導體造成的損壞和/或斷裂。在一個實例中,扇出的穩健保護經由在接觸上製造再分佈層之前利用無磨工藝跨越相鄰裸片產生共面觸點來提供。在另一實例中,模制化合物中的多個柱用於抑制模制化合物的分層和/或開裂,從而降低了這些缺陷從模制化合物傳播到再分佈層的可能性,其中這些缺陷可能會損壞再分佈層內的導體和/或使其斷裂。
在一個實例中,提供了一種晶片封裝元件,其包括第一積體電路(IC)裸片、襯底、再分佈層、模制化合物、以及多個柱。再分佈層提供第一IC裸片的電路系統與襯底的電路系統之間的電連接。模制化合物被設置為與第一IC裸片接觸並且經由再分佈層與襯底隔開。多個柱被設置在模制化合物中並且與第一IC裸片橫向隔開。多個柱沒有電連接到第一IC裸片的電路系統。
在另一實例中,提供了一種晶片封裝元件,其包括第一積體電路(IC)裸片、第二積體電路(IC)裸片、襯底、再分佈層、模制化合物、以及多個接線柱。再分佈層具有電路系統,該電路系統經由焊料連接電耦合到襯底的電路系統。模制化合物被設置為與第一IC裸片接觸並且經由再分佈層與襯底隔開。第一多個柱被設置在第一IC裸片與第二IC裸片之間的模制化合物中。第一多個柱經由再分佈層與襯底隔開。
在另一實例中,提供了一種製造晶片封裝元件的方法,該方法包括:將第一積體電路(IC)裸片安裝到載體;將第二IC裸片安裝到載體;使用模制化合物填充在第一IC裸片與第二IC裸片之間形成的間隙,該模制化合物被設置在第一柱周圍,該第一柱設置在間隙中;移除模制化合物的一部分,以暴露第一IC裸片和第二IC裸片的電接觸焊盤;以及在模制化合物以及第一IC裸片和第二IC裸片上形成再分佈層,該再分佈層具有電路系統,該電路系統電連接到第一IC裸片和第二IC裸片的電路。
提供了一種晶片封裝元件及其製造方法,其抑制對設置在至少一個積體電路(IC)裸片與諸如插入襯底或封裝襯底之類的底襯底之間的扇出(可互換地稱為「再分佈層」)內的導體造成的損壞和/或斷裂。在一個實例中,無磨工藝被用於在相鄰IC裸片上產生共面接觸焊盤,而不會研磨從IC裸片和模制化合物延伸的導電柱。由於研磨是模制化合物中裂紋生成和分層的常見原因,所以在一些實例中取消研磨操作會大大增強了模制化合物中此類缺陷的概率,因此,大大降低了此類缺陷導致裂紋傳播到導體可能損壞或斷裂的扇出中的概率。在其他實例中,即使在研磨被用於暴露IC裸片的接觸焊盤的過程中,設置在模制化合物中的環繞至少一個積體電路(IC)裸片的多個柱被用於抑制模制化合物中裂紋生成和分層。
本文中所描述的晶片封裝元件包括至少一個積體電路(IC)裸片,其被設置在模制化合物中並且安裝在襯底上。再分佈層被設置在IC裸片與襯底之間。再分佈層經由焊料連接電性和機械耦合到襯底。再分佈層提供了IC裸片與襯底之間的信號、接地和功率傳輸路徑(即,電路系統)。襯底可以是封裝襯底或插入襯底。當被利用時,柱沒有延伸穿過IC裸片並且位於IC裸片的橫向外側。這些柱顯著改善了模制化合物的機械效能,從而極大地提高了模制化合物在移除模制化合物的一部分以暴露IC裸片的接觸焊盤或導體用於電連接到再分佈層中製造的扇出的電路系統期間與IC裸片的抗開裂性或抗分層(即,剝離)性。由於如上該的模制化合物不太容易出現或不太可能開裂或分層,所以此類缺陷極不可能傳播到再分佈層中,其中可能會損害再分佈層的一個或多個佈線,從而導致晶片封裝元件的效能降低甚至發生故障。
本文中公開了用於防止損壞再分佈層中製造的扇出的電路系統的其他實例和技術,其可替代地不用模制化合物內的柱。這些技術利用在模制化合物中蝕刻凹槽以暴露裸片接觸焊盤。然後,在仍然暴露裸片接觸焊盤的同時,在模制化合物上對介電材料進行圖案化。導電材料沉積到凹槽中,並且與IC裸片的暴露的接觸焊盤連接。導電材料與電介質材料的底部表面共面,使得可以直接製造再分佈層,而沒有研磨或在與再分佈層相鄰設置的聚合物材料中誘致其他機械應力。結果,與再分佈層相鄰設置的聚合物材料中的缺陷極不可能傳播到再分佈層中,其中可能會損害再分佈層的一個或多個佈線,從而導致晶片封裝元件的效能下降甚至發生故障。
因此,增強模制化合物和與再分佈層相鄰的其他聚合物層的抗開裂性和/或抗分層性極大地改善了防止裂紋傳播到扇出中,這會導致扇出內的導體損壞或斷裂。因此,晶片封裝元件的可靠性和效能顯著提高。
現在,轉到圖1,示意性地圖示了晶片封裝元件100的示意性截面圖,該晶片封裝元件100具有與積體電路(IC)裸片106、126相鄰的多個柱110,該多個柱110設置在模制化合物112中。晶片封裝元件100還包括再分佈層(RDL)102、插入襯底104、以及封裝襯底108。再分佈層102設置在IC裸片106與插入襯底104之間,並且還與模制化合物112接觸。
儘管圖1中示出了彼此橫向隔開的兩個IC裸片106、126,但是IC裸片的總數可以從一個到可以適配在晶片封裝元件100內的裸片的盡可能多的數目的範圍內。附加地,儘管圖1圖示了單個IC裸片106,但是IC 裸片 106可以是IC裸片的堆疊的底部裸片。更進一步地,儘管圖1所圖示的IC裸片126被示為IC裸片126的堆疊,但是可替代地,IC裸片126的堆疊可以由單個IC裸片126替換。可以用於晶片封裝元件100的IC裸片106、126的實例包括但不限於諸如現場可程式設計閘陣列(FPGA)之類的可程式設計邏輯裝置、諸如高頻寬記憶體(HBM)之類的記憶體設備、光學設備、處理器或其他IC邏輯結構。IC裸片106中的一個或多個IC裸片106可以可選地包括光學設備,諸如光電偵測器、雷射器、光源等。在圖1的實例中,IC裸片106是邏輯裸片,而IC裸片126是堆疊在緩衝裸片上的多個記憶體裸片。IC裸片126的堆疊可以封裝在聚合物包覆模制化合物128中。
在圖1所描繪的實例中,晶片封裝元件100被配置為高頻寬記憶體(HBM)設備,其中IC裸片106被配置為邏輯裸片,諸如現場可程式設計閘陣列(FPGA),而IC裸片126被配置為HBM裸片堆疊。應當設想,包括晶片封裝元件100的IC裸片106、126的類型可以相同或不同,其包括除HBM裸片和FPGA裸片之外的類型。
每個IC裸片106、126包括底部表面140和頂部表面142。IC裸片106的底部表面140耦合到再分佈層102的頂部表面146。最底部的IC裸片126的底部表面140亦耦合到再分佈層102的頂部表面146。再分佈層102的底部表面144經由焊料連接118或其他合適電連接耦合到插入襯底104的頂部表面138。可選蓋(未示出)可以設置在IC裸片106、126的頂部表面142上。當IC裸片106上存在蓋或其他散熱器時,熱介面材料(TIM)可以設置在IC裸片106、126的頂部表面142與蓋的底部表面之間,以增強了它們之間的熱傳遞。在一個實例中,TIM可以是熱凝膠或熱環氧樹脂,諸如封裝構件附接黏合劑。在一些實現方式中,單獨散熱器可以設置在蓋上方並且與之接觸。
附加地,可選加強件(未示出)可以用於增強晶片封裝元件100的剛度。當使用時,加強件可以由陶瓷、金屬或其他各種無機材料製成,並且耦合到插入襯底104或封裝襯底108中的一個襯底。
如上文所討論的,IC裸片106、126的電路系統被連接到再分佈層102的電路系統。在圖2中,對IC裸片106、126與再分佈層102之間的連接的細節進行進一步詳述。再分佈層102亦與模制化合物112的底部表面114接觸。
參照圖2的局部截面圖,IC裸片106、126包括接觸焊盤202,IC裸片106、126的電路系統160終止於該接觸焊盤202。接觸焊盤202暴露於IC裸片106、126的底部表面140。在IC裸片106、126的底部表面140上直接製造再分佈層102的頂部表面146。再分佈層102包括至少三個金屬層和電介質層,對該至少三個金屬層和電介質層進行圖案化,以產生再分佈層102的電路系統162。在一個實例中,包括電介質層210內由圖案化的金屬線206和通孔208形成的電路系統162的佈線204直接連接在再分佈層 102的頂部表面146上,而無需焊料連接。以此種方式,與利用焊料互連的連接相比,接觸焊盤202之間的間隔可能具有更精細的間距。包括電路系統162的佈線204終止並暴露於再分佈層的底部表面144,以便於與下方襯底的電路系統(例如,插入襯底104的電路系統164)進行焊料連接。
僅回到圖1,再分佈層102的電路系統162經由焊料連接118電性和機械地耦合到插入襯底104的電路系統164。插入襯底104的電路系統164類似地連接到封裝襯底108的電路系統166。在圖1所描繪的實例中,插入襯底104的底部表面136經由焊料連接118或其他合適連接電性和機械耦合到封裝襯底108的頂部表面134。
晶片封裝元件100可以安裝到印刷電路板(PCB)116,以形成電子設備150。以此種方式,封裝襯底108的電路系統166經由焊料球122或其他合適連接耦合到PCB 116的電路系統168。在圖1所描繪的實例中,封裝襯底108的底部表面132經由焊料球122電性和機械耦合到PCB的頂部表面130。
模制化合物112與再分佈層102的頂部表面146接觸。模制化合物112還填充IC裸片106、126之間限定的間隙120。模制化合物112還存在於IC裸片106的與間隙120相對的外側上(即,IC裸片106的與相鄰裸片126相對的一側上)。在僅利用單個裸片的實施例中,模制化合物112被設置在IC裸片106的橫向外側。
模制化合物112向晶片封裝元件100提供了附加剛度,同時還保護了IC裸片106、126與再分佈層102的電路系統之間的電連接。模制化合物112可以是諸如基於環氧樹脂材料之類的聚合物材料或其他合適材料。當IC裸片126被設置在包覆模制化合物128中時,模制化合物112與包覆模制化合物128、再分佈層102和IC裸片106接觸。
柱110被設置在模制化合物112中。柱110用於增加模制化合物112與IC裸片106、126的側面的抗開裂性或抗分層性,特別是當移除模制化合物112的一部分,以暴露IC裸片106的底部表面140,用於將IC裸片106、126的電路系統160電耦合到再分佈層102的電路系統162時。當存在包覆模制化合物128時,柱110亦增加了對模制化合物112從包覆模制化合物128破裂、分離或分層的抗性。
柱110由硬度大於模制化合物112的硬度的材料製成。柱110可以由電介質或金屬材料製成。在一個實例中,柱110由一個或多個金屬層製成。例如,柱110可以由銅、鈦或其他合適金屬材料製成。當柱110由銅製成時,柱110可以包括一個或多個種子層以便於鍍覆,諸如鈦、鎢、鉭和鎳釩等。
柱110通常具有細長幾何形狀,其具有沿長方向的主軸線,該主軸線基本垂直於IC裸片106的底部表面140和插入襯底104的頂部表面138。柱110的橫截面輪廓大致上呈圓形,但是可以具有任何其他合適的幾何形狀。
柱110的底部表面170通常與再分佈層102的頂部表面146共面。柱110的底部表面170通常亦與模制化合物112的底部表面114共面。每個柱110通常從底部表面170延伸到頂部表面172,使得表面170、172之間限定的柱110的長度與IC裸片106的側壁124至少部分重疊。IC裸片106的側壁124通常限定IC裸片106的高度,亦就是說,IC裸片106的頂部表面142和底部表面140之間的距離。
在一個實例中,柱110的頂部表面172與IC裸片106的頂部表面142共面。在另一實例中,柱110的頂部表面172位於IC裸片106的頂部表面142下方。無論頂部表面172的位置如何,柱110的底部表面170皆可以在IC裸片106的底部表面140下方延伸。應當設想,在一些實例中,底部表面170可以延伸到再分佈層102中。
在具有呈堆疊佈置的IC裸片126的另一實例中,柱110的頂部表面172與最上部的IC裸片126的頂部表面142共面。在另一實例中,柱110的頂部表面172位於最上部的IC裸片126的頂部表面142下方。無論頂部表面172的位置如何,柱110的底部表面170皆可以在最底部的IC裸片126的底部表面140的下方延伸。應當設想,在一些實例中,底部表面170可以延伸到再分佈層102中。
在模制化合物112沉積之前或之後,可以形成柱110。例如,在模制化合物112沉積在IC裸片106和柱110周圍之前或之後,柱110可以形成在臨時載體上(如下文所示出的和描述的)。柱110可以例如經由鍍覆或其他合適沉積技術形成在臨時載體上。在另一實例中,模制化合物112可以沉積在IC裸片106、126周圍,然後在模制化合物112中形成孔,該柱110設置在該模制化合物112中。包含柱110的孔可以經由蝕刻、鐳射鑽孔、壓花、熱成型、機械鑽孔或其他合適技術形成。
通常,提供柱110以改善模制化合物112的開裂抗性和分層抗性。如此,柱110沒有被耦合到IC裸片106、126的電路系統160。柱110還可以耦合到再分佈層102的電路系統162。柱110亦可以不耦合到插入襯底104的電路系統164。在圖1所描繪的實例中,柱110相對於IC裸片106、126的電路系統160、162、164中的一個或多個或甚至全部、再分佈層102和插入襯底104電浮動。
柱110可以由增加模制化合物112的剛度的材料製成。合適材料包括與模制化合物112相比具有良好黏合性和更大硬度的材料。合適材料可以是導電材料或不導電材料。合適材料可以比模制化合物112更導熱。合適材料包括金屬,諸如銅、焊料、鈦、鉭和鎳釩等。合適材料還包括保留在黏合劑中的工業金剛石。柱110可以是單個固體,或由諸如粉末、金屬棉或離散形狀之類的保持在黏合劑中的多個元素組成。包括柱110的材料亦可以是焊膏、金屬纖維、金屬粉末、金屬顆粒、金屬球、導熱黏合劑或其他合適導熱材料。
在一個實例中,柱110是導熱的並且垂直遠離插入襯底104的頂部表面138在IC裸片106、126之間提供穩健導電傳熱路徑。若在裸片106、126上方利用蓋(未示出),則可以在柱110與蓋之間利用熱介面材料(TIM),以在柱110與蓋之間提供穩健傳熱介面,以從IC裸片106、126之間引出熱量。
柱110可以具有任何合適截面輪廓,並且通常具有至少與IC裸片106的高度相同的長度。在一個實例中,柱110的截面輪廓是圓形的。可以選擇柱110的數目、尺寸、密度和位置,以在模制化合物112與IC裸片106、126和包覆模制化合物128(若存在)中的至少一個之間提供期望的剪切抗性。
圖3是圖1的晶片封裝元件100的示意性俯視圖,以顯示設定在IC裸片106、126之間的柱110的示例性幾何佈置。在圖3所描繪的實例中,柱110包括設置在相鄰IC裸片106、126之間的柱302。可選地,柱110可以包括設置在IC裸片106、126外側並且設置在IC裸片106、126與插入襯底104的邊緣308之間的柱304。換言之,柱304設置在IC裸片106、126外側(若存在,則設置在包覆模制化合物128外側),並且由模制化合物112包圍。可以選擇柱302的位置、大小和密度以增強期望位置中模制化合物112的剪切抗性、開裂抗性或分層抗性。可以選擇柱304(若存在)的位置、大小和密度,以增強經由期望位置中的模制化合物112的垂直傳熱。在下文所進一步描述的附圖中提供的實例性非限制性實例中,提供了柱110的附加細節。
圖4是相鄰IC裸片之間具有電浮柱110的諸如上文參考圖1至圖2所描述的晶片封裝元件100等之類的晶片封裝元件的製造方法400的流程圖。圖5A至圖5F是處於圖4的方法400的不同階段的晶片封裝元件的示意性截面圖。應當指出,與圖1相比較,圖5A至圖5F所圖示的IC裸片106、126和其他構件的方位相差180°。換句話說,與圖1所示的方位相比較,圖5A至圖5F所圖示的IC裸片106、126和其他構件的方位被顛倒了。
如圖5A所示,方法400開始於操作402,在該操作402處,將IC裸片106、126附接到載體500。載體500僅在初始製造操作期間使用,如此在將IC裸片106、126安裝到諸如插入襯底104之類的襯底並且完成製造晶片封裝元件100之前,載體500被可移動地附接以附接IC裸片106、126。在一個實例中,IC裸片106、126的頂部表面142使用可釋放的壓敏黏合劑被附接到載體500。一個IC裸片或多個IC裸片126可以封裝在包覆模制化合物128中,諸如上文參考圖1所描述和示出的包覆模制化合物。
在操作404處,模制化合物112被設置在IC裸片106、126周圍並且與載體500接觸。模制化合物112延伸超出IC裸片106、126的底部表面140直到初始表面540,如圖5B所圖示的。初始高度542被定義為IC裸片106、126的初始表面540和底部表面140之間限定的距離。模制化合物112可以經由另一合適方法旋塗、分配、包覆模壓或沉積。在操作404處,模制化合物112填充相鄰管IC芯106、126之間限定的間隙120。
在操作406處,在IC裸片106、126之間的模制化合物112中形成孔502,如圖5C所示。孔502可以例如經由蝕刻、鐳射鑽孔、壓花、熱成型、機械鑽孔或其他合適技術形成。孔502的深度可能小於初始高度542,該深度延伸到IC裸片106的底部表面140和頂部表面142之間限定的距離,或延伸到載體500(使得孔502的末端基本上與IC裸片106、126的頂部表面142共面,使得載體500經由孔502暴露)。
在操作408處,孔502隨後填充有加強材料以形成柱110,如圖5D所示。孔502可以經由將材料分配到孔502中或在孔502中電鍍材料以形成柱110來形成。在一個實例中,種子層504沉積在孔502中。例如,種子層504可以被沉積在形成孔502的底部的模制化合物112上,或當經由孔502暴露時,可以被沉積在載體500上。種子層504可以使用化學氣相沉積、物理氣相沉積、噴墨印刷或其他合適技術來沉積。種子層504為隨後沉積在孔502中的金屬材料提供黏附層以繼續形成柱110。種子層504可以可選地被沉積在孔502的側壁上。在圖5D所示的實例中,種子層504由銅製成。在沉積種子層504之後,體導體506被沉積在種子層504上,如圖5D所示。體導體506可以使用無電鍍、電鍍、化學氣相沉積、物理氣相沉積或其他合適技術而被沉積在種子層504上。體導體506完全或接近模制化合物112的初始表面540填充孔502。在圖5D所示的實例中,體導體506是銅,其直接鍍在種子層504上。當孔502較淺時,有利地,需要較少材料來填充孔502並且形成柱110,這節省了成本。當孔502較深時,填充孔502並且形成柱110的導電材料促進熱量從晶片封裝元件100中傳遞出去,這有利地提高了效能可靠性。
在操作410處,對模制化合物112的初始表面540和柱110的末端進行研磨,機械或以其他方式移除,以使模制化合物112的底部表面114、裸片接觸焊盤202和柱110的底部表面170共面,如圖5E所示。柱110抑制模制化合物112萌生裂紋、與IC裸片106、126的側壁124(當存在時,和/或包覆模制化合物128)開裂、分層或以其他方式分離。由於IC裸片106、126的側壁124萌生裂紋、與IC裸片106、126的側壁124開裂、分層或以其他方式分離的可能性較小,所以此類缺陷極不可能傳播到再分佈層102中,其中可能會損害佈線204中的一個或多個佈線204,從而導致晶片封裝元件100的效能降低甚至發生故障。
在操作412處,在不使用焊料連接的情況下,直接在模制化合物112的底部表面114上製造再分佈層102,如圖5F所示。再分佈層102經由沉積形成金屬佈線204的至少三個或更多個介電層來製造。金屬佈線204可以呈互連金屬線206和通孔208的形式,其形成再分佈層102的電路系統162。
在操作414處,移除載體500,並且再分佈層102利用焊料連接118電性和機械連接到插入襯底104,如圖1所示。在操作414處,封裝襯底108利用焊料連接器118電性和機械連接到插入襯底104,以完成晶片封裝元件100的製造。製造晶片封裝元件100除了利用上文所描述的柱110之外還可以包括其他步驟和構件。
圖6是製造晶片封裝元件的方法600的流程圖,其中IC裸片106、126設置在模制化合物112中,除了利用方法600製造的晶片封裝元件可選地無需在相鄰IC裸片106、126之間設置電浮柱110之外,該晶片封裝元件與上文參考圖1至圖2所描述的晶片封裝元件100類似。圖7A至圖7G是處於圖6的方法600的不同階段的晶片封裝元件的示意性截面圖。應當指出,圖7A至圖7G所圖示的IC裸片106、126和其他構件的方位與圖1相比相差180度。換句話說,與圖1所示的方位相比較,圖7A至圖7G所圖示的IC裸片106、126和其他構件的方位被顛倒了。
方法600開始於操作602,在該操作602處,將IC裸片106、126附接到載體700,如圖7A所示。載體700僅在初始製造操作期間使用,如此在將IC裸片106、126安裝到諸如插入襯底104之類的襯底並且完成晶片封裝元件100製造之前,載體700被可移除地附接以附接IC裸片106、126。在一個實例中,IC裸片106、126的頂部表面142使用可釋放的壓敏黏合劑被附接到載體700。一個IC裸片或多個IC裸片106、126可以封裝在包覆模制化合物128中,諸如上文參考圖1所描述和示出的包覆模制化合物。
在操作604處,模制化合物112被設置在IC裸片106、126周圍並且與載體700接觸。模制化合物112延伸超出IC裸片106、126的底部表面140直到初始表面740,如圖7B所圖示的。初始高度742被定義為IC裸片106、126的初始表面740和底部表面140之間限定的距離。模制化合物112可以經由另一合適方法旋塗、分配、包覆模壓或沉積。在操作604處,模制化合物112填充相鄰IC裸片106、126之間限定的間隙120。如圖7B所示,接觸焊盤202的遠端702與模制化合物112的初始表面740之間的間隔可以跨越IC裸片106、126中的單個IC裸片發生變化和/或可以跨越IC裸片106、126發生變化。模制化合物112的厚度通常大於或等於接觸焊盤202中的最長接觸焊盤202延伸超出IC裸片106、126的底部表面140的距離。
在操作606處,相對於柱110選擇性地蝕刻模制化合物112的初始表面740,以在模制化合物112中限定二次表面704,如圖7C所示。選擇性蝕刻允許接觸焊盤202的遠端702延伸超出模制化合物112的二次表面704。
在操作608處,在模制化合物112的二次表面704上沉積聚合物層706並且在該模制化合物112的二次表面704上對其進行圖案化,如圖7D所示。對聚合物層706進行圖案化,使得形成凹槽708以暴露接觸焊盤202的遠端702。在一個實例中,凹槽708形成在接觸焊盤202的每個遠端702周圍。聚合物層706的厚度足以使接觸焊盤202的每個遠端702凹入凹槽708內。換句話說,在對聚合物層706進行圖案化之後,遠端702位於模制化合物112的二次表面704下方。在一個實例中,聚合物層706由聚醯亞胺或其他合適介電材料形成。在圖案化之後,聚合物層706的暴露表面成為模制化合物112的底部表面114。
在操作610處,凹槽708填充有導電材料710,並且使得其與模制化合物112的初始表面740共面,如圖7E所示。填充凹槽708的導電材料710使IC裸片106、126的電路系統160延伸,以與模制化合物112的底部表面114共面,使得可以直接在導電材料710上形成再分佈層102的電路系統162(即,沒有焊料連接)。由於模制化合物112未經歷對模制化合物112誘致剪切力的研磨或其他機械過程,所以模制化合物112基本上不受IC裸片106、126的側壁124(若存在,和/或包覆模制化合物128)萌生裂紋、與該IC裸片106、126的側壁124開裂、分層或分離的影響。由於IC裸片106、126的側壁124萌生裂紋、與IC裸片106、126的側壁124開裂、分層或其他分離的可能性較小,所以此類缺陷極不可能傳播到再分佈層102中,其中可能會損害佈線204中的一個或多個佈線204,從而導致晶片封裝元件100的效能降低甚至發生故障。
在操作612處,在不使用焊料連接的情況下,直接在模制化合物112的底部表面114上製造再分佈層102,如圖7F所示。再分佈層102經由沉積形成金屬佈線204的至少三個或更多個介電層來製造。金屬佈線204可以呈形成再分佈層102的電路系統162的互連金屬線206和通孔208的形式。經由在沒有使用焊接連接的情況下,直接在模制化合物112的底部表面114上製造再分佈層102,可以實現用於與IC裸片106、126的電介面的更高的間距密度。
在操作614處,移除載體700,並且再分佈層102利用焊料連接118電性和機械連接到插入襯底104,如圖7G所示。在操作614處,封裝襯底108還利用焊料連接118電性和機械連接到插入襯底104,以完成晶片封裝元件700的製造。晶片封裝元件700與晶片封裝元件100基本相同,除了缺少柱110以及接觸焊盤202和導電材料710如何在IC裸片106、126的電路系統160與再分佈層102的電路系統162之間進行連接的配置之外。晶片封裝元件的製造700可以包括其他步驟和構件。
圖8是製造晶片封裝元件的方法800的流程圖,其中IC裸片106、126設置在模制化合物112中,除了利用方法600製造的晶片封裝元件可選地無需在相鄰IC裸片106、126之間設置電浮柱110之外,該晶片封裝元件與上文參考圖1至圖2所描述的晶片封裝元件100類似。圖9A至圖9I是處於圖8的方法800的不同階段的晶片封裝元件的示意性截面圖。應當指出,圖9A至圖9I所圖示的IC裸片106、126和其他構件的方位與圖1相比相差180度。換句話說,與圖1所圖示的方位相比較,圖9A至圖9I所圖示的IC裸片106、126和其他構件的方位被顛倒了。
方法800開始於操作802,在該操作802處,將IC裸片106、126附接到載體900,如圖9A所示。載體900僅在初始製造操作期間使用,如此在將IC裸片106、126安裝到諸如插入襯底104之類的襯底並且完成晶片封裝元件100製造之前,載體900被可移動地附接以附接IC裸片106、126。在一個實例中,IC裸片106、126的頂部表面142使用可釋放的壓敏黏合劑被附接到載體900。一個IC裸片或多個IC裸片106、126可以封裝在包覆模制化合物128中,諸如上文參考圖1所描述和示出的包覆模制化合物。
在操作804處,模制化合物112被設置在裸片106、126周圍並且與載體900接觸。模制化合物112延伸超出IC裸片106、126的底部表面140直到初始表面940,如圖9B所示。初始高度942被定義為IC裸片106、126的初始表面940和底部表面140之間限定的距離。模制化合物112可以經由另一合適方法旋塗、分配、包覆模壓或沉積。在操作804處,模制化合物112填充相鄰IC裸片106、126之間限定的間隙120。如圖9B所示,接觸焊盤202的遠端702與模制化合物112的初始表面940之間的間隔可以跨越IC裸片106、126中的單個IC裸片發生變化和/或跨越IC裸片106、126發生變化。模制化合物112的厚度通常大於或等於接觸焊盤202中的最長接觸焊盤202延伸超出IC裸片106、126的底部表面140的距離。
在操作806處,相對於柱110選擇性地蝕刻模制化合物112的初始表面940,以在模制化合物112中限定二次表面904,如圖9C所示。選擇性蝕刻允許接觸焊盤202的遠端702延伸超出模制化合物112的二次表面904。
在操作808處,抗蝕劑層906被沉積在模制化合物112的二次表面904上,如圖9D所示。沉積抗蝕劑層906至覆蓋其全部而非大部分接觸焊盤202的厚度。
在操作810處,移除抗蝕劑層906的頂部部分以使抗蝕劑層906的暴露表面908與接觸焊盤202的遠端702共面,如圖9E所示。可以經由化學機械拋光、飛切(fly-cut)或其他合適工藝來移除抗蝕劑層906的頂部部分。操作808還移除了一些或全部接觸焊盤202的一部分,使得接觸焊盤202的遠端702變得彼此共面,並且與抗蝕劑層906的暴露表面908共面。由於保護模制化合物112不受在移除抗蝕劑層906的頂部部分和接觸焊盤202的一部分的同時引起的應力的影響,所以基本上防止了模制化合物112的裂紋萌生、開裂和分層。
在操作812處,移除剩餘抗蝕劑層906,如圖9F所示。可以經由抗蝕劑剝除工藝(例如,化學抗蝕劑移除或其他合適工藝)來移除抗蝕劑層906。
在操作814處,在模制化合物112上沉積聚合物層706並且在該模制化合物112上對其進行圖案化,如圖9G所示。對聚合物層706進行圖案化,使得在接觸焊盤202的每個遠端702周圍形成凹槽708。聚合物層706的厚度足以使接觸焊盤202的每個遠端702凹入凹槽708內。換句話說,在對聚合物層706進行圖案化之後,遠端702位於聚合物層706的頂部表面下方。在一個實例中,聚合物層706由聚醯亞胺或其他合適介電材料形成。在圖案化之後,聚合物層706的暴露表面成為模制化合物112的底部表面114。
在操作816處,凹槽708填充有導電材料710,並且使得其與模制化合物112(例如,聚合物層706)的底部表面114共面,如圖9H所示。填充凹槽708的導電材料710使IC裸片106、126的電路系統160延伸,以與模制化合物112的底部表面114共面,使得可以直接在導電材料710上形成再分佈層102的電路系統162(即,沒有焊料連接)。由於模制化合物112受到抗蝕劑層906的保護,所以由於模制化合物112未經歷對模制化合物112誘致剪切力的研磨或其他機械過程,因此模制化合物112基本上不受IC裸片106、126的側壁124(若存在,和/或包覆模制化合物128)萌生裂紋、與IC裸片106、126的側壁124開裂,分層或其他分離的影響。由於IC裸片106、126的側壁124萌生裂紋、與IC裸片106、126的側壁124開裂、分層或其他分離的可能性較小,所以此類缺陷極不可能傳播到再分佈層102中,其中可能會損害佈線204中的一個或多個佈線204,從而導致晶片封裝元件100的效能降低甚至發生故障。
在操作818處,直接在模制化合物112的底部表面114上製造再分佈層102,而無需使用焊料連接,如圖9I所示。再分佈層102經由沉積形成金屬佈線204的至少三個或更多個介電層來製造。金屬佈線204可以呈形成再分佈層102的電路系統162的互連金屬線206和通孔208的形式。經由在沒有使用焊接連接的情況下,直接在模制化合物112的底部表面114上製造再分佈層102,可以實現用於與IC裸片106、126的電介面的更高的間距密度。
在操作820處,移除載體900並且再分佈層102利用焊料連接118電性和機械連接到插入襯底104,如圖7G所示。在操作820處,封裝襯底108還利用焊料連接118電性和機械連接到插入襯底104,以完成晶片封裝元件700的製造。如上文所陳述的,晶片封裝元件700與晶片封裝元件100基本相同,除了缺少柱110以及接觸焊盤202和導電材料710如何在IC裸片106、126的電路系統160與再分佈層102的電路系統162之間進行連接的配置之外。晶片封裝元件700的製造可以包括其他步驟和構件。
因此,已經提供了一種晶片封裝元件及其製造方法,其利用設置在積體電路(IC)裸片周圍的多個柱和增強模制化合物和與再分佈層相鄰的其他聚合物層的開裂抗性和/或分層抗性的無磨工藝。增強開裂抗性和/或分層抗性極大地改善了防止裂紋傳播到再分佈層的扇出中,這會導致再分佈層電路系統內的導體損壞或斷裂。因此,晶片封裝元件的可靠性和效能顯著提高。
除了以下發明申請專利範圍之外,可以在以下非限制性實例中描述所公開的技術。實例1以有利地降低模制化合物中裂紋萌生的可能性的方式利用模制化合物的研磨,以利用與研磨過程相關聯的節省成本的優點。實例2至3利用有利地消除了對模制化合物進行研磨以減少模制化合物中裂紋萌生的概率的技術。
實例1:一種製造晶片封裝元件的方法,包括:將IC裸片附接到載體;將模制化合物設置在IC裸片周圍;在IC裸片之間的模制化合物中形成孔;使用加強材料填充孔,以形成柱;移除模制化合物的一部分和柱的末端,以使模制化合物的底部表面、裸片接觸焊盤和柱的底部表面共面;在不使用焊料連接的情況下,直接在模制化合物的底部表面上製造再分佈層;以及移除載體,利用焊料連接將再分佈層電性和機械連接到插入襯底,並且利用焊料連接將封裝襯底電性和機械連接到插入襯底。
實例2:一種製造晶片封裝元件的方法,包括:將IC裸片附接到載體;將模制化合物佈置在裸片周圍並且與載體接觸;相對於從IC裸片延伸的接觸焊盤(即,柱)選擇性地蝕刻模制化合物的初始表面;在模制化合物上沉積聚合物層並且對其進行圖案化,以形成暴露接觸焊盤的凹槽;使用導電材料填充該凹槽並且使導電材料與模制化合物共面;在不使用焊料連接的情況下,直接在模制化合物上製造再分佈層;移除載體,並且利用焊料連接將再分佈層電連接到插入襯底,並且利用焊料連接將封裝襯底電性和機械連接到插入襯底。
實例3:一種製造晶片封裝元件的方法,包括:將IC裸片附接到載體;將模制化合物佈置在裸片周圍並且與載體接觸;相對於從IC裸片延伸的接觸焊盤(即,柱)選擇性地蝕刻模制化合物的初始表面;在模制化合物上沉積抗蝕劑層;移除抗蝕劑層的頂部部分,以使抗蝕劑層的暴露表面與接觸焊盤的遠端共面;移除剩餘抗蝕劑層;在模制化合物上沉積聚合物層並且對其進行圖案化,以形成凹槽,使用導電材料填充凹槽並且使導電材料與模制化合物共面;在不使用焊料連接的情況下,直接在模制化合物上製造再分佈層;移除載體,利用焊料連接將再分佈層電性和機械連接到插入襯底,然後利用焊料連接將封裝襯底電性和機械地連接到插入襯底。
實例4:一種晶片封裝元件,包括第一積體電路(IC)裸片;襯底;再分佈層,其具有電路系統,該電路系統在第一IC裸片的電路系統與襯底的電路系統之間提供電連接;模制化合物,其被設置為與第一IC裸片接觸並且經由再分佈層與襯底隔開;多個接觸焊盤,其從第一裸片延伸並且其末端暴露在模制化合物中形成的凹槽中;以及導電材料,其設置在凹槽中並且將襯底的電路系統電耦合到再分佈層的電路系統。
實例5:一種晶片封裝元件,包括第一積體電路(IC)裸片;襯底;再分佈層,其具有電路系統,該電路系統在第一IC裸片的電路系統與襯底的電路系統之間提供電連接;模制化合物,其被設置為與第一IC裸片接觸並且經由再分佈層與襯底隔開;介電層,其設置在模制化合物與再分佈層之間;多個接觸焊盤,其從第一裸片延伸並且其末端暴露在介電層中形成的凹槽中;以及導電材料,其設置在凹槽中並且將襯底的電路系統電耦合到再分佈層的電路系統。
有利地,至少實例2和3的方法亦可以用於增加支柱(即,接觸焊盤)的高度和重塑,從而增加IC裸片的底部表面與再分佈層的頂部表面之間的模制化合物緩衝。該方法還可以用於增加支柱尺寸,以適應從無法或不會提供統一支柱尺寸的協力廠商供應商獲得IC裸片。
雖然前述內容針對本發明的實施例,但是在不背離本發明的基本範圍的情況下,可以設計本發明的其他進一步實施例,並且本發明的範圍由所附發明申請專利範圍確定。
100:晶片封裝元件
102:再分佈層
104:插入襯底
106:IC裸片
108:封裝襯底
110:柱
112:模制化合物
114:底部表面
116:印刷電路板(PCB)
118:焊料連接
120:間隙
122:焊料球
124:側壁
126:裸片
128:包覆模制化合物
130:頂部表面
132:底部表面
134:頂部表面
136:底部表面
138:頂部表面
140:底部表面
142:頂部表面
144:底部表面
146:頂部表面
150:電子設備
160:電路系統
162:電路系統
164:電路系統
166:電路系統
168:電路系統
170:底部表面
172:頂部表面
202:接觸焊盤
204:佈線
206:金屬線
208:通孔
210:電介質層
302:柱
304:柱
308:邊緣400:方法
402、404、406、408、410、412、414:操作
500:載體
502:孔
504:種子層
506:體導體
540:初始表面
542:初始高度
600:方法
602、604、606、608、610、612、614:操作
700:載體/晶片封裝元件
702:遠端
704:二次表面
706:聚合物層
708:凹槽
710:導電材料
740:初始表面
742:初始高度
800:方法
802、804、806、808、810、812、814、816、818、820:操作
900:載體
904:二次表面
906:抗蝕劑層
908:暴露表面
940:初始表面
942:初始高度
為了可以更詳細地理解本發明的上述特徵的方式,經由參考實施例,可以做出對上文所簡要總結的本發明的更具體描述,其中一些實施例在附圖中圖示。然而,應當指出,附圖僅圖示了本發明的典型實施例,因此不應視為對本發明範圍的限制,因為本發明可以承認其他等同實施例。
[01] 圖1是多個柱設置在積體電路(IC)裸片周圍的晶片封裝元件的示意性截面圖。
[02] 圖2是圖示了與晶片封裝元件的再分佈層相鄰設置的柱的圖1的晶片封裝元件的局部截面圖。
[03] 圖3是顯示了設置在IC裸片周圍的柱的實例性幾何佈置的圖1的晶片封裝元件的示意性俯視圖。
[04] 圖4是製造被配置為增強再分佈層內的電路系統的可靠性的具有柱的晶片封裝元件的方法的流程圖。
[05] 圖5A至圖5F是處於圖4的方法的不同階段的晶片封裝元件的示意性截面圖。
[06] 圖6是製造被配置為增強再分佈層內的電路系統的可靠性的晶片封裝元件的方法的流程圖。
[07] 圖7A至圖7G是處於圖6的方法的不同階段的晶片封裝元件的示意性截面圖。
[08] 圖8是另一製造被配置為增強再分佈層內的電路系統的可靠性的晶片封裝元件的方法的流程圖。
[09] 圖9A至圖9I是處於圖6的方法的不同階段的晶片封裝元件的示意性截面圖。
為了便於理解,在可能的地方使用了相同的附圖標記來表示圖中公共的相同元件。應當設想,一個實施例的元件可以有益地併入其他實施例中。
100:晶片封裝元件
102:再分佈層
104:插入襯底
106:IC裸片
108:封裝襯底
110:柱
112:模制化合物
114:底部表面
116:印刷電路板(PCB)
118:焊料連接
120:間隙
122:焊料球
124:側壁
126:裸片
128:包覆模制化合物
130:頂部表面
132:底部表面
134:頂部表面
136:底部表面
138:頂部表面
140:底部表面
142:頂部表面
144:底部表面
146:頂部表面
150:電子設備
160:電路系統
162:電路系統
164:電路系統
166:電路系統
168:電路系統
Claims (20)
- 一種晶片封裝元件,包括 一第一積體電路(IC)裸片; 一襯底; 一再分佈層,提供該第一IC裸片的一電路系統與該襯底的一電路系統之間的電連接; 一模制化合物,被設置為與該第一IC裸片接觸,並且經由該再分佈層與該襯底隔開;以及 多個柱,被設置在該模制化合物中,並且與該第一IC裸片橫向隔開,該多個柱未電連接到該第一IC裸片的該電路系統。
- 根據請求項1之晶片封裝元件,其中該多個柱的一底部表面和該模制化合物的一底部表面接觸該再分佈層。
- 根據請求項2之晶片封裝元件,其中該多個柱的該底部表面和該模制化合物的該底部表面共面。
- 根據請求項1之晶片封裝元件,其中該多個柱由含金屬材料製成。
- 根據請求項1之晶片封裝元件,還包括 一第二IC裸片,被設置為與該模制化合物接觸,並且與該第一IC裸片橫向隔開,該第二IC裸片經由該再分佈層與該襯底隔開,其中該多個柱中的至少一些柱被設置在該第一IC裸片與該第二IC裸片之間。
- 根據請求項5之晶片封裝元件,其中該多個柱中的至少一些柱被設置在該第一IC裸片的、與該第二IC裸片相對的一側上。
- 根據請求項5之晶片封裝元件,其中該多個柱相對於該第一IC裸片的該電路系統和該第二IC裸片的一電路系統電浮動。
- 根據請求項7之晶片封裝元件,其中該多個柱的一頂部表面和一底部表面共面。
- 根據請求項7之晶片封裝元件,還包括 一記憶體裸片,堆疊在該第二IC裸片上,其中該第一IC裸片被配置為邏輯裸片。
- 一種晶片封裝元件,包括 一襯底; 一再分佈層,具有一電路系統,該電路系統經由焊料連接電耦合到該襯底的電路系統; 一第一積體電路(IC)裸片; 一第二積體電路(IC)裸片; 一模制化合物,被設置為與該第一IC裸片接觸,並且經由該再分佈層與該襯底隔開;以及 一第一多個柱,被設置在該第一IC裸片與該第二IC裸片之間的該模制化合物中,該第一多個柱經由該再分佈層與該襯底隔開。
- 根據請求項10之晶片封裝元件,其中該第一多個柱的一底部表面和該模制化合物的一底部表面共面,並且接觸該再分佈層。
- 根據請求項10之晶片封裝元件,其中該第一多個柱由含金屬材料製成。
- 根據請求項10之晶片封裝元件,還包括 一第二多個柱,被設置在該第一IC裸片的、與該第二IC裸片相對的一側上。
- 根據請求項10之晶片封裝元件,其中該多個柱相對於該第一IC裸片的一電路系統和該第二IC裸片的一電路系統電浮動。
- 根據請求項10之晶片封裝元件,還包括 一記憶體裸片,堆疊在該第二IC裸片上,其中該第一IC裸片被配置為邏輯裸片。
- 一種製造晶片封裝元件的方法,該方法包括 將一第一積體電路(IC)裸片安裝到一載體; 將一第二IC裸片安裝到該載體; 使用一模制化合物填充該第一IC裸片與該第二IC裸片之間形成的一間隙,該模制化合物被設置在一第一柱周圍,該第一柱被設置在該間隙中; 移除該模制化合物的一部分以暴露該第一IC裸片和該第二IC裸片的一電接觸焊盤;以及 在該模制化合物以及該第一IC裸片和該第二IC裸片上形成一再分佈層,該再分佈層具有一電路系統,該電路系統電連接到該第一IC裸片和該第二IC裸片的一電路系統。
- 根據請求項16之晶片封裝元件,還包括 移除該載體。
- 根據請求項16之晶片封裝元件,還包括 經由焊料連接將該再分佈層電性和機械耦合到一襯底。
- 根據請求項16之晶片封裝元件,其中安裝該第一IC裸片還包括 將邏輯裸片安裝到該載體;以及 其中安裝該第二IC裸片還包括 將一記憶體堆疊安裝到該載體。
- 根據請求項16之晶片封裝元件,其中移除該模制化合物的該一部分以暴露該第一IC裸片和該第二IC裸片的電接觸還包括 研磨該模制化合物。
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JP2000114413A (ja) * | 1998-09-29 | 2000-04-21 | Sony Corp | 半導体装置、その製造方法および部品の実装方法 |
TWI225292B (en) * | 2003-04-23 | 2004-12-11 | Advanced Semiconductor Eng | Multi-chips stacked package |
DE102006060411B3 (de) * | 2006-12-20 | 2008-07-10 | Infineon Technologies Ag | Chipmodul und Verfahren zur Herstellung eines Chipmoduls |
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KR20100083363A (ko) * | 2009-01-13 | 2010-07-22 | 삼성전자주식회사 | 반도체 패키지 장치 |
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