CN112786544A - 堆栈式硅封装组件的扇出集成 - Google Patents
堆栈式硅封装组件的扇出集成 Download PDFInfo
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- CN112786544A CN112786544A CN202011208840.9A CN202011208840A CN112786544A CN 112786544 A CN112786544 A CN 112786544A CN 202011208840 A CN202011208840 A CN 202011208840A CN 112786544 A CN112786544 A CN 112786544A
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- die
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Abstract
本公开的实施例涉及堆栈式硅封装组件的扇出集成。提供了一种芯片封装组件及其制造方法,其利用模制化合物中的多个柱来提高抗分层性。在一个示例中,提供了一种芯片封装组件,该芯片封装组件包括第一集成电路(IC)管芯、衬底、再分布层、模制化合物、以及多个柱。再分布层提供第一IC管芯的电路系统与衬底的电路系统之间的电连接。模制化合物被设置为与第一IC管芯接触并且通过再分布层与衬底隔开。多个柱被布置在模制化合物中并且与第一IC管芯横向隔开。多个接线柱没有电连接到第一IC管芯的电路系统。
Description
技术领域
本发明的各个实施例总体涉及芯片封装组件,并且具体涉及一种包括多个柱的芯片封装组件,该多个柱设置在模制化合物中,这些柱与至少一个集成电路(IC)管芯横向隔开,这些柱被配置为减少制造芯片封装组件期间模制化合物分层或开裂的可能性。
背景技术
诸如平板电脑、计算机、复印机、数码相机、智能电话、控制系统和自动柜员机等之类的电子设备经常采用利用芯片封装组件的电子部件来增加功能并且提高部件密度。传统管芯封装方案通常利用封装衬底(通常与硅通孔(TSV)插入衬底结合)来使得多个集成电路(IC)管芯能够安装到单个封装衬底。IC管芯可以包括存储器、逻辑或其他IC设备。
在许多下一代芯片封装组件中,诸如再分布层之类的扇出被用于将IC管芯连接到安装有IC管芯的衬底。IC管芯通常设置在模制化合物中,以向芯片封装组件提供改善的结构完整性。然而,模制化合物的裂纹和/或模制化合物与IC管芯分层经常传播到扇出中,这会导致扇出内的导体(即,电迹线)断裂或变坏。扇出内的断裂和/或损坏导体会导致性能下降、使用寿命缩短甚至导致设备发生故障。
因此,需要一种芯片封装组件,该芯片封装组件具有对IC管芯与安装有IC管芯的衬底之间设置的扇出内的导体的损坏和/或断裂的抗性。
发明内容
提供了一种芯片封装组件及其制造方法,其抑制对至少一个集成电路(IC)管芯与诸如插入衬底或封装衬底之类的底衬底之间设置的扇出(即,再分布层)内的导体造成的损坏和/或断裂。在一个示例中,扇出的稳健保护通过在接触上制造再分布层之前利用无磨工艺跨越相邻管芯产生共面接触来提供。在另一示例中,模制化合物中的多个柱用于抑制模制化合物的分层和/或开裂,从而降低了这些缺陷从模制化合物传播到再分布层的可能性,其中这些缺陷可能会损坏再分布层内的导体和/或使其断裂。
在一个示例中,提供了一种芯片封装组件,其包括第一集成电路(IC)管芯、衬底、再分布层、模制化合物、以及多个柱。再分布层提供第一IC管芯的电路系统与衬底的电路系统之间的电连接。模制化合物被设置为与第一IC管芯接触并且通过再分布层与衬底隔开。多个柱被设置在模制化合物中并且与第一IC管芯横向隔开。多个柱没有电连接到第一IC管芯的电路系统。
在另一示例中,提供了一种芯片封装组件,其包括第一集成电路(IC)管芯、第二集成电路(IC)管芯、衬底、再分布层、模制化合物、以及多个接线柱。再分布层具有电路系统,该电路系统经由焊料连接电耦合到衬底的电路系统。模制化合物被设置为与第一IC管芯接触并且通过再分布层与衬底隔开。第一多个柱被设置在第一IC与第二IC之间的模制化合物中。第一多个柱通过再分布层与衬底隔开。
在另一示例中,提供了一种制造芯片封装组件的方法,该方法包括:将第一集成电路(IC)管芯安装到载体;将第二IC管芯安装到载体;使用模制化合物填充在第一IC管芯与第二IC之间形成的间隙,该模制化合物被设置在第一柱周围,该第一柱设置在间隙中;移除模制化合物的一部分,以暴露第一IC管芯和第二IC的电接触;以及在模制化合物以及第一IC管芯和第二IC管芯上形成再分布层,该再分布层具有电路系统,该电路系统电连接到第一IC管芯和第二IC管芯的电路。
附图说明
为了可以更详细地理解本发明的上述特征的方式,通过参考实施例,可以做出对上文所简要总结的本发明的更具体描述,其中一些实施例在附图中图示。然而,应当指出,附图仅图示了本发明的典型实施例,因此不应视为对本发明范围的限制,因为本发明可以承认其他等同实施例。
图1是多个柱设置在集成电路(IC)管芯周围的芯片封装组件的示意性截面图。
图2是图示了与芯片封装组件的再分布层相邻设置的柱的图1的芯片封装组件的局部截面图。
图3是显示了设置在IC管芯周围的柱的示例性几何布置的图1的芯片封装组件的示意性俯视图。
图4是制造被配置为增强再分布层内的电路系统的可靠性的具有柱的芯片封装组件的方法的流程图。
图5A至图5F是处于图4的方法的不同阶段的芯片封装组件的示意性截面图。
图6是制造被配置为增强再分布层内的电路系统的可靠性的芯片封装组件的方法的流程图。
图7A至图7G是处于图6的方法的不同阶段的芯片封装组件的示意性截面图。
图8是另一制造被配置为增强再分布层内的电路系统的可靠性的芯片封装组件的方法的流程图。
图9A至图9I是处于图6的方法的不同阶段的芯片封装组件的示意性截面图。
为了便于理解,在可能的地方使用了相同的附图标记来表示图中公共的相同元件。应当设想,一个实施例的元件可以有益地并入其他实施例中。
具体实施方式
提供了一种芯片封装组件及其制造方法,其抑制对设置在至少一个集成电路(IC)管芯与诸如插入衬底或封装衬底之类的底衬底之间的扇出(可互换地称为“再分布层”)内的导体造成的损坏和/或断裂。在一个示例中,无磨工艺被用于在相邻IC管芯上产生共面接触焊盘,而不会研磨从IC管芯和模制化合物延伸的导电柱。由于研磨是模制化合物中裂纹生成和分层的常见原因,所以在一些示例中取消研磨操作会大大增强了模制化合物中此类缺陷的概率,因此,大大降低了此类缺陷导致裂纹传播到导体可能损坏或断裂的扇出中的概率。在其他示例中,即使在研磨被用于暴露IC管芯的接触焊盘的过程中,设置在模制化合物中的环绕至少一个集成电路(IC)管芯的多个柱被用于抑制模制化合物中裂纹生成和分层。
本文中所描述的芯片封装组件包括至少一个集成电路(IC)管芯,其被设置在模制化合物中并且安装在衬底上。再分布层被设置在IC管芯与衬底之间。再分布层经由焊料连接电性和机械耦合到衬底。再分布层提供了IC管芯与衬底之间的信号、接地和功率传输路径(即,电路系统)。衬底可以是封装衬底或插入衬底。当被利用时,柱没有延伸穿过IC管芯并且位于IC管芯的横向外侧。这些柱显著改善了模制化合物的机械性能,从而极大地提高了模制化合物在移除模制化合物的一部分以暴露IC管芯的接触焊盘或导体用于电连接到再分布层中制造的扇出的电路系统期间与IC管芯的抗开裂性或抗分层(即,剥离)性。由于如上所述的模制化合物不太容易出现或不太可能开裂或分层,所以此类缺陷极不可能传播到再分布层中,其中可能会损害再分布层的一个或多个布线,从而导致芯片封装组件的性能降低甚至发生故障。
本文中公开了用于防止损坏再分布层中制造的扇出的电路系统的其他示例和技术,其可替代地不用模制化合物内的柱。这些技术利用在模制化合物中蚀刻凹槽以暴露管芯接触焊盘。然后,在仍然暴露管芯接触焊盘的同时,在模制化合物上对介电材料进行图案化。导电材料沉积到凹槽中,并且与IC管芯的暴露的接触焊盘连接。导电材料与电介质材料的底部表面共面,使得可以直接制造再分布层,而没有研磨或在与再分布层相邻设置的聚合物材料中诱致其他机械应力。结果,与再分布层相邻设置的聚合物材料中的缺陷极不可能传播到再分布层中,其中可能会损害再分布层的一个或多个布线,从而导致芯片封装组件的性能下降甚至发生故障。
因此,增强模制化合物和与再分布层相邻的其他聚合物层的抗开裂性和/或抗分层性极大地改善了防止裂纹传播到扇出中,这会导致扇出内的导体损坏或断裂。因此,芯片封装组件的可靠性和性能显著提高。
现在,转到图1,示意性地图示了芯片封装组件100的示意性截面图,该芯片封装组件100具有与集成电路(IC)管芯106、126相邻的多个柱110,该多个柱110设置在模制化合物112中。芯片封装组件100还包括再分布层(RDL)102、插入衬底104、以及封装衬底108。再分布层102设置在IC管芯106与插入衬底104之间,并且还与模制化合物112接触。
尽管图1中示出了彼此横向隔开的两个IC管芯106、126,但是IC管芯的总数可以从一个到可以适配在芯片封装组件100内的管芯的尽可能多的数目的范围内。附加地,尽管图1图示了单个IC管芯106,但是IC管芯106可以是IC管芯的堆栈的底部管芯。更进一步地,尽管图1所图示的IC管芯126被示为IC管芯126的堆栈,但是可替代地,IC管芯126的堆栈可以由单个IC管芯126替换。可以用于芯片封装组件100的IC管芯106、126的示例包括但不限于诸如现场可编程门阵列(FPGA)之类的可编程逻辑设备、诸如高带宽存储器(HBM)之类的存储器设备、光学设备、处理器或其他IC逻辑结构。IC管芯106中的一个或多个IC管芯106可以可选地包括光学设备,诸如光电检测器、激光器、光源等。在图1的示例中,IC管芯106是逻辑管芯,而IC管芯126是堆叠在缓冲管芯上的多个存储器管芯。IC管芯126的堆栈可以封装在聚合物包覆模制化合物128中。
在图1所描绘的示例中,芯片封装组件100被配置为高带宽存储器(HBM)设备,其中IC管芯106被配置为逻辑管芯,诸如现场可编程门阵列(FPGA),而IC管芯126被配置为HBM管芯堆栈。应当设想,包括芯片封装组件100的IC管芯106、126的类型可以相同或不同,其包括除HBM管芯和FPGA管芯之外的类型。
每个IC管芯106、126包括底部表面140和顶部表面142。IC管芯106的底部表面140耦合到再分布层102的顶部表面146。最底部的IC管芯126的底部表面140也耦合到再分布层102的顶部表面146。再分布层102的底部表面144通过焊料连接118或其他合适电连接耦合到插入衬底104的顶部表面138。可选盖(未示出)可以设置在IC管芯106、126的顶部表面142上。当IC管芯106上存在盖或其他散热器时,热界面材料(TIM)可以设置在IC管芯106、126的顶部表面142与盖的底部表面之间,以增强了它们之间的热传递。在一个示例中,TIM可以是热凝胶或热环氧树脂,诸如封装部件附接粘合剂。在一些实现方式中,单独散热器可以设置在盖上方并且与之接触。
附加地,可选加强件(未示出)可以用于增强芯片封装组件100的刚度。当使用时,加强件可以由陶瓷、金属或其他各种无机材料制成,并且耦合到插入衬底104或封装衬底108中的一个衬底。
如上文所讨论的,IC管芯106、126的电路系统被连接到再分布层102的电路系统。在图2中,对IC管芯106、126与再分布层102之间的连接的细节进行进一步详述。再分布层102也与模制化合物112的底部表面114接触。
参照图2的局部截面图,IC管芯106、126包括接触焊盘202,IC管芯106、126的电路系统160终止于该接触焊盘202。接触焊盘202暴露于IC管芯106、126的底部表面140。在IC管芯106、126的底部表面140上直接制造再分布层102的顶部表面146。再分布层102包括至少三个金属层和电介质层,对该至少三个金属层和电介质层进行图案化,以产生再分布层102的电路系统162。在一个示例中,包括电介质层210内由图案化的金属线206和通孔208形成的电路系统162的布线204直接连接在RDL 102的顶部表面146上,而无需焊料连接。以这种方式,与利用焊料互连的连接相比,接触焊盘202之间的间隔可能具有更精细的间距。包括电路系统162的布线204终止并暴露于RDL的底部表面144,以便于与下方衬底的电路系统(例如,插入衬底104的电路系统164)进行焊料连接。
仅回到图1,再分布层102的电路系统162通过焊料连接118电性和机械地耦合到插入衬底104的电路系统164。插入衬底104的电路系统164类似地连接到封装衬底108的电路系统166。在图1所描绘的示例中,插入衬底104的底部表面136通过焊料连接118或其他合适连接电性和机械耦合到封装衬底108的顶部表面134。
芯片封装组件100可以安装到印刷电路板(PCB)116,以形成电子设备150。以这种方式,封装衬底108的电路系统166经由焊料球122或其他合适连接耦合到PCB 116的电路系统168。在图1所描绘的示例中,封装衬底108的底部表面132通过焊料球122电性和机械耦合到PCB的顶部表面130。
模制化合物112与再分布层102的顶部表面146接触。模制化合物112还填充IC管芯106、126之间限定的间隙120。模制化合物112还存在于IC管芯106的与间隙120相对的外侧上(即,IC管芯106的与相邻管芯126相对的一侧上)。在仅利用单个管芯的实施例中,模制化合物112被设置在IC管芯106的横向外侧。
模制化合物112向封装组件100提供了附加刚度,同时还保护了IC管芯106、126与再分布层102的电路系统之间的电连接。模制化合物112可以是诸如基于环氧树脂材料之类的聚合物材料或其他合适材料。当IC管芯126被设置在包覆模制化合物128中时,模制化合物112与包覆模制化合物128、再分布层102和IC管芯106接触。
柱110被设置在模制化合物112中。柱110用于增加模制化合物112与IC管芯106、126的侧面的抗开裂性或抗分层性,特别是当移除模制化合物112的一部分,以暴露IC管芯106的底部表面140,用于将IC管芯106、126的电路系统160电耦合到再分布层102的电路系统162时。当存在包覆模制化合物128时,柱110也增加了对模制化合物112从模制化合物128破裂、分离或分层的抗性。
柱110由硬度大于模制化合物112的硬度的材料制成。柱110可以由电介质或金属材料制成。在一个示例中,柱110由一个或多个金属层制成。例如,柱110可以由铜、钛或其他合适金属材料制成。当柱110由铜制成时,柱110可以包括一个或多个种子层以便于镀覆,诸如钛、钨、钽和镍钒等。
柱110通常具有细长几何形状,其具有沿长方向的主轴线,该主轴线基本垂直于IC管芯106的底部表面140和插入衬底104的顶部表面138。柱110的横截面轮廓大致上呈圆形,但是可以具有任何其他合适的几何形状。
柱110的底部表面170通常与再分布层102的顶部表面146共面。柱110的底部表面170通常也与模制化合物112的底部表面114共面。每个柱110通常从底部表面170延伸到顶部表面172,使得表面170、172之间限定的柱110的长度与IC管芯106的侧壁124至少部分重叠。IC管芯106的侧壁124通常限定IC管芯106的高度,也就是说,IC管芯106的顶部表面140和底部表面142之间的距离。
在一个示例中,柱110的顶部表面172与IC管芯106的顶部表面142共面。在另一示例中,柱110的顶部表面172位于IC管芯106的顶部表面142下方。无论顶部表面172的位置如何,柱110的底部表面170都可以在IC管芯106的底部表面140下方延伸。应当设想,在一些示例中,底部表面170可以延伸到再分布层102中。
在具有呈堆栈布置的IC管芯126的另一示例中,柱110的顶部表面172与最上部的IC管芯126的顶部表面142共面。在另一示例中,柱110的顶部表面172位于最上部的IC管芯126的顶部表面142下方。无论顶部表面172的位置如何,柱110的底部表面170都可以在最底部的IC管芯126的底部表面140的下方延伸。应当设想,在一些示例中,底部表面170可以延伸到再分布层102中。
在模制化合物112沉积之前或之后,可以形成柱110。例如,在模制化合物112沉积在IC管芯106和柱110周围之前或之后,柱110可以形成在临时载体上(如下文所示出的和描述的)。柱110可以例如通过镀覆或其他合适沉积技术形成在临时载体上。在另一示例中,模制化合物112可以沉积在IC管芯106、126周围,然后在模制化合物112中形成孔,该柱110设置在该模制化合物112中。包含柱110的孔可以通过蚀刻、激光钻孔、压花、热成型、机械钻孔或其他合适技术形成。
通常,提供柱110以改善模制化合物112的开裂抗性和分层抗性。如此,柱110没有被耦合到IC管芯106、126的电路系统160。柱110还可以耦合到再分布层102的电路系统162。柱110也可以不耦合到插入衬底104的电路系统164。在图1所描绘的示例中,柱110相对于IC管芯106、126的电路系统160、162、164中的一个或多个或甚至全部、再分布层102和插入衬底104电浮动。
柱110可以由增加模制化合物112的刚度的材料制成。合适材料包括与模制化合物112相比具有良好粘合性和更大硬度的材料。合适材料可以是导电材料或不导电材料。合适材料可以比模制化合物112更导热。合适材料包括金属,诸如铜、焊料、钛、钽和镍钒等。合适材料还包括保留在粘合剂中的工业金刚石。柱110可以是单个固体,或由诸如粉末、金属棉或离散形状之类的保持在粘合剂中的多个元素组成。包括柱110的材料也可以是焊膏、金属纤维、金属粉末、金属颗粒、金属球、导热粘合剂或其他合适导热材料。
在一个示例中,柱110是导热的并且垂直远离插入衬底104的顶部表面138在IC管芯106、126之间提供稳健导电传热路径。如果在管芯106、126上方利用盖(未示出),则可以在柱110与盖之间利用热界面材料(TIM),以在柱110与盖之间提供稳健传热界面,以从IC管芯106、126之间引出热量。
柱110可以具有任何合适截面轮廓,并且通常具有至少与IC管芯106的高度相同的长度。在一个示例中,柱110的截面轮廓是圆形的。可以选择柱110的数目、尺寸、密度和位置,以在模制化合物112与IC管芯106、126和包覆模制化合物128(如果存在)中的至少一个之间提供期望的剪切抗性。
图3是图1的芯片封装组件100的示意性俯视图,以显示设置在IC管芯106、126之间的柱110的示例性几何布置。在图3所描绘的示例中,柱110包括设置在相邻IC管芯106、126之间的柱302。可选地,柱110可以包括设置在IC管芯106、126外侧并且设置在IC管芯106、126与插入衬底104的边缘308之间的柱304。换言之,柱304设置在IC管芯106、126外侧(如果存在,则设置在包覆模制化合物128外侧),并且由模制化合物112包围。可以选择支柱302的位置、大小和密度以增强期望位置中模制化合物112的剪切抗性、开裂抗性或分层抗性。可以选择柱304(如果存在)的位置、大小和密度,以增强通过期望位置中的模制化合物112的垂直传热。在下文所进一步描述的附图中提供的示例性非限制性示例中,提供了柱110的附加细节。
图4是相邻IC管芯之间具有电浮柱110的诸如上文参考图1至图2所描述的芯片封装组件100等之类的芯片封装组件的制造方法400的流程图。图5A至图5F是处于图4的方法400的不同阶段的芯片封装组件的示意性截面图。应当指出,与图1相比较,图5A至图5F所图示的管芯106、126和其他部件的方位相差180°。换句话说,与图1所示的方位相比较,图5A至图5F所图示的管芯106、126和其他部件的方位被颠倒了。
如图5A所示,方法400开始于操作402,在该操作402处,将IC管芯106、126附接到载体500。载体500仅在初始制造操作期间使用,如此在将IC管芯106、126安装到诸如插入衬底104之类的衬底并且完成制造芯片封装组件100之前,载体500被可移动地附接以附接IC管芯106、126。在一个示例中,IC管芯106、126的顶部表面142使用可释放的压敏粘合剂被附接到载体500。一个IC管芯或多个IC管芯126可以封装在包覆模制化合物128中,诸如上文参考图1所描述和示出的包覆模制化合物。
在操作404处,模制化合物112被设置在管芯106、126周围并且与载体500接触。模制化合物112延伸超出IC管芯106、126的底部表面140直到初始表面540,如图5B所图示的。初始高度542被定义为IC管芯106、126的初始表面540和底部表面140之间限定的距离。模制化合物112可以通过另一合适方法旋涂、分配、包覆模压或沉积。在操作404处,模制化合物112填充相邻管芯106、126之间限定的间隙120。
在操作406处,在IC管芯106、126之间的模制化合物112中形成孔502,如图5C所示。孔502可以例如通过蚀刻、激光钻孔、压花、热成型、机械钻孔或其他合适技术形成。孔502的深度可能小于初始高度542,该深度延伸到IC管芯106的顶部表面140和底部表面142之间限定的距离,或延伸到载体500(使得孔的末端502基本上与IC管芯106、126的顶部表面142共面,使得载体500通过孔502暴露)。
在操作408处,孔502随后填充有加强材料以形成柱110,如图5D所示。孔502可以通过将材料分配到孔502中或在孔502中电镀材料以形成孔110来形成。在一个示例中,种子层504沉积在孔502中。例如,种子层504可以被沉积在形成孔502的底部的模制化合物112上,或当通过孔502暴露时,可以被沉积在载体500上。种子层504可以使用化学气相沉积、物理气相沉积、喷墨印刷或其他合适技术来沉积。种子层504为随后沉积在孔502中的金属材料提供粘附层以继续形成柱110。种子层504可以可选地被沉积在孔502的侧壁上。在图5D所示的示例中,种子层504由铜制成。在沉积种子层504之后,体导体506被沉积在种子层504上,如图5D所示。体导体506可以使用无电镀、电镀、化学气相沉积、物理气相沉积或其他合适技术而被沉积在种子层504上。体导体506完全或接近模制化合物112的初始表面540填充孔502。在图5D所示的示例中,体导体506是铜,其直接镀在种子层504上。当孔502较浅时,有利地,需要较少材料来填充孔502并且形成柱110,这节省了成本。当孔502较深时,填充孔502并且形成柱110的导电材料促进热量从芯片封装组件100中传递出去,这有利地提高了性能可靠性。
在操作410处,对模制化合物112的初始表面540和柱110的末端进行研磨,机械或以其他方式移除,以使模制化合物112的底部表面114、管芯接触焊盘202和柱110的底部表面170共面,如图5E所示。柱110抑制模制化合物112萌生裂纹、与管芯106、126的侧壁124(当存在时,和/或包覆模制化合物128)开裂、分层或以其他方式分离。由于管芯106、126的侧壁124萌生裂纹、与管芯106、126的侧壁124开裂、分层或以其他方式分离的可能性较小,所以此类缺陷极不可能传播到RDL层102中,其中可能会损害布线204中的一个或多个布线204,从而导致芯片封装组件100的性能降低甚至发生故障。
在操作412处,在不使用焊料连接的情况下,直接在模制化合物112的底部表面114上制造RDL层102,如图5F所示。RDL层102通过沉积形成金属布线204的至少三个或更多个介电层来制造。金属布线204可以呈互连金属线206和通孔208的形式,其形成再分布层102的电路系统162。
在操作414处,移除载体500,并且RDL层102利用焊料连接118电性和机械连接到插入衬底104,如图1所示。在操作414处,封装衬底108利用焊料连接器118电性和机械连接到插入衬底104,以完成芯片封装组件100的制造。制造芯片封装组件100除了利用上文所描述的柱110之外还可以包括其他步骤和部件。
图6是制造芯片封装组件的方法600的流程图,其中IC管芯106、126设置在模制化合物112中,除了利用方法600制造的芯片封装组件可选地无需在相邻IC管芯106、126之间设置电浮柱110之外,该芯片封装组件与上文参考图1至图2所描述的芯片封装组件100类似。图7A至图7G是处于图6的方法600的不同阶段的芯片封装组件的示意性截面图。应当指出,图7A至图7G所图示的管芯106、126和其他部件的方位与图1相比相差180度。换句话说,与图1所示的方位相比较,图7A至图7G所图示的管芯106、126和其他部件的方位被颠倒了。
方法600开始于操作602,在该操作602处,将IC管芯106、126附接到载体700,如图7A所示。载体700仅在初始制造操作期间使用,如此在将IC管芯106、126安装到诸如插入衬底104之类的衬底并且完成芯片封装组件100制造之前,载体700被可移除地附接以附接IC管芯106、126。在一个示例中,IC管芯106、126的顶部表面142使用可释放的压敏粘合剂被附接到载体700。一个IC管芯或多个IC管芯106、126可以封装在包覆模制化合物128中,诸如上文参考图1所描述和示出的包覆模制化合物。
在操作604处,模制化合物112被设置在管芯106、126周围并且与载体700接触。模制化合物112延伸超出IC管芯106、126的底部表面140直到初始表面740,如图7B所图示的。初始高度742被定义为IC管芯106、126的初始表面740和底部表面140之间限定的距离。模制化合物112可以通过另一合适方法旋涂、分配、包覆模压或沉积。在操作604处,模制化合物112填充相邻管芯106、126之间限定的间隙120。如图7B所示,接触焊盘202的远端702与模制化合物112的初始表面740之间的间隔可以跨越IC管芯106、126中的单个IC管芯发生变化和/或可以跨越IC管芯106、126发生变化。模制化合物112的厚度通常大于或等于接触焊盘202中的最长接触焊盘202延伸超出IC管芯106、126的底部表面140的距离。
在操作606处,相对于柱110选择性地蚀刻模制化合物112的初始表面740,以在模制化合物112中限定二次表面704,如图7C所示。选择性蚀刻允许接触焊盘202的远端702延伸超出模制化合物112的二次表面704。
在操作608处,在模制化合物112的二次表面704上沉积聚合物层706并且在该模制化合物112的二次表面704上对其进行图案化,如图7D所示。对聚合物层706进行图案化,使得形成凹槽708以暴露接触焊盘202的远端702。在一个示例中,凹槽708形成在接触焊盘202的每个远端702周围。聚合物层706的厚度足以使接触焊盘202的每个远端702凹入凹槽708内。换句话说,在对聚合物层706进行图案化之后,远端702位于模制化合物112的二次表面704下方。在一个示例中,聚合物层706由聚酰亚胺或其他合适介电材料形成。在图案化之后,聚合物层706的暴露表面成为模制化合物112的底部表面114。
在操作610处,凹槽708填充有导电材料710,并且使得其与模制化合物112的初始表面740共面,如图7E所示。填充凹槽708的导电材料710使管芯106、126的电路系统160延伸,以与模制化合物112的底部表面114共面,使得可以直接在导电材料710上形成RDL层102的电路系统162(即,没有焊料连接)。由于模制化合物112未经历对模制化合物112诱致剪切力的研磨或其他机械过程,所以模制化合物112基本上不受管芯106、126的侧壁124(如果存在,和/或包覆模制化合物128)萌生裂纹、与该管芯106、126的侧壁124开裂、分层或分离的影响。由于管芯106、126的侧壁124萌生裂纹、与管芯106、126的侧壁124开裂、分层或其他分离的可能性较小,所以此类缺陷极不可能传播到RDL层102中,其中可能会损害布线204中的一个或多个布线204,从而导致芯片封装组件100的性能降低甚至发生故障。
在操作612处,在不使用焊料连接的情况下,直接在模制化合物112的底部表面114上制造RDL层102,如图7F所示。RDL层102通过沉积形成金属布线204的至少三个或更多个介电层来制造。金属布线204可以呈形成再分布层102的电路系统162的互连金属线206和通孔208的形式。通过在没有使用焊接连接的情况下,直接在模制化合物112的底部表面114上制造RDL层102,可以实现用于与管芯106、126的电接口的更高的间距密度。
在操作614处,移除载体700,并且RDL层102利用焊料连接118电性和机械连接到插入衬底104,如图7G所示。在操作614处,封装衬底108还利用焊料连接118电性和机械连接到插入衬底104,以完成芯片封装组件700的制造。芯片封装组件700与芯片封装组件100基本相同,除了缺少柱110以及接触焊盘202和导电材料710如何在IC管芯106、126的电路系统160与RDL层102的电路162之间进行连接的配置之外。芯片封装组件的制造700可以包括其他步骤和部件。
图8是制造芯片封装组件的方法800的流程图,其中IC管芯106、126设置在模制化合物112中,除了利用方法600制造的芯片封装组件可选地无需在相邻IC管芯106、126之间设置电浮柱110之外,该芯片封装组件与上文参考图1至图2所描述的芯片封装组件100类似。图9A至图9I是处于图8的方法800的不同阶段的芯片封装组件的示意性截面图。应当指出,图9A至图9I所图示的管芯106、126和其他部件的方位与图1相比相差180度。换句话说,与图1所图示的方位相比较,图9A至图9I所图示的管芯106、126和其他部件的方位被颠倒了。
方法800开始于操作802,在该操作802处,将IC管芯106、126附接到载体900,如图9A所示。载体900仅在初始制造操作期间使用,如此在将IC管芯106、126安装到诸如插入衬底104之类的衬底并且完成芯片封装组件100制造之前,载体900被可移动地附接以附接IC管芯106、126。在一个示例中,IC管芯106、126的顶部表面142使用可释放的压敏粘合剂被附接到载体900。一个IC管芯或多个IC管芯106、126可以封装在包覆模制化合物128中,诸如上文参考图1所描述和示出的包覆模制化合物。
在操作804处,模制化合物112被设置在管芯106、126周围并且与载体900接触。模制化合物112延伸超出IC管芯106、126的底部表面140直到初始表面940,如图9B所示。初始高度942被定义为IC管芯106、126的初始表面940和底部表面140之间限定的距离。模制化合物112可以通过另一合适方法旋涂、分配、包覆模压或沉积。在操作804处,模制化合物112填充相邻管芯106、126之间限定的间隙120。如图9B所示,接触焊盘202的远端702与模制化合物112的初始表面940之间的间隔可以跨越IC管芯106、126中的单个IC管芯发生变化和/或跨越IC管芯106、126发生变化。模制化合物112的厚度通常大于或等于接触焊盘202中的最长接触焊盘202延伸超出IC管芯106、126的底部表面140的距离。
在操作806处,相对于柱110选择性地蚀刻模制化合物112的初始表面940,以在模制化合物112中限定二次表面904,如图9C所示。选择性蚀刻允许接触焊盘202的远端702延伸超出模制化合物112的二次表面904。
在操作808处,抗蚀剂层906被沉积在模制化合物112的二次表面904上,如图9D所示。沉积抗蚀剂层906至覆盖其全部而非大部分接触焊盘202的厚度。
在操作810处,移除抗蚀剂层906的顶部部分以使抗蚀剂层906的暴露表面908与接触焊盘202的远端702共面,如图9E所示。可以通过化学机械抛光、飞切(fly-cut)或其他合适工艺来移除抗蚀剂层906的顶部部分。操作808还移除了一些或全部接触焊盘202的一部分,使得接触焊盘202的远端702变得彼此共面,并且与抗蚀剂层906的暴露表面908共面。由于保护模制化合物112不受在移除抗蚀剂层906的顶部部分和接触焊盘202的一部分的同时引起的应力的影响,所以基本上防止了模制化合物112的裂纹萌生、开裂和分层。
在操作812处,移除剩余抗蚀剂层906,如图9F所示。可以通过抗蚀剂剥除工艺(例如,化学抗蚀剂移除或其他合适工艺)来移除抗蚀剂层906。
在操作814处,在模制化合物112上沉积聚合物层706并且在该模制化合物112上对其进行图案化,如图9G所示。对聚合物层706进行图案化,使得在接触焊盘202的每个远端702周围形成凹槽708。聚合物层706的厚度足以使接触焊盘202的每个远端702凹入凹槽708内。换句话说,在对聚合物层706进行图案化之后,远端702位于聚合物层706的顶部表面下方。在一个示例中,聚合物层706由聚酰亚胺或其他合适介电材料形成。在图案化之后,聚合物层706的暴露表面成为模制化合物112的底部表面114。
在操作816处,凹槽708填充有导电材料710,并且使得其与模制化合物112(例如,聚合物层706)的底部表面114共面,如图9H所示。填充凹槽708的导电材料710使管芯106、126的电路系统160延伸,以与模制化合物112的底部表面114共面,使得可以直接在导电材料710上形成RDL层102的电路162(即,没有焊料连接)。由于模制化合物112受到抗蚀剂层906的保护,所以由于模制化合物112未经历对模制化合物112诱致剪切力的研磨或其他机械过程,因此模制化合物112基本上不受管芯106、126的侧壁124(如果存在,和/或包覆模制化合物128)萌生裂纹、与管芯106、126的侧壁124开裂,分层或其他分离的影响。由于管芯106、126的侧壁124萌生裂纹、与管芯106、126的侧壁124开裂、分层或其他分离的可能性较小,所以此类缺陷极不可能传播到RDL层102中,其中可能会损害布线204中的一个或多个布线204,从而导致芯片封装组件100的性能降低甚至发生故障。
在操作818处,直接在模制化合物112的底部表面114上制造RDL层102,而无需使用焊料连接,如图9I所示。RDL层102通过沉积形成金属布线204的至少三个或更多个介电层来制造。金属布线204可以呈形成再分布层102的电路系统162的互连金属线206和通孔208的形式。通过在没有使用焊接连接的情况下,直接在模制化合物112的底部表面114上制造RDL层102,可以实现用于与管芯106、126的电接口的更高的间距密度。
在操作820处,移除载体900并且RDL层102利用焊料连接118电性和机械连接到插入衬底104,如图7G所示。在操作820处,封装衬底108还利用焊料连接118电性和机械连接到插入衬底104,以完成芯片封装组件700的制造。如上文所陈述的,芯片封装组件700与芯片封装组件100基本相同,除了缺少柱110以及接触焊盘202和导电材料710如何在IC管芯106、126的电路系统160与RDL层102的电路系统162之间进行连接的配置之外。芯片封装组件700的制造可以包括其他步骤和部件。
因此,已经提供了一种芯片封装组件及其制造方法,其利用设置在集成电路(IC)管芯周围的多个柱和增强模制化合物和与再分布层相邻的其他聚合物层的开裂抗性和/或分层抗性的无磨工艺。增强开裂抗性和/或分层抗性极大地改善了防止裂纹传播到再分布层的扇出中,这会导致再分布层电路系统内的导体损坏或断裂。因此,芯片封装组件的可靠性和性能显著提高。
除了以下权利要求书之外,可以在以下非限制性示例中描述所公开的技术。示例1以有利地降低模制化合物中裂纹萌生的可能性的方式利用模制化合物的研磨,以利用与研磨过程相关联的节省成本的优点。示例2至3利用有利地消除了对模制化合物进行研磨以减少模制化合物中裂纹萌生的概率的技术。
示例1:一种制造芯片封装组件的方法,包括:将IC管芯附接到载体;将模制化合物设置在IC管芯周围;在IC管芯之间的模制化合物中形成孔;使用加强材料填充孔,以形成柱;移除模制化合物的一部分和柱的末端,以使模制化合物的底部表面、管芯接触焊盘和柱的底部表面共面;在不使用焊料连接的情况下,直接在模制化合物的底部表面上制造再分布层;以及移除载体,利用焊料连接将再分布层电性和机械连接到插入衬底,并且利用焊料连接将封装衬底电性和机械连接到插入衬底。
示例2:一种制造芯片封装组件的方法,包括:将IC管芯附接到载体;将模制化合物布置在管芯周围并且与载体接触;相对于从IC管芯延伸的接触焊盘(即,柱)选择性地蚀刻模制化合物的初始表面;在模制化合物上沉积聚合物层并且对其进行图案化,以形成暴露接触焊盘的凹槽;使用导电材料填充该凹槽并且使导电材料与模制化合物共面;在不使用焊料连接的情况下,直接在模制化合物上制造再分布层;移除载体,并且利用焊料连接将再分布层电连接到插入衬底,并且利用焊料连接将封装衬底电性和机械连接到插入衬底。
示例3:一种制造芯片封装组件的方法,包括:将IC管芯附接到载体;将模制化合物布置在管芯周围并且与载体接触;相对于从IC管芯延伸的接触焊盘(即,柱)选择性地蚀刻模制化合物的初始表面;在模制化合物上沉积抗蚀剂层;移除抗蚀剂层的顶部部分,以使抗蚀剂层的暴露表面与接触焊盘的远端共面;移除剩余抗蚀剂层;在模制化合物上沉积聚合物层并且对其进行图案化,以形成凹槽,使用导电材料填充凹槽并且使导电材料与模制化合物共面;在不使用焊料连接的情况下,直接在模制化合物上制造再分布层;移除载体,利用焊料连接将再分布层电性和机械连接到插入衬底,然后利用焊料连接将封装衬底电性和机械地连接到插入衬底。
示例4:一种芯片封装组件,包括第一集成电路(IC)管芯;衬底;再分布层,其具有电路系统,该电路系统在第一IC管芯的电路系统与衬底的电路系统之间提供电连接;模制化合物,其被设置为与第一IC管芯接触并且通过再分布层与衬底隔开;多个接触焊盘,其从第一管芯延伸并且其末端暴露在模制化合物中形成的凹槽中;以及导电材料,其设置在凹槽中并且将衬底的电路系统电耦合到再分布层的电路系统。
示例5:一种芯片封装组件,包括第一集成电路(IC)管芯;衬底;再分布层,其具有电路系统,该电路系统在第一IC管芯的电路系统与衬底的电路系统之间提供电连接;模制化合物,其被设置为与第一IC管芯接触并且通过再分布层与衬底隔开;介电层,其设置在模制化合物与再分布层之间;多个接触焊盘,其从第一管芯延伸并且其末端暴露在介电层中形成的凹槽中;以及导电材料,其设置在凹槽中并且将衬底的电路系统电耦合到再分布层的电路系统。
有利地,至少示例2和3的方法也可以用于增加支柱(即,接触焊盘)的高度和重塑,从而增加IC管芯的底部表面与RDL层的顶部表面之间的模制化合物缓冲。该方法还可以用于增加支柱尺寸,以适应从无法或不会提供统一支柱尺寸的第三方供应商获得IC管芯。
虽然前述内容针对本发明的实施例,但是在不背离本发明的基本范围的情况下,可以设计本发明的其他进一步实施例,并且本发明的范围由所附权利要求书确定。
Claims (20)
1.一种芯片封装组件,包括:
第一集成电路(IC)管芯;
衬底;
再分布层,提供所述第一IC管芯的电路系统与所述衬底的电路系统之间的电连接;
模制化合物,被设置为与所述第一IC管芯接触并且通过所述再分布层与所述衬底隔开;以及
多个柱,被设置在所述模制化合物中并且与所述第一IC管芯横向隔开,所述多个柱未电连接到所述第一IC管芯的所述电路系统。
2.根据权利要求1所述的芯片封装组件,其中所述多个柱的底部表面和所述模制化合物的底部表面接触所述再分布层。
3.根据权利要求2所述的芯片封装组件,其中所述多个柱的所述底部表面和所述模制化合物的所述底部表面共面。
4.根据权利要求1所述的芯片封装组件,其中所述多个柱由含金属材料制成。
5.根据权利要求1所述的芯片封装组件,还包括:
第二IC管芯,被设置为与模制化合物接触并且与所述第一IC管芯横向隔开,所述第二IC管芯通过所述再分布层与所述衬底隔开,其中所述多个柱中的至少一些柱被设置在所述第一IC管芯与所述第二IC管芯之间。
6.根据权利要求5所述的芯片封装组件,其中所述多个柱中的至少一些柱被设置在所述第一IC管芯的与所述第二IC管芯相对的一侧上。
7.根据权利要求5所述的芯片封装组件,其中所述多个柱相对于所述第一IC管芯的所述电路系统和所述第二IC管芯的电路系统电浮动。
8.根据权利要求7所述的芯片封装组件,其中所述多个柱的顶部表面和底部表面共面。
9.根据权利要求5所述的芯片封装组件,还包括:
存储器管芯,堆叠在所述第二IC管芯上,其中所述第一IC管芯被配置为逻辑管芯。
10.一种芯片封装组件,包括:
衬底;
再分布层,具有电路系统,所述电路系统经由焊料连接电耦合到所述衬底的电路系统;
第一集成电路(IC)管芯;
第二集成电路(IC)管芯;
模制化合物,被设置为与所述第一IC管芯接触并且通过所述再分布层与所述衬底隔开;以及
第一多个柱,被设置在所述第一IC管芯与所述第二IC管芯之间的所述模制化合物中,所述第一多个柱通过所述再分布层与所述衬底隔开。
11.根据权利要求10所述的芯片封装组件,其中所述第一多个柱的底部表面和所述模制化合物的底部表面共面并且接触所述再分布层。
12.根据权利要求10所述的芯片封装组件,其中所述第一多个柱由含金属材料制成。
13.根据权利要求10所述的芯片封装组件,还包括:
第二多个柱,被设置在所述第一IC管芯的与所述第二IC管芯相对的一侧上。
14.根据权利要求10所述的芯片封装组件,其中所述多个柱相对于所述第一IC管芯的电路系统和所述第二IC管芯的电路系统电浮动。
15.根据权利要求10所述的芯片封装组件,还包括:
存储器管芯,堆叠在所述第二IC管芯上,其中所述第一IC管芯被配置为逻辑管芯。
16.一种制造芯片封装组件的方法,所述方法包括:
将第一集成电路(IC)管芯安装到载体;
将第二IC管芯安装到所述载体;
使用模制化合物填充所述第一IC管芯与所述第二IC之间形成的间隙,所述模制化合物被设置在第一柱周围,所述第一柱被设置在所述间隙中;
移除所述模制化合物的一部分以暴露所述第一IC管芯和所述第二IC管芯的电接触焊盘;以及
在所述模制化合物以及第一IC管芯和第二IC管芯上形成再分布层,所述再分布层具有电路系统,所述电路系统电连接到所述第一IC管芯和所述第二IC管芯的电路系统。
17.根据权利要求16所述的方法,还包括:
移除所述载体。
18.根据权利要求16所述的方法,还包括:
经由焊料连接将所述再分布层电性和机械耦合到衬底。
19.根据权利要求16所述的方法,其中安装所述第一IC管芯还包括:将逻辑管芯安装到所述载体;以及
其中安装所述第二IC管芯还包括:将存储器堆栈安装到所述载体。
20.根据权利要求16所述的方法,其中移除所述模制化合物的所述一部分以暴露所述第一IC管芯和所述第二IC管芯的电接触还包括:
研磨所述模制化合物。
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US11876075B2 (en) * | 2021-12-23 | 2024-01-16 | Nanya Technology Corporation | Semiconductor device with composite bottom interconnectors |
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JP2000114413A (ja) * | 1998-09-29 | 2000-04-21 | Sony Corp | 半導体装置、その製造方法および部品の実装方法 |
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