CN102820281A - 用于集成电路器件的3d集成微电子组件及其制作方法 - Google Patents
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Abstract
本发明涉及用于集成电路器件的3D集成微电子组件及其制作方法。一种3D中介层(及其制作方法),包括具有相对的第一和第二表面的晶体基板装卸器,其中在第一表面中形成腔体。绝缘材料层在限定腔体的装卸器的表面上形成。腔体被填充以柔性电介质材料。多个电互连通过中介层形成。每个电互连包括通过晶体基板装卸器形成的从第二表面延伸到腔体的第一孔、通过柔性电介质材料形成以便从第一孔延伸且与之对准的第二孔、沿着第一孔的侧壁形成的绝缘材料层以及通过第一和第二孔延伸的导电材料。
Description
技术领域
本发明涉及半导体封装,且更具体而言,涉及一种在其上安装半导体器件的3D中介层(interposer)。
背景技术
半导体器件的趋势是封装在较小封装(其在提供片外信令连接时保护芯片)中的较小集成电路器件(IC器件,也称为芯片)。最近发展和提炼了在单个封装中堆叠相关芯片的3D封装。3D封装可以导致增加的密度和较小的形状因子、较好的电性能(因为较短的互连长度,这允许增加的器件速度和较低的功耗)、较好的异构集成(即,集成诸如图像传感器及其处理器这样的不同功能层)以及较低的成本。包括先通孔(Via-First)、后通孔(Via-Last)和中通孔(Via-middle)工艺的用于形成穿硅通孔(TSV)的现有3D IC封装技术利用本质上复杂且昂贵的半导体光刻工艺。因此,世界上很少公司可以付得起每年在CMOS R&D中的几十亿美元来保持步伐。
另一相关3D封装技术是中介层。常规中介层是在基板上、在基板中和/或通过基板形成有导电图案以提供用于半导体器件的电接口的绝缘基板(典型地,塑料或陶瓷)。中介层常用于采用使用焊球来创建芯片和中介层之间的电连接的倒装芯片方法的芯片组装技术。中介层可以提供相对于半导体器件上的电连接图案或密度具有修改、增加或减小的连接图案或密度的电连接。
更近来,随着穿硅通孔的出现,已发展了3D硅和玻璃中介层以在几何尺寸和材料方面均增加印刷电路板和集成电路之间的缝隙,以用于系统级封装(SiP)、层叠封装(PoP)、倒装芯片球栅阵列(fc-BGA)或更新的扇出晶片级封装。3D中介层将晶片级技术和优点与3D路由能力(例如,更高的分辨率和更精细的节距/密度)相组合。
常规3D中介层在图1中示出。中介层1包括硅基板2、通过基板2延伸且通过基板2形成电接触的穿硅通孔3、路由层4和SMT兼容接触5、倒装芯片连接器6(在其上安装IC芯片7)。制造中介层1中的一个难度涉及随着基板2的宽度增加难以制作的通孔3(例如,要求昂贵的半导体溅射工具)。此外,由于中介层和在其上安装中介层的PC板之间的不同热和机械特性所导致的热应力,中介层1和底层印刷电路板之间的SMT接触5可能失效。需要一种补充的、成本有效的TSV解决方案来增强3D中介层的性能。
发明内容
本发明是一种解决常规中介层的缺陷的3D中介层及其制作方法。
中介层包括具有相对的第一和第二表面的晶体基板装卸器(handler)(其中在第一表面中形成腔体)、布置在限定腔体的装卸器的表面上的绝缘材料层、布置在腔体中的柔性电介质材料以及多个电互连。每个电互连包括通过晶体基板装卸器形成的从第二表面延伸到腔体的第一孔、通过柔性电介质材料形成以便从第一孔延伸且与第一孔对准的第二孔、沿着第一孔的侧壁形成的绝缘材料层以及通过第一和第二孔延伸的导电材料。
形成中介层的方法包括:在具有相对的第一和第二表面的晶体基板装卸器中形成腔体,其中在晶体基板装卸器的第一表面中形成腔体;形成通过晶体基板装卸器从第二表面延伸到腔体的多个第一孔;在限定腔体的装卸器的表面上和在第一孔的侧壁上形成绝缘材料层;在腔体中形成柔性电介质材料;形成通过柔性电介质材料的第二孔,使得第二孔中的每一个从第一孔之一延伸且与之对准;以及针对从第一孔之一延伸且与之对准的第二孔中的每一个,形成通过一个第一孔和一个第二孔延伸的导电材料。
本发明的其他目的和特征将通过说明书、权利要求书和附图的研究而将变得显见。
附图说明
图1是常规中介层的剖面侧视图。
图2-7是顺序地示出在形成本发明的中介层中的步骤的剖面侧视图。
图8是集成到本发明的中介层的IC器件的剖面侧视图。
具体实施方式
本发明是一种3D中介层,其形成如下面描述且在图2-7中示出。形成工艺开始于如图2中所示的晶体基板装卸器10。非限制性示例可以包括具有约600μm的厚度的晶体基板的装卸器。腔体12可以通过使用激光、等离子体蚀刻工艺、喷砂工艺、机械研磨工艺或任意其他类似的方法而形成在装卸器中。优选地,腔体12通过光刻等离子体蚀刻而形成,该光刻等离子体蚀刻包括在装卸器10上形成光致抗蚀剂层、对光致抗蚀剂层进行图案化以露出装卸器10的选择部分以及然后执行等离子体蚀刻工艺(例如,使用SF6等离子体)以去除装卸器10的露出部分以形成腔体12。优选地,腔体不进一步延伸超过晶体基板厚度的3/4,或至少留下约50μm的最小厚度。等离子体蚀刻可以是各向异性的、锥形的、各向同性的或其组合。
如图3中所示,然后形成通过装卸器10的减薄部分、由此从腔体12延伸到上表面的贯通孔14。孔14可以使用激光、等离子体蚀刻工艺、等离子体和湿法蚀刻的组合、喷砂工艺或任意类似方法来形成。优选地,以与形成腔体12类似的方式,贯通孔14通过等离子体蚀刻而形成(除了孔14完全通过晶体基板装卸器10的减薄部分延伸)。等离子体硅蚀刻(例如,各向异性的、锥形的、各向同性的或其组合)允许孔剖面的各种形状。优选地,孔14的剖面是锥形的,其中在孔14的腔体侧具有较小的尺寸而在装卸器10的顶面具有较大的尺寸。优选地,最小孔直径约为10μm,且壁相对于与形成孔14所通过的晶体基板的表面垂直的方向的角度介于5°和45°之间,使得孔在其顶面比在其面对腔体12的表面具有更大的剖面尺寸。如图3中所示,装卸器10的所有露出的表面(或至少限定腔体12的表面、孔14的侧壁以及装卸器10的顶面)然后覆盖有绝缘材料层16(即,使用喷涂工艺、PECVD工艺、电化学沉积工艺等进行施加)。在优选的非限制性实施例中,绝缘材料层16可以是利用PECVD工艺施加的最小厚度为100埃的二氧化硅(SiO2)。
如图4中所示,使用旋涂工艺、喷涂工艺、点胶工艺、电化学沉积工艺、层压工艺或任意其他类似方法,腔体12然后被填充以柔性(compliant)电介质材料18。柔性电介质是在所有三个正交方向上呈现柔性且可以适应晶体基板(~2.6 ppm/°C)和铜(~17 ppm/°C)互连之间的热膨胀系数(CTE)失配的相对软的材料(例如,阻焊剂)。柔性电介质材料18优选地是诸如BCB(苯并环丁烯)、阻焊剂、阻焊膜、FR4、模塑料或BT环氧树脂的聚合物。贯通孔20然后通过电介质材料18形成且与孔14对准。孔20可以通过使用用于较大尺寸的孔20的CO2激光(例如约70μm的斑点尺寸)或用于较小尺寸的孔20(例如直径小于50μm)的UV激光(例如,在355nm的波长约20μm的斑点尺寸)形成。可以使用脉冲长度小于140ns的介于10至50kHz之间的激光脉冲频率。优选地,贯通孔20具有10μm的最小直径,且相对于垂直倾斜不大于15度。
贯通孔20的侧壁然后被金属化(即,被金属化层22覆盖)。金属化工艺优选地开始于用于去除涂污在贯通孔20的内壁上的任意树脂(钻通诸如环氧、聚酰亚胺、氰酸酯树脂等电介质材料导致)的除污工艺。该工艺涉及使用γ-丁内酯和水的混合物接触树脂涂污以软化树脂涂污,接着是用碱性高锰酸盐溶液处理以去除软化的树脂以及用水合酸性中和剂处理以中和并去除高锰酸盐残留。在除污处理之后,初始导电金属化层22通过化学镀铜来形成,接着被光刻回蚀,使得金属化层沿着电介质18(在孔20的底部)远离孔20且沿着绝缘层16(在孔14的顶部)远离孔14均延伸短距离(例如,25μm或更长)。通过来自表面粗糙度的固着效果在电镀界面获得粘合。所得结构在图4中示出。
然后,通过在绝缘层16(以及从孔14延伸的金属层22的那些部分)上方且在电介质层18(以及从孔20延伸的金属层22的那些部分)上方沉积金属层(例如,通过金属溅射),在孔组合14/20的两端形成金属接触。然后执行光可成像的抗蚀剂层的沉积,接着是光刻步骤(即,通过掩模的UV曝光以及选择性抗蚀剂层去除),接着是通过光致抗蚀剂去除而露出的那些部分的选择性金属蚀刻以及光致抗蚀剂去除。所得到的结构在图5中示出,其中金属接触24布置在孔14上方且与从其延伸的金属层22电接触,且金属接触26布置在孔20上方且与从其延伸的金属层22电接触。
通过执行一系列交替的绝缘和导电层形成与光刻步骤的组合,金属接触26可以被扩展、扇出或扇入,以创建将电接触26路由到中介层的底面上其所需最终位置的路由层28,如图6中所示。这些路由层还将柔性电介质材料18包封在腔体12中。当完成路由工艺时,外部金属层被电镀以Ni和Au。金属接触24还可以向上扩展有通过金属沉积和光刻蚀刻而形成的附加金属层(例如铜)。然后分别使用焊接合金的丝网印刷工艺或通过植球工艺或通过电镀工艺在金属接触24和26上形成BGA互连30和32。BGA(球栅阵列)互连是通常通过焊接或部分熔融金属球到接合焊盘上形成的用于与对等导体形成物理和电连接的圆形导体。所得到的结构是图7中示出的中介层组件36。
如图8中所示,IC芯片38然后被集成(即,机械附接或安装)到中介层36,其中BGA互连30接触IC芯片38的接合焊盘40且与之形成电连接。集成可以通过使用常规拾放或管芯附接装置来执行。优选地,这在加热环境中执行,使得BGA互连30与金属接触24和接合焊盘40均接合(且在其间形成牢固的电连接)。利用在图8中示出的所得到的结构,IC芯片38的每个接合焊盘40经由BGA互连30、金属接触24、通过孔14/20延伸的金属层22以及金属接触26(通过路由层28延伸)而电连接到中介层36的底部上的BGA互连32中的至少一个。
上面描述且在附图中示出的中介层36及其制造方法具有若干优点。首先,孔14/20和其中的金属层22形成通过中介层传输信号且电耦合BGA互连30到BGA互连32的电互连。其次,避免了形成通过晶体装卸器的长孔,而是形成通过装卸器10的减薄部分的较短孔14。与要求昂贵硅蚀刻装置和处理的形成通过晶体硅的较长孔相比,形成通过电介质18的较长孔20较为容易且要求较不昂贵的装置和处理。第三,绝缘层16和电介质18的组合提供了优越的电绝缘。第四,因为电介质材料18的热和机械特性更好地匹配中介层36将安装到的PCB的热和机械特性,与在中介层主要是通过其整个厚度的晶体硅的情况下相比,机械应力得以减小。第五,电介质材料18附加地提供优越的机械绝缘。
应当理解,本发明不限于上面描述和此处示出的(多个)实施例,而是涵盖落在所附权利要求的范围内的任意和所有变型。例如,此处对于本发明的引用并不旨在限制任意权利要求或权利要求术语的范围,而是相反仅引用可以被一个或多个权利要求覆盖的一个或多个特征。上述的材料、工艺和数值示例仅是示例性的,且不应认为限制了权利要求。而且,从权利要求和说明书显见,并不是所有方法步骤必须以示出或要求保护的确切顺序执行,而是以允许本发明的中介层的适当形成的任意顺序单独或同时执行。单层材料可以形成为这种或类似材料的多层,且反之亦然。尽管通过孔14/20的金属接触的形成被示出且描述为沿着孔14/20的侧壁形成的金属层22,但是它们备选地可以通过使用金属或其他导电材料来完全填充孔14/20而形成。或者,金属材料可以在完全填充孔20的同时沿着孔14的侧壁形成,或反之亦然。
应当注意,如此使用的术语“上方”和“上”均包括性包括“直接位于…上”(没有布置于其间的中间材料、元件或空间)和“间接位于…上”(有布置于其间的中间材料、元件或空间)。同样,术语“相邻”包括“直接相邻”(没有布置于其间的中间材料、元件或空间)和“间接相邻”(有布置于其间的中间材料、元件或空间),“安装到”包括“直接安装到”(没有布置于其间的中间材料、元件或空间)和“间接安装到”(有布置于其间的中间材料、元件或空间),且“电耦合”包括“直接电偶合到”(其间没有把元件电连接在一起的中间材料或元件)和“间接电耦合到”(其间有把元件电连接在一起的中间材料或元件)。例如,“在基板上方”形成元件可以包括直接在基板上形成元件,其间没有中间材料/元件,也可以在基板上间接形成元件,其间具有一个或多个中间材料/元件。
Claims (19)
1.一种中介层,包含:
具有相对的第一和第二表面的晶体基板装卸器,其中在第一表面中形成腔体;
布置在限定腔体的装卸器的表面上的绝缘材料层;
布置在腔体中的柔性电介质材料;以及
多个电互连,每个电互连包含:
通过晶体基板装卸器形成的从第二表面延伸到腔体的第一孔;
通过柔性电介质材料形成以便从第一孔延伸且与第一孔对准的第二孔;
沿着第一孔的侧壁形成的绝缘材料层;以及
通过第一和第二孔延伸的导电材料。
2.根据权利要求1所述的中介层,其中柔性电介质材料包括聚合物。
3.根据权利要求1所述的中介层,其中针对多个电互连中的每一个,第一孔是锥形的,使得第一孔在腔体处比在第二表面处具有更小的剖面尺寸。
4.根据权利要求1所述的中介层,其中针对多个电互连中的每一个,第一孔的侧壁相对于与第一和第二表面垂直的方向在5°和45°之间的方向上延伸。
5.根据权利要求1所述的中介层,其中导电材料包含沿着第一和第二孔的侧壁延伸的金属层。
6.根据权利要求1所述的中介层,其中多个电互连中的每一个还包含:
第一金属接触,布置在第一孔上方,与第二表面绝缘,且电耦合到导电材料;以及
第二金属接触,布置在电介质材料和第二孔上方且电耦合到导电材料,
其中第一金属接触经由通过第一和第二孔延伸的导电材料而电耦合到第二金属接触。
7.根据权利要求6所述的中介层,还包含:
第一多个圆形互连,该第一多个圆形互连中的每个电耦合到第一金属接触之一;以及
第二多个圆形互连,该第二多个圆形互连中的每个电耦合到第二金属接触之一。
8.根据权利要求6所述的中介层,还包含:
布置在第一表面上方和柔性电介质材料上方的一层或多层绝缘材料,其中该一层或多层绝缘材料将柔性材料包封在腔体中,且其中第二金属接触通过该一层或多层绝缘材料延伸。
9.根据权利要求6所述的中介层,还包含:
包括多个接合焊盘的IC器件,其中该IC器件安装在第二表面上方,使得该多个接合焊盘电耦合到第一多个圆形互连。
10.一种形成中介层的方法,包含:
在具有相对的第一和第二表面的晶体基板装卸器中形成腔体,其中在晶体基板装卸器的第一表面中形成腔体;
形成通过晶体基板装卸器从第二表面延伸到腔体的多个第一孔;
在限定腔体的装卸器的表面上和在第一孔的侧壁上形成绝缘材料层;
在腔体中形成柔性电介质材料;
形成通过柔性电介质材料的第二孔,使得第二孔中的每一个从第一孔之一延伸且与之对准;以及
针对从第一孔之一延伸且与之对准的第二孔中的每一个,形成通过一个第一孔和一个第二孔延伸的导电材料。
11.根据权利要求10所述的方法,其中柔性电介质材料包括聚合物。
12.根据权利要求10所述的方法,其中第一孔中的每一个是锥形的,使得第一孔在腔体处比在第二表面处具有更小的剖面尺寸。
13.根据权利要求10所述的方法,其中针对第一孔中的每一个,第一孔的侧壁相对于与第一和第二表面垂直的方向在5°和45°之间的方向上延伸。
14.根据权利要求10所述的方法,其中针对从第一孔之一延伸且与之对准的第二孔中的每一个,还包含:
形成第一金属接触,该第一金属接触布置在第一孔上方、与第二表面绝缘、且电耦合到导电材料;以及
形成第二金属接触,该第二金属接触布置在电介质材料和第二孔上方且电耦合到导电材料,
其中第一金属接触经由通过第一和第二孔延伸的导电材料而电耦合到第二金属接触。
15.根据权利要求14所述的方法,还包含:
形成第一多个圆形互连,所述第一多个圆形互连中的每个电耦合到第一金属接触之一;以及
形成第二多个圆形互连,所述第二多个圆形互连中的每个电耦合到第二金属接触之一。
16.根据权利要求14所述的方法,还包含:
形成布置在第一表面上方和在柔性电介质材料上方的一层或多层绝缘材料,其中该一层或多层绝缘材料将柔性电介质材料包封在腔体中,且其中第二金属接触通过该一层或多层绝缘材料延伸。
17.根据权利要求14所述的方法,还包含:
在第二表面上方安装包括多个接合焊盘的IC器件,使得该多个接合焊盘电耦合到第一多个圆形互连。
18.根据权利要求10所述的方法,其中第二孔的形成利用激光来执行。
19.根据权利要求10所述的方法,其中导电材料的形成利用金属电镀工艺来执行以在第一和第二孔的侧壁上形成金属层。
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CN102347283A (zh) * | 2010-07-23 | 2012-02-08 | 泰塞拉公司 | 具有覆盖过孔的金属垫的微电子元件 |
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US8546951B2 (en) | 2013-10-01 |
KR101354241B1 (ko) | 2014-01-22 |
US20120313255A1 (en) | 2012-12-13 |
TWI533413B (zh) | 2016-05-11 |
US8753925B2 (en) | 2014-06-17 |
KR20120137256A (ko) | 2012-12-20 |
TW201308526A (zh) | 2013-02-16 |
CN102820281B (zh) | 2015-05-13 |
US20140004664A1 (en) | 2014-01-02 |
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