TW202115829A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202115829A
TW202115829A TW109116824A TW109116824A TW202115829A TW 202115829 A TW202115829 A TW 202115829A TW 109116824 A TW109116824 A TW 109116824A TW 109116824 A TW109116824 A TW 109116824A TW 202115829 A TW202115829 A TW 202115829A
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Taiwan
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pattern
active
interlayer insulating
insulating layer
source
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TW109116824A
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English (en)
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TWI786406B (zh
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裵德漢
金盛民
朴柱勳
鄭潤永
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南韓商三星電子股份有限公司
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Abstract

一種半導體裝置包括：基底，包括第一主動區；第一主動圖案，位於第一主動區上；閘極電極，與第一主動圖案交叉且在第一方向上延伸；第一源極/汲極圖案，位於第一主動圖案上，第一源極/汲極圖案相鄰於閘極電極；第一層間絕緣層，覆蓋閘極電極及第一源極/汲極圖案；以及主動接觸件，穿透第一層間絕緣層以電性連接至第一源極/汲極圖案，其中主動接觸件在第一方向上延伸，其中主動接觸件的頂表面包括：第一突起；第二突起；以及位於第一突起與第二突起之間的第一凹部。

Description

半導體裝置
本發明概念的示例性實施例是有關於一種半導體裝置，且更確切而言是有關於一種包括場效電晶體的半導體裝置及其製造方法。
半導體裝置可包括積體電路，積體電路包括金屬氧化物半導體場效電晶體（metal-oxide-semiconductor field effect transistor，MOSFET）。MOSFET是具有源極端子、閘極端子、汲極端子及本體端子的四端子裝置。MOSFET的本體通常會連接至源極端子，從而使MOSFET變成如場效電晶體一樣的三端子裝置。由於半導體裝置的大小及設計規則已減小，因此MOSFET已按比例縮小。半導體裝置的操作特性可能會因MOSFET按比例縮小而劣化。因此，已研究形成具有出色效能的高積體度的半導體裝置的各種方法。
根據本發明概念的示例性實施例，一種半導體裝置包括：基底，包括第一主動區；第一主動圖案，位於所述第一主動區上；閘極電極，與所述第一主動圖案交叉且在第一方向上延伸；第一源極/汲極圖案，位於所述第一主動圖案上，所述第一源極/汲極圖案相鄰於所述閘極電極；第一層間絕緣層，覆蓋所述閘極電極及所述第一源極/汲極圖案；以及主動接觸件，穿透所述第一層間絕緣層以電性連接至所述第一源極/汲極圖案，其中所述主動接觸件在所述第一方向上延伸，其中所述主動接觸件的頂表面包括：第一突起；第二突起；以及位於所述第一突起與所述第二突起之間的第一凹部。
根據本發明概念的示例性實施例，一種半導體裝置包括：基底，包括主動區；主動圖案，位於所述主動區上；閘極電極，與所述主動圖案交叉；源極/汲極圖案，位於所述主動圖案上，所述源極/汲極圖案相鄰於所述閘極電極；層間絕緣層，覆蓋所述閘極電極及所述源極/汲極圖案；以及主動接觸件，穿透所述層間絕緣層，以電性連接至所述源極/汲極圖案，其中所述主動接觸件包括：導電圖案；以及設置於所述導電圖案與所述層間絕緣層之間的障壁圖案，其中所述主動接觸件包括：擴張部分，設置於所述層間絕緣層的上部部分中；以及貫穿部分，自所述擴張部分垂直地延伸至所述源極/汲極圖案，且其中所述障壁圖案是凹陷的，使得所述障壁圖案的最頂端低於所述層間絕緣層的頂表面。
根據本發明概念的示例性實施例，一種半導體裝置包括：基底，包括第一主動區；裝置隔離層，在所述第一主動區上界定第一主動圖案，其中所述裝置隔離層覆蓋所述第一主動圖案的下部部分的側壁，且所述第一主動圖案的上部部分自所述裝置隔離層向上突起；一對第一源極/汲極圖案，位於所述第一主動圖案的所述上部部分中；通道圖案，位於所述第一主動圖案的所述上部部分中以及所述一對第一源極/汲極圖案之間；閘極電極，與所述通道圖案交叉且在第一方向上延伸；閘極間隔件，設置於所述閘極電極的側壁上且在所述第一方向上延伸；閘極介電圖案，設置於所述閘極電極與所述通道圖案之間以及所述閘極電極與所述閘極間隔件之間；閘極頂蓋圖案，設置於所述閘極電極的頂表面上且在所述第一方向上延伸；第一層間絕緣層，位於所述閘極頂蓋圖案上；主動接觸件，穿透所述第一層間絕緣層，以電性連接至所述一對第一源極/汲極圖案中的至少一者；蝕刻停止層，位於所述第一層間絕緣層上，所述蝕刻停止層覆蓋所述主動接觸件的頂表面；第二層間絕緣層，位於所述蝕刻停止層上；內連線，設置於所述第二層間絕緣層中；以及通孔，設置於所述內連線與所述主動接觸件之間，以將所述內連線電性連接至所述主動接觸件，其中所述主動接觸件在所述第一方向上延伸，其中所述主動接觸件的所述頂表面包括：第一突起；第二突起；以及位於所述第一突起與所述第二突起之間的第一凹部。
根據本發明概念的示例性實施例，一種半導體裝置包括：基底，包括第一主動區；第一主動圖案，位於所述第一主動區上；閘極電極，與所述第一主動圖案交叉且在第一方向上延伸；第一源極/汲極圖案，位於所述第一主動圖案上，所述第一源極/汲極圖案相鄰於所述閘極電極；第一層間絕緣層，覆蓋所述閘極電極及所述第一源極/汲極圖案；以及主動接觸件，穿透所述第一層間絕緣層以電性連接至所述第一源極/汲極圖案，其中所述主動接觸件在所述第一方向上延伸，其中所述主動接觸件的頂表面包括低於所述第一層間絕緣層的頂表面的凹部以及位於所述凹部與所述第一源極/汲極圖案之間的空隙。
圖1是圖解說明根據本發明概念的示例性實施例的半導體裝置的平面圖。圖2A、圖2B、圖2C及圖2D是分別沿著圖1所示線A-A’、B-B’、C-C’及D-D’截取的剖視圖。
參考圖1及圖2A至圖2D，可提供包括第一主動區PR及第二主動區NR的基底100。基底100可以是包含矽、鍺或矽鍺的半導體基底，或者可以是化合物半導體基底。在本發明概念的示例性實施例中，基底100可以是矽基底。
在本發明概念的示例性實施例中，第一主動區PR及第二主動區NR可包括於邏輯單元區中，構成半導體裝置的邏輯電路的邏輯電晶體設置於所述邏輯單元區上。舉例而言，構成邏輯電路的邏輯電晶體可設置於基底100的邏輯單元區上。邏輯電晶體中的一些邏輯電晶體可設置於第一主動區PR及第二主動區NR中的每一者上。第一主動區PR可以是p通道金屬氧化物半導體場效電晶體（p-channel metal-oxide-semiconductor field effect transistor，PMOSFET）區，且第二主動區NR可以是n通道金屬氧化物半導體場效電晶體（n-channel metal-oxide-semiconductor field effect transistor，NMOSFET）區。
第一主動區PR及第二主動區NR可由形成於基底100的上部部分中的第二溝渠TR2界定。第二溝渠TR2可設置於第一主動區PR與第二主動區NR之間。第一主動區PR與第二主動區NR彼此可在第一方向D1上被插置於第一主動區PR與第二主動區NR之間的第二溝渠TR2間隔開。第一主動區PR及第二主動區NR中的每一者可在與第一方向D1交叉的第二方向D2上延伸。
第一主動圖案AP1可設置於第一主動區PR上，且第二主動圖案AP2可設置於第二主動區NR上。第一主動圖案AP1及第二主動圖案AP2可在第二方向D2上延伸。第一主動圖案AP1及第二主動圖案AP2可以是基底100的垂直地突起的部分。舉例而言，第一主動圖案AP1及第二主動圖案AP2可自基底100的上部部分垂直地突起。第一溝渠TR1可界定於彼此相鄰的第一主動圖案AP1之間及彼此相鄰的第二主動圖案AP2之間。第一溝渠TR1可較第二溝渠TR2淺。
裝置隔離層ST可填充第一溝渠TR1及第二溝渠TR2。裝置隔離層ST可包括氧化矽層。第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分可自裝置隔離層ST垂直地突起（參見圖2C）。第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分中的每一者可具有鰭形狀。裝置隔離層ST可不覆蓋第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分。裝置隔離層ST可覆蓋第一主動圖案AP1的下部部分的側壁及第二主動圖案AP2的下部部分的側壁。
第一源極/汲極圖案SD1可設置於第一主動圖案AP1的上部部分中。第一源極/汲極圖案SD1可以是具有第一導電類型（例如，P型）的摻雜區。第一通道圖案CH1可設置於一對第一源極/汲極圖案SD1之間。
第二源極/汲極圖案SD2可設置於第二主動圖案AP2的上部部分中。第二源極/汲極圖案SD2可以是具有第二導電類型（例如，N型）的摻雜區。第二通道圖案CH2可設置於一對第二源極/汲極圖案SD2之間。
第一源極/汲極圖案SD1及第二源極/汲極圖案SD2可包括藉由選擇性磊晶生長（selective epitaxial growth，SEG）製程形成的磊晶圖案。在本發明概念的示例性實施例中，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2中的每一者的頂表面可與第一通道圖案CH1及第二通道圖案CH2中的每一者的頂表面設置於實質上相同的水平高度處。
第一源極/汲極圖案SD1可包含晶格常數較基底100的半導體元素的晶格常數大的半導體元素（例如，SiGe）。因此，第一源極/汲極圖案SD1可向第一通道圖案CH1提供壓縮應力。第二源極/汲極圖案SD2可與基底100包含相同的半導體元素（例如，矽）。
閘極電極GE可在第一方向D1上延伸以與第一主動圖案AP1及第二主動圖案AP2交叉。閘極電極GE可以預定的節距排列於第二方向D2上。閘極電極GE可與第一通道圖案CH1及第二通道圖案CH2在垂直方向上交疊。
再次參考圖2C，閘極電極GE可設置於第一通道圖案CH1的第一頂表面TS1及第一通道圖案CH1的至少一個第一側壁SW1上。閘極電極GE可設置於第二通道圖案CH2的第二頂表面TS2及第二通道圖案CH2的至少一個第二側壁SW2上。換言之，根據本實施例的電晶體可以是其中閘極電極GE三維（three-dimensional，3D）地環繞通道CH1及CH2的三維場效電晶體（例如，FinFET）。閘極電極GE可更與設置於第一主動區PR與第二主動區NR之間的第二溝渠TR2交疊。
再次參考圖1及圖2A至圖2D，閘極間隔件GS可設置於閘極電極GE中的每一者的兩個側壁上。閘極間隔件GS可在第一方向D1上沿著閘極電極GE延伸。閘極間隔件GS的頂表面可高於閘極電極GE的頂表面。閘極間隔件GS的頂表面可與將在稍後闡述的第一層間絕緣層110的頂表面共面。閘極間隔件GS可包含SiCN、SiCON或SiN。在本發明概念的示例性實施例中，閘極間隔件GS中的每一者可具有由SiCN、SiCON或SiN中的至少兩者形成的多層結構。
閘極頂蓋圖案GP可設置於閘極電極GE中的每一者上。閘極頂蓋圖案GP可在第一方向D1上沿著閘極電極GE延伸。閘極頂蓋圖案GP可包含相對於將在稍後闡述的第一層間絕緣層110及第二層間絕緣層120具有蝕刻選擇性的材料。舉例而言，閘極頂蓋圖案GP可包含SiON、SiCN、SiCON或SiN。
閘極介電圖案GI可設置於閘極電極GE與第一主動圖案AP1之間以及閘極電極GE與第二主動圖案AP2之間。閘極介電圖案GI可沿著上面設置有閘極介電圖案GI的閘極電極GE的底表面延伸。舉例而言，再次參考圖2C，閘極介電圖案GI可覆蓋第一通道圖案CH1的第一頂表面TS1及第一側壁SW1。閘極介電圖案GI可覆蓋第二通道圖案CH2的第二頂表面TS2及第二側壁SW2。閘極介電圖案GI可覆蓋位於閘極電極GE下方的裝置隔離層ST的頂表面。
在本發明概念的示例性實施例中，閘極介電圖案GI可包含介電常數高於氧化矽的介電常數的高介電常數（high-k）介電材料。舉例而言，高介電常數介電材料可包括氧化鉿、氧化鉿矽、氧化鉿鋯、氧化鉿鉭、氧化鑭、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化鋰、氧化鋁、氧化鉛鈧鉭或鈮酸鉛鋅。
在本發明概念的示例性實施例中，閘極介電圖案GI可包含鐵電材料。包含鐵電材料的閘極介電圖案GI可用作負性電容器。舉例而言，當對鐵電材料施加外部電壓時，由於自初始極性狀態至另一狀態的相變，鐵電材料中的偶極的移動可產生負性電容。在此種情形中，包含鐵電材料的電晶體的總電容可增大，且因此電晶體的次臨限值擺動（sub-threshold swing）特性可改良且電晶體的操作電壓可減小。
閘極介電圖案GI的鐵電材料可包括摻雜有（或含有）鋯（Zr）、矽（Si）、鋁（Al）或鑭（La）的氧化鉿。由於氧化鉿摻雜有預定比率的鋯（Zr）、矽（Si）、鋁（Al）或鑭（La），因此鐵電材料的至少一部分可具有斜方晶體結構。當鐵電材料的至少一部分具有斜方晶體結構時，可產生負性電容。鐵電材料中具有斜方晶體結構的一部分的體積比率可介於10%至50%範圍內。
當鐵電材料包括摻雜鋯的氧化鉿（ZrHfO）時，Zr原子對Zr原子與Hf原子之和的比率（Zr/（Hf+Zr））可介於45原子百分比至55原子百分比範圍內。當鐵電材料包括摻雜矽的氧化鉿（SiHfO）時，Si原子對Si原子與Hf原子之和的比率（Si/（Hf+Si））可介於4原子百分比至6原子百分比範圍內。當鐵電材料包括摻雜鋁的氧化鉿（AlHfO）時，Al原子對Al原子與Hf原子之和的比率（Al/（Hf+Al））可介於5原子百分比至10原子百分比範圍內。當鐵電材料包括摻雜鑭的氧化鉿（LaHfO）時，La原子對La原子與Hf原子之和的比率（La/（Hf+La））可介於5原子百分比至10原子百分比範圍內。
閘極電極GE中的每一者可包括第一金屬圖案及位於所述第一金屬圖案上的第二金屬圖案。第一金屬圖案可設置於閘極介電圖案GI上且可相鄰於第一通道圖案CH1及第二通道圖案CH2。第一金屬圖案可包含用於調整電晶體的臨限值電壓的功函數金屬。可藉由調整第一金屬圖案的厚度及組成物來獲得電晶體的所期望臨限值電壓。
第一金屬圖案可包括金屬氮化物層。舉例而言，第一金屬圖案可包含氮（N）且包含鈦（Ti）、鉭（Ta）、鋁（Al）、鎢（W）及鉬（Mo）中的至少一種。另外，第一金屬圖案可更包含碳（C）。在本發明概念的示例性實施例中，第一金屬圖案可包括多個經堆疊功函數金屬層。
第二金屬圖案可包含電阻低於第一金屬圖案的電阻的金屬。舉例而言，第二金屬圖案可包含鎢（W）、鋁（Al）、鈦（Ti）及鉭（Ta）中的至少一種。
再次參考圖1及圖2A至圖2D，第一層間絕緣層110可設置於基底100上。第一層間絕緣層110可覆蓋閘極間隔件GS以及第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。第一層間絕緣層110的頂表面可與閘極頂蓋圖案GP的頂表面及閘極間隔件GS的頂表面實質上共面。第二層間絕緣層120可設置於第一層間絕緣層110及閘極頂蓋圖案GP上。舉例而言，第一層間絕緣層110及第二層間絕緣層120中的每一者可包括氧化矽層。
主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110以分別電性連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。主動接觸件AC中的每一者可設置於一對閘極電極GE之間。當在圖1中所示的平面圖中進行觀察時，主動接觸件AC可具有在第一方向D1上延伸的棒形狀。
主動接觸件AC可包括導電圖案FM及環繞所述導電圖案FM的障壁圖案BM。舉例而言，導電圖案FM可包含鋁、銅、鎢、鉬或鈷。障壁圖案BM可覆蓋導電圖案FM的底表面及側壁。障壁圖案BM可包括金屬層/金屬氮化物層。所述金屬層可包含鈦、鉭、鎢、鎳、鈷或鉑。所述金屬氮化物層可包括氮化鈦（TiN）層、氮化鉭（TaN）層、氮化鎢（WN）層、氮化鎳（NiN）層、氮化鈷（CoN）層或氮化鉑（PtN）層。
再次參考圖2A，主動接觸件AC可包括：擴張部分EP，設置於第二層間絕緣層120的上部部分中；以及貫穿部分VP，自所述擴張部分EP垂直地延伸至第一源極/汲極圖案SD1或第二源極/汲極圖案SD2。貫穿部分VP可穿透所述一對閘極電極GE之間的第一層間絕緣層110。主動接觸件AC可在主動接觸件AC的中心區中包括在第三方向D3上延伸的至少一個空隙VD。舉例而言，主動接觸件AC可包括在第三方向D3上彼此間隔開的兩個空隙VD。
貫穿部分VP在第二方向D2上的寬度可朝向貫穿部分VP的底表面減小。換言之，貫穿部分VP可具有錐形形狀。擴張部分EP在第二方向D2上的寬度可大於貫穿部分VP在第二方向D2上的最大寬度。
擴張部分EP的頂表面EPt可包括第一突起P1、第二突起P2以及位於第一突起P1與第二突起P2之間的凹部DE。第二突起P2可在第二方向D2上相鄰於第一突起P1。凹部DE可與空隙VD在垂直方向上對齊。換言之，凹部DE可在第三方向D3上與空隙VD對齊。凹部DE可在第一突起P1與第二突起P2之間朝向基底100凹陷。
第一突起P1及第二突起P2可在第三方向D3上突起。第一突起P1的最頂端及第二突起P2的最頂端的水平高度可實質上相同於或低於第二層間絕緣層120的頂表面的水平高度。凹部DE的水平高度可低於第二絕緣層120的頂表面。
主動接觸件AC的擴張部分EP可包括位於障壁圖案BM上的凹槽RS。換言之，障壁圖案BM的上部部分可朝向基底100凹陷。障壁圖案BM的最頂端的水平高度可低於第一突起P1的最頂端及第二突起P2的最頂端的水平高度。障壁圖案BM的最頂端的水平高度可低於凹部DE的水平高度。障壁圖案BM的最頂端的水平高度可低於第二層間絕緣層120的頂表面的水平高度。凹槽RS可暴露出擴張部分EP的上部部分的側壁。
主動接觸件AC可以是自對齊接觸件。換言之，可使用閘極頂蓋圖案GP及閘極間隔件GS將主動接觸件AC形成為自對齊。舉例而言，主動接觸件AC可覆蓋閘極間隔件GS的側壁的至少一部分。主動接觸件AC可覆蓋閘極頂蓋圖案GP的頂表面的一部分。
矽化物圖案SC可分別設置於主動接觸件AC與第一源極/汲極圖案SD1之間以及主動接觸件AC與第二源極/汲極圖案SD2之間。主動接觸件AC可經由矽化物圖案SC電性連接至源極/汲極圖案SD1或SD2。矽化物圖案SC可包含金屬矽化物且可包含例如矽化鈦、矽化鉭、矽化鎢、矽化鎳或矽化鈷中的至少一種。
閘極接觸件GC可穿透第二層間絕緣層120及閘極頂蓋圖案GP以電性連接至閘極電極GE。閘極接觸件GC可設置於位於第一主動區PR與第二主動區NR之間的裝置隔離層ST上。當在圖1中所示的平面圖中進行觀察時，閘極接觸件GC可具有在第二方向D2上延伸的棒形狀。
至少一個閘極接觸件GC可在第二方向D2上延伸以對彼此相鄰的閘極電極GE進行連接。舉例而言，閘極接觸件GC可與一對閘極電極GE交疊。如主動接觸件AC一樣，閘極接觸件GC可包括導電圖案FM及環繞導電圖案FM的障壁圖案BM。
再次參考圖2C，閘極接觸件GC可包括：擴張部分EP，設置於第二層間絕緣層120的上部部分中；以及貫穿部分VP，自擴張部分EP垂直地延伸至閘極電極GE。貫穿部分VP可穿透設置於閘極電極GE上的閘極頂蓋圖案GP。閘極接觸件GC可在閘極接觸件GC的中心區中包括在第三方向D3上延伸的至少一個空隙VD。在閘極接觸件GC中，擴張部分EP在第一方向D1上的寬度可大於貫穿部分VP在第一方向D1上的最大寬度。
閘極接觸件GC的擴張部分EP的頂表面EPt可包括第一突起P1、第二突起P2以及位於第一突起P1與第二突起P2之間的凹部DE。對閘極接觸件GC的擴張部分EP的詳細說明可與上文對主動接觸件AC的擴張部分EP的說明實質上相同或類似。
蝕刻停止層ESL可設置於第二層間絕緣層120上。第三層間絕緣層130可設置於蝕刻停止層ESL上。蝕刻停止層ESL可設置於第二層間絕緣層120與第三層間絕緣層130之間。蝕刻停止層ESL可直接覆蓋主動接觸件AC及閘極接觸件GC中的每一者的擴張部分EP的頂表面EPt。蝕刻停止層ESL可填充主動接觸件AC及閘極接觸件GC中的每一者的凹槽RS。在此種情形中，蝕刻停止層ESL可覆蓋擴張部分EP的上部部分的暴露側壁。蝕刻停止層ESL可直接覆蓋主動接觸件AC及閘極接觸件GC中的每一者的障壁圖案BM的最頂端。
蝕刻停止層ESL可包含相對於第三層間絕緣層130具有蝕刻選擇性的材料。舉例而言，蝕刻停止層ESL可包含SiON、SiCN、SiCON或SiN。
第一金屬層可設置於第三層間絕緣層130中。第一金屬層可包括第一內連線M1、第一通孔V1及第二通孔V2。第一通孔V1及第二通孔V2可設置於第一內連線M1下方。
第一內連線M1可彼此平行地在第二方向D2上延伸。第一內連線M1可排列於第一方向D1上。第一通孔V1可設置於主動接觸件AC與第一內連線M1中的對應第一內連線M1之間以將主動接觸件AC電性連接至第一內連線M1中的對應第一內連線M1。第二通孔V2可設置於閘極接觸件GC與第一內連線M1中的對應第一內連線M1之間以將閘極接觸件GC電性連接至第一內連線M1中的對應第一內連線。
第一通孔V1及第二通孔V2中的每一者可穿透蝕刻停止層ESL且可與擴張部分EP的頂表面EPt直接接觸。舉例而言，第一通孔V1及第二通孔V2中的每一者可覆蓋擴張部分EP的頂表面EPt的第一突起P1、第二突起P2及凹部DE。如上文所述，擴張部分EP的頂表面EPt可具有不平坦輪廓。因此，可增大第一通孔V1或第二通孔V2與擴張部分EP之間的接觸面積。因此，可減小第一通孔V1或第二通孔V2與擴張部分EP之間的電阻，且可改良半導體裝置的電性特性。
舉例而言，第一內連線M1與設置於第一內連線M1下方的第一通孔V1或第二通孔V2可彼此連接成單個一元式本體以構成單個導電結構。換言之，第一內連線M1與第一通孔V1或第二通孔V2可形成在一起。可使用雙鑲嵌製程將第一內連線M1與第一通孔V1或第二通孔V2形成為單個導電結構。可在第三層間絕緣層130上另外設置經堆疊金屬層（例如M2、M3、M4等）。
圖3、圖5、圖7及圖9是圖解說明製造根據本發明概念的示例性實施例的半導體裝置的方法的平面圖。圖4、圖6A、圖8A及圖10A是分別沿著圖3、圖5、圖7及圖9所示線A-A’截取的剖視圖。圖6B、圖8B及圖10B是分別沿著圖5、圖7及圖9所示線B-B’截取的剖視圖。圖8C及圖10C是分別沿著圖7及圖9所示線C-C’截取的剖視圖。圖8D及圖10D是分別沿著圖7及圖9所示線D-D’截取的剖視圖。
參考圖3及圖4，可提供包括第一主動區PR及第二主動區NR的基底100。可將基底100圖案化以形成第一主動圖案AP1及第二主動圖案AP2。第一主動圖案AP1可形成於第一主動區PR上，且第二主動圖案AP2可形成於第二主動區NR上。第一主動圖案AP1及第二主動圖案AP2可沿著第二方向D2在長度方向上延伸。可在第一主動圖案AP1之間以及在第二主動圖案AP2之間形成第一溝渠TR1。第一溝渠TR1可沿著第一方向D1將第一主動圖案AP1彼此隔開，且可沿著第一方向D1將第二主動圖案AP2彼此隔開。可將基底100圖案化以在第一主動區PR與第二主動區NR之間形成第二溝渠TR2。第二溝渠TR2可較第一溝渠TR1深。
可在基底100上形成裝置隔離層ST以填充第一溝渠TR1及第二溝渠TR2。裝置隔離層ST可包含絕緣材料，例如氧化矽層。可使裝置隔離層ST凹陷，直至暴露出第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分為止。因此，第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分可自裝置隔離層ST垂直地突起。換言之，第一主動圖案AP1的上部部分及第二主動圖案AP2的上部部分不被裝置隔離層ST覆蓋。
參考圖5、圖6A及圖6B，犧牲圖案PP可形成為與第一主動圖案AP1及第二主動圖案AP2交叉。犧牲圖案PP可具有在第一方向D1上延伸的線形狀或棒形狀。舉例而言，形成犧牲圖案PP可包括在基底100的整個頂表面上形成犧牲層、在所述犧牲層上形成硬罩幕圖案MA、及使用所述硬罩幕圖案MA作為蝕刻罩幕來將所述犧牲層圖案化。犧牲層可包含多晶矽。
可分別在犧牲圖案PP中的每一者的兩個側壁上形成一對閘極間隔件GS。形成閘極間隔件GS可包括：在基底100的整個頂表面上共形地形成閘極間隔件層及非等向性地蝕刻所述閘極間隔件層。舉例而言，閘極間隔件層可包含SiCN、SiCON或SiN。在本發明概念的示例性實施例中，閘極間隔件層可由包含SiCN、SiCON或SiN的多層形成。
參考圖7及圖8A至圖8D，可在第一主動圖案AP1的上部部分中形成第一源極/汲極圖案SD1。一對第一源極/汲極圖案SD1可形成於犧牲圖案PP中的每一者的兩側處。
舉例而言，可使用硬罩幕圖案MA及閘極間隔件GS作為蝕刻罩幕來蝕刻第一主動圖案AP1的上部部分以形成第一凹槽區RSR1。當對第一主動圖案AP1的上部部分進行蝕刻時，第一主動圖案AP1之間的裝置隔離層ST可凹陷（參見圖8D）。
可藉由使用第一主動圖案AP1的第一凹槽區RSR1的內表面作為晶種層實行選擇性磊晶生長（selective epitaxial growth，SEG）製程來形成第一源極/汲極圖案SD1。由於形成第一源極/汲極圖案SD1，因此第一通道圖案CH1可位於所述一對第一源極/汲極圖案SD1之間。舉例而言，SEG製程可包括化學氣相沈積（chemical vapor deposition，CVD）製程或分子束磊晶（molecular beam epitaxy，MBE）製程。第一源極/汲極圖案SD1可包含晶格常數大於基底100的半導體元素的晶格常數的半導體元素（例如，SiGe）。在本發明概念的示例性實施例中，第一源極/汲極圖案SD1中的每一者可由多個經堆疊半導體層形成。
在本發明概念的示例性實施例中，可在用於形成第一源極/汲極圖案SD1的SEG製程期間將摻雜物原位注入至第一源極/汲極圖案SD1中。在本發明概念的示例性實施例中，可在用於形成第一源極/汲極圖案SD1的SEG製程之後將摻雜物注入或植入至第一源極/汲極圖案SD1中。第一源極/汲極圖案SD1可摻雜有摻雜物以具有第一導電類型（例如，P型）。
可在第二主動圖案AP2的上部部分中形成第二源極/汲極圖案SD2。一對第二源極/汲極圖案SD2可形成於犧牲圖案PP中的每一者的兩側處。
舉例而言，可使用硬罩幕圖案MA及閘極間隔件GS作為蝕刻罩幕來蝕刻第二主動圖案AP2的上部部分以形成第二凹槽區RSR2。可藉由使用第二主動圖案AP2的第二凹槽區RSR2的內表面作為晶種層實行SEG製程來形成第二源極/汲極圖案SD2。由於形成第二源極/汲極圖案SD2，因此第二通道圖案CH2可位於所述一對第二源極/汲極圖案SD2之間。舉例而言，第二源極/汲極圖案SD2可與基底100包含相同的半導體元素（例如，矽）。第二源極/汲極圖案SD2可摻雜有摻雜物以具有第二導電類型（例如，N型）。
可藉由彼此不同的製程依序形成第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。換言之，第一源極/汲極圖案SD1可不與第二源極/汲極圖案SD2同時形成。
參考圖9及圖10A至圖10D，可形成第一層間絕緣層110以覆蓋第一源極/汲極圖案SD1及第二源極/汲極圖案SD2、硬罩幕圖案MA以及閘極間隔件GS。舉例而言，第一層間絕緣層110可包括氧化矽層。
可將第一層間絕緣層110平坦化，直至暴露出犧牲圖案PP的頂表面為止。可使用回蝕製程或化學機械拋光（chemical mechanical polishing，CMP）製程來實行第一層間絕緣層110的平坦化製程。可在平坦化製程期間完全移除硬罩幕圖案MA。因此，第一層間絕緣層110的頂表面可與犧牲圖案PP的頂表面及閘極間隔件GS的頂表面實質上共面。
犧牲圖案PP可分別被閘極電極GE取代。舉例而言，可選擇性地移除暴露的犧牲圖案PP。可藉由移除犧牲圖案PP形成空的空間。可在空的空間中的每一者中形成閘極介電圖案GI、閘極電極GE及閘極頂蓋圖案GP。舉例而言，可依序形成閘極介電圖案GI、閘極電極GE及閘極頂蓋圖案GP。閘極電極GE可包括第一金屬圖案及位於所述第一金屬圖案上的第二金屬圖案。第一金屬圖案可由能夠調整電晶體的臨限值電壓的功函數金屬形成，且第二金屬圖案可由低電阻金屬形成。
再次參考圖1及圖2A至圖2D，可在第一層間絕緣層110上形成第二層間絕緣層120。第二層間絕緣層120可包括氧化矽層。可在第二層間絕緣層120及第一層間絕緣層110中形成主動接觸件AC。主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110以電性連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。閘極接觸件GC可被形成為穿透第二層間絕緣層120及閘極頂蓋圖案GP。閘極接觸件GC可電性連接至閘極電極GE。舉例而言，閘極接觸件GC可穿透閘極頂蓋圖案GP且與閘極電極GE進行接觸。
可在主動接觸件AC、閘極接觸件GC及第二層間絕緣層120上形成蝕刻停止層ESL。可在蝕刻停止層ESL上形成第三層間絕緣層130。可在第三層間絕緣層130中形成第一金屬層。第一金屬層可包括第一內連線M1、第一通孔V1及第二通孔V2。
圖11至圖14是沿著圖1所示線A-A’截取的剖視圖，用以圖解說明根據本發明概念的示例性實施例的形成主動接觸件的方法。在後文中，將參考圖11至圖14詳細地主要闡述形成主動接觸件AC的方法。
參考圖1及圖11，可對第二層間絕緣層120實行圖案化製程，以形成穿透第二層間絕緣層120及第一層間絕緣層110的多個孔HO。孔HO中的每一者可暴露出第一源極/汲極圖案SD1或第二源極/汲極圖案SD2。在本發明概念的示例性實施例中，孔HO可藉由閘極頂蓋圖案GP及閘極間隔件GS自對齊。
另外，可實行用於對孔HO的上部部分進行擴張的圖案化製程，以在孔HO的上部部分中形成擴張孔EHO。可在擴張孔EHO下方形成穿孔VHO。穿孔VHO可穿透第二層間絕緣層120及第一層間絕緣層110且可朝向基底100延伸。穿孔VHO可具有錐形形狀，且擴張孔EHO可在第二方向D2上較穿孔VHO寬。
可對藉由孔HO暴露出的第一源極/汲極圖案SD1及第二源極/汲極圖案SD2實行矽化製程，從而分別在第一源極/汲極圖案SD1及第二源極/汲極圖案SD2上形成矽化物圖案SC。矽化物圖案SC可包含金屬矽化物。
參考圖1及圖12，可在具有孔HO的基底100上共形地形成障壁層BML。障壁層BML可部分地填充孔HO。可在障壁層BML上形成導電層FML。導電層FML可填充孔HO。
可使用原子層沈積（atomic layer deposition，ALD）製程或化學氣相沈積（CVD）製程形成障壁層BML。可使用CVD製程形成導電層FML。由於經由CVD製程共形地形成導電層FML，因此在形成導電層FML期間可在孔HO中形成至少一個空隙VD。
障壁層BML可包括金屬層/金屬氮化物層。所述金屬層可包含鈦、鉭、鎢、鎳、鈷或鉑。所述金屬氮化物層可包括氮化鈦（TiN）層、氮化鉭（TaN）層、氮化鎢（WN）層、氮化鎳（NiN）層、氮化鈷（CoN）層或氮化鉑（PtN）層。導電層FML可包含鋁、銅、鎢、鉬或鈷。
參考圖1及圖13，可對導電層FML及障壁層BML實行平坦化製程，直至暴露出第二層間絕緣層120的頂表面為止。平坦化製程可包括CMP製程。可藉由將導電層FML及障壁層BML平坦化來在孔HO中的每一者中形成導電圖案FM及環繞導電圖案FM的障壁圖案BM。孔HO中的導電圖案FM及障壁圖案BM可構成主動接觸件AC。
即使實行平坦化製程，第二層間絕緣層120上的障壁層BML的一部分仍可能會保留下來以在第二層間絕緣層120上造成橋接圖案BRP。橋接圖案BRP可保留於彼此相鄰的主動接觸件AC之間。橋接圖案BRP可使彼此相鄰的主動接觸件AC電性連接。換言之，橋接圖案BRP可對應於製程缺陷，且橋接圖案BRP可在相鄰的主動接觸件AC之間造成電性短路。
參考圖1及圖14，可在主動接觸件AC上實行用於部分地移除障壁圖案BM的回蝕製程TEB。可藉由回蝕製程TEB完全移除第二層間絕緣層120上的橋接圖案BRP。
可藉由回蝕製程TEB在主動接觸件AC的上部部分中形成凹槽RS。換言之，障壁圖案BM的上部部分可凹陷。凹槽RS可暴露出導電圖案FM的上部部分的側壁。
可藉由回蝕製程TEB在主動接觸件AC的頂表面EPt處形成第一突起P1、第二突起P2以及位於第一突起P1與第二突起P2之間的凹部DE。換言之，亦可在回蝕製程TEB期間部分地蝕刻導電圖案FM的上部部分，且因此主動接觸件AC的頂表面EPt可具有不平坦輪廓。
由於導電圖案FM在其中心區中因CVD製程而具有空隙VD，因此導電圖案FM的中心區可在物理上及在化學上弱於導電圖案FM的邊緣區。因此，導電圖案FM的中心區可在回蝕製程TEB期間更加凹陷，從而形成凹部DE。換言之，空隙VD可使得在導電圖案FM中出現凹部DE。
再次參考圖1及圖2A至圖2D，隨後，可在主動接觸件AC及第二層間絕緣層120上形成蝕刻停止層ESL。蝕刻停止層ESL可覆蓋主動接觸件AC的頂表面EPt。蝕刻停止層ESL可填充凹槽RS。
亦可藉由與上文參考圖11至圖14所述的形成主動接觸件AC的方法類似的方法形成閘極接觸件GC。舉例而言，閘極接觸件GC可與主動接觸件AC同時形成。
圖15及圖16是沿著圖1所示線A-A’截取的剖視圖，用以圖解說明根據本發明概念的示例性實施例的半導體裝置。在本實施例中，為簡單且方便地進行闡釋，與在圖1及圖2A至圖2D的實施例中相同的技術特徵將不再加以贅述。換言之，後文中將主要闡述本實施例與圖1及圖2A至圖2D的實施例之間的差異。
參考圖15，主動接觸件AC的擴張部分EP的頂表面EPt可具有平坦輪廓。擴張部分EP的頂表面EPt可與第二層間絕緣層120的頂表面實質上共面。凹槽RS可暴露出擴張部分EP的上部部分的側壁。凹槽RS可填充有蝕刻停止層ESL。
可藉由利用導電層FML自孔HO（參見圖11及圖12）的下部部分至孔HO的上部部分填充孔HO的方法來形成根據本實施例的主動接觸件AC。因此，主動接觸件AC中可不會形成空隙。
參考圖16，主動接觸件AC的擴張部分EP可不包括凹槽RS。換言之，障壁圖案BM的頂表面可與第二層間絕緣層120的頂表面實質上共面。擴張部分EP的上部部分的側壁可被障壁圖案BM完全覆蓋。
形成根據本實施例的主動接觸件AC可包括實行圖13及圖14所示回蝕製程TEB達足夠短的時間，以僅移除橋接圖案BRP。因此，障壁圖案BM的頂表面可不會凹陷成低於第二層間絕緣層120的頂表面。
圖17A、圖17B、圖17C及圖17D是分別沿著圖1所示線A-A’、B-B’、C-C’及D-D’截取的剖視圖，用以圖解說明根據本發明概念的示例性實施例的半導體裝置。在本實施例中，為簡單且方便地進行闡釋，與在圖1及圖2A至2D的實施例中相同的技術特徵將不再加以贅述。換言之，後文中將主要闡述本實施例與圖1及圖2A至圖2D的實施例之間的差異。
參考圖1及圖17A至圖17D，可提供包括第一主動區PR及第二主動區NR的基底100。裝置隔離層ST可設置於基底100上。裝置隔離層ST可在基底100上界定第一主動圖案AP1及第二主動圖案AP2。第一主動圖案AP1及第二主動圖案AP2可分別位於第一主動區PR及第二主動區NR上。
第一主動圖案AP1可包括在垂直方向上堆疊的第一通道圖案CH1。經堆疊第一通道圖案CH1可在第三方向D3上彼此間隔開。經堆疊第一通道圖案CH1可在垂直方向上彼此交疊。第二主動圖案AP2可包括在垂直方向上堆疊的第二通道圖案CH2。經堆疊第二通道圖案CH2可在第三方向D3上彼此間隔開。經堆疊第二通道圖案CH2可在垂直方向上彼此交疊。第一通道圖案CH1及第二通道圖案CH2可包含矽（Si）、鍺（Ge）或矽鍺（SiGe）。
第一主動圖案AP1可更包括第一源極/汲極圖案SD1。經堆疊第一通道圖案CH1可設置於彼此相鄰的一對第一源極/汲極圖案SD1之間。經堆疊第一通道圖案CH1可對彼此相鄰的所述一對第一源極/汲極圖案SD1進行連接。
第二主動圖案AP2可更包括第二源極/汲極圖案SD2。經堆疊第二通道圖案CH2可設置於彼此相鄰的一對第二源極/汲極圖案SD2之間。經堆疊第二通道圖案CH2可對彼此相鄰的所述一對第二源極/汲極圖案SD2進行連接。
閘極電極GE可在第一方向D1上延伸以與第一通道圖案CH1及第二通道圖案CH2交叉。閘極電極GE可與第一通道圖案CH1及第二通道圖案CH2在垂直方向上交疊。一對閘極間隔件GS可分別設置於閘極電極GE的兩個側壁上。閘極頂蓋圖案GP可設置於閘極電極GE上。
再次參考圖17C，閘極電極GE可環繞第一通道圖案CH1及第二通道圖案CH2中的每一者。閘極電極GE可設置於第一通道圖案CH1的第一頂表面TS1、至少一個第一側壁SW1及第一底表面BS1上。閘極電極GE可設置於最低的第一通道圖案CH1與第一主動圖案AP1的頂部之間。閘極電極GE可設置於第二通道圖案CH2的第二頂表面TS2、至少一個第二側壁SW2及第二底表面BS2上。閘極電極GE可設置於最低的第二通道圖案CH2與第二主動圖案AP2的頂部之間。換言之，閘極電極GE可環繞第一通道圖案CH1及第二通道圖案CH2中的每一者的頂表面、底表面及兩個側壁。根據本實施例的電晶體可以是其中閘極電極GE三維地環繞通道CH1及CH2的3D場效電晶體（例如，多橋通道FET（multibridge channel FET，MBCFET））。
再次參考圖1及圖17A至圖17D，閘極介電圖案GI可設置於閘極電極GE與第一通道圖案CH1及第二通道圖案CH2中的每一者之間。閘極介電圖案GI可環繞第一通道圖案CH1及第二通道圖案CH2中的每一者。
絕緣圖案IP可在第二主動區NR上設置於閘極介電圖案GI與第二源極/汲極圖案SD2之間。閘極電極GE與第二源極/汲極圖案SD2可藉由閘極介電圖案GI及絕緣圖案IP間隔開。絕緣圖案IP可不位於第一主動區PR上。
第一層間絕緣層110及第二層間絕緣層120可設置於基底100的整個頂表面上。主動接觸件AC可穿透第二層間絕緣層120及第一層間絕緣層110以分別連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。閘極接觸件GC可穿透第二層間絕緣層120及閘極頂蓋圖案GP以電性連接至閘極電極GE。如上文參考圖1及圖2A至圖2D所述，主動接觸件AC與閘極接觸件GC可實質上相同。
蝕刻停止層ESL及第三層間絕緣層130可依序設置於第二層間絕緣層120上。第一金屬層可設置於第三層間絕緣層130中。第一金屬層可包括第一內連線M1、第一通孔V1及第二通孔V2。
根據本發明概念的上述示例性實施例，可完全移除可造成主動接觸件之間的短路的橋接圖案以改良半導體裝置的可靠性及電性特性。根據本發明概念的上述示例性實施例，主動接觸件的頂表面可具有不平坦輪廓，且因此可增大通孔與主動接觸件之間的接觸面積。因此，可減小通孔與主動接觸件之間的電阻，且可改良半導體裝置的電性特性。
雖然已參考本發明概念的示例性實施例闡述了本發明概念，但熟習此項技術者應明瞭，可在不背離申請專利範圍中所陳述的本發明概念的精神及範疇的情況下對本發明概念做出各種改變及潤飾。
100:基底 110:第一層間絕緣層 120:第二層間絕緣層/第二絕緣層 130:第三層間絕緣層 A-A’、B-B’、C-C’、D-D’:線 AC:主動接觸件 AP1:第一主動圖案 AP2:第二主動圖案 BM:障壁圖案 BML:障壁層 BS1:第一底表面 BS2:第二底表面 BRP:橋接圖案 CH1:第一通道圖案/通道 CH2:第二通道圖案/通道 D1:第一方向 D2:第二方向 D3:第三方向 DE:凹部 EHO:擴張孔 EP:擴張部分 EPt:頂表面 ESL:蝕刻停止層 FM:導電圖案 FML:導電層 GC:閘極接觸件 GE:閘極電極 GI:閘極介電圖案 GP:閘極頂蓋圖案 GS:閘極間隔件 HO:孔 IP:絕緣圖案 M1:第一內連線 MA:硬罩幕圖案 NR:第二主動區 P1:第一突起 P2:第二突起 PP:犧牲圖案 PR:第一主動區 RS:凹槽 RSR1:第一凹槽區 RSR2:第二凹槽區 SC:矽化物圖案 SD1:第一源極/汲極圖案/源極/汲極圖案 SD2:第二源極/汲極圖案/源極/汲極圖案 ST:裝置隔離層 SW1:第一側壁 SW2:第二側壁 TEB:回蝕製程 TS1:第一頂表面 TS2:第二頂表面 TR1:第一溝渠 TR2:第二溝渠 V1:第一通孔 V2:第二通孔 VD:空隙 VHO:穿孔 VP:貫穿部分
參照附圖及隨附詳細說明將更明瞭本發明概念的示例性實施例。 圖1是圖解說明根據本發明概念的示例性實施例的半導體裝置的平面圖。 圖2A、圖2B、圖2C及圖2D是分別沿著圖1所示線A-A’、B-B’、C-C’及D-D’截取的剖視圖。 圖3、圖5、圖7及圖9是圖解說明製造根據本發明概念的示例性實施例的半導體裝置的方法的平面圖。 圖4、圖6A、圖8A及圖10A是分別沿著圖3、圖5、圖7及圖9所示線A-A’截取的剖視圖。 圖6B、圖8B及圖10B是分別沿著圖5、圖7及圖9所示線B-B’截取的剖視圖。 圖8C及圖10C是分別沿著圖7及圖9所示線C-C’截取的剖視圖。 圖8D及圖10D是分別沿著圖7及圖9所示線D-D’截取的剖視圖。 圖11、圖12、圖13及圖14是沿著圖1所示線A-A’截取的剖視圖，用以圖解說明形成根據本發明概念的示例性實施例的主動接觸件的方法。 圖15及圖16是沿著圖1所示線A-A’截取的剖視圖，用以圖解說明根據本發明概念的示例性實施例的半導體裝置。 圖17A、圖17B、圖17C及圖17D是分別沿著圖1所示線A-A’、B-B’、C-C’及D-D’截取的剖視圖，用以圖解說明根據本發明概念的示例性實施例的半導體裝置。
100:基底
A-A’、B-B’、C-C’、D-D’:線
AC:主動接觸件
AP1:第一主動圖案
AP2:第二主動圖案
D1:第一方向
D2:第二方向
D3:第三方向
GC:閘極接觸件
GE:閘極電極
NR:第二主動區
PR:第一主動區
SD1:第一源極/汲極圖案/源極/汲極圖案
SD2:第二源極/汲極圖案/源極/汲極圖案

Claims (20)

  1. 一種半導體裝置，包括： 基底，包括第一主動區； 第一主動圖案，位於所述第一主動區上； 閘極電極，與所述第一主動圖案交叉且在第一方向上延伸； 第一源極/汲極圖案，位於所述第一主動圖案上，所述第一源極/汲極圖案相鄰於所述閘極電極； 第一層間絕緣層，覆蓋所述閘極電極及所述第一源極/汲極圖案；以及 主動接觸件，穿透所述第一層間絕緣層以電性連接至所述第一源極/汲極圖案， 其中所述主動接觸件在所述第一方向上延伸； 其中所述主動接觸件的頂表面包括：第一突起；第二突起；以及位於所述第一突起與所述第二突起之間的第一凹部。
  2. 如請求項1所述的半導體裝置，其中所述主動接觸件包括：導電圖案；以及設置於所述導電圖案與所述第一層間絕緣層之間的障壁圖案，且 其中所述障壁圖案是凹陷的，使得所述障壁圖案的最頂端低於所述第一層間絕緣層的頂表面。
  3. 如請求項2所述的半導體裝置，其中所述障壁圖案的所述最頂端低於所述第一凹部。
  4. 如請求項2所述的半導體裝置，其中所述主動接觸件包括：擴張部分，設置於所述第一層間絕緣層的上部部分中；以及貫穿部分，自所述擴張部分垂直地延伸至所述第一源極/汲極圖案，且 其中所述擴張部分在第二方向上的寬度大於所述貫穿部分在所述第二方向上的最大寬度，其中所述第二方向與所述第一方向交叉。
  5. 如請求項1所述的半導體裝置，其中所述第一突起的最頂端及所述第二突起的最頂端實質上相同於或低於所述第一層間絕緣層的頂表面。
  6. 如請求項1所述的半導體裝置，其中所述主動接觸件包括空隙，且 其中所述第一凹部與所述空隙在垂直方向上對齊。
  7. 如請求項1所述的半導體裝置，更包括： 第二主動圖案，位於所述基底的第二主動區上；以及 第二源極/汲極圖案，位於所述第二主動圖案上， 其中所述第二源極/汲極圖案相鄰於所述閘極電極， 其中所述第一主動區是p通道金屬氧化物半導體場效電晶體（PMOSFET）區，且 其中所述第二主動區是n通道金屬氧化物半導體場效電晶體（NMOSFET）區。
  8. 如請求項1所述的半導體裝置，更包括： 蝕刻停止層，位於所述第一層間絕緣層上， 其中所述蝕刻停止層覆蓋所述主動接觸件的所述頂表面。
  9. 如請求項8所述的半導體裝置，更包括： 第二層間絕緣層，位於所述蝕刻停止層上； 第一內連線，設置於所述第二層間絕緣層中；以及 第一通孔，設置於所述第一內連線與所述主動接觸件之間，以將所述第一內連線電性連接至所述主動接觸件。
  10. 如請求項1所述的半導體裝置，更包括： 閘極接觸件，穿透所述第一層間絕緣層，以電性連接至所述閘極電極， 其中所述閘極接觸件在第二方向上延伸，且 其中所述閘極接觸件的頂表面包括：第三突起；第四突起；以及位於所述第三突起與所述第四突起之間的第二凹部。
  11. 一種半導體裝置，包括： 基底，包括主動區； 主動圖案，位於所述主動區上； 閘極電極，與所述主動圖案交叉； 源極/汲極圖案，位於所述主動圖案上，所述源極/汲極圖案相鄰於所述閘極電極； 層間絕緣層，覆蓋所述閘極電極及所述源極/汲極圖案；以及 主動接觸件，穿透所述層間絕緣層，以電性連接至所述源極/汲極圖案， 其中所述主動接觸件包括：導電圖案；以及設置於所述導電圖案與所述層間絕緣層之間的障壁圖案， 其中所述主動接觸件包括：擴張部分，設置於所述層間絕緣層的上部部分中；以及貫穿部分，自所述擴張部分垂直地延伸至所述源極/汲極圖案，且 其中所述障壁圖案是凹陷的，使得所述障壁圖案的最頂端低於所述層間絕緣層的頂表面。
  12. 如請求項11所述的半導體裝置，其中所述閘極電極在第一方向上延伸， 其中所述閘極接觸件在所述第一方向上延伸， 其中所述擴張部分的頂表面包括：第一突起；第二突起；以及位於所述第一突起與所述第二突起之間的凹部。
  13. 如請求項12所述的半導體裝置，其中所述障壁圖案的所述最頂端低於所述凹部。
  14. 如請求項12所述的半導體裝置，其中所述主動接觸件包括空隙，且 其中所述凹部與所述空隙在垂直方向上對齊。
  15. 如請求項11所述的半導體裝置，更包括： 蝕刻停止層，位於所述層間絕緣層上， 其中所述蝕刻停止層覆蓋所述擴張部分的頂表面，且 其中所述蝕刻停止層填充所述凹槽。
  16. 一種半導體裝置，包括： 基底，包括第一主動區； 裝置隔離層，在所述第一主動區上界定第一主動圖案，其中所述裝置隔離層覆蓋所述第一主動圖案的下部部分的側壁，且所述第一主動圖案的上部部分自所述裝置隔離層向上突起； 一對第一源極/汲極圖案，位於所述第一主動圖案的所述上部部分中； 通道圖案，位於所述第一主動圖案的所述上部部分中以及所述一對第一源極/汲極圖案之間； 閘極電極，與所述通道圖案交叉且在第一方向上延伸； 閘極間隔件，設置於所述閘極電極的側壁上且在所述第一方向上延伸； 閘極介電圖案，設置於所述閘極電極與所述通道圖案之間以及所述閘極電極與所述閘極間隔件之間； 閘極頂蓋圖案，設置於所述閘極電極的頂表面上且在所述第一方向上延伸； 第一層間絕緣層，位於所述閘極頂蓋圖案上； 主動接觸件，穿透所述第一層間絕緣層，以電性連接至所述一對第一源極/汲極圖案中的至少一者； 蝕刻停止層，位於所述第一層間絕緣層上，所述蝕刻停止層覆蓋所述主動接觸件的頂表面； 第二層間絕緣層，位於所述蝕刻停止層上； 內連線，設置於所述第二層間絕緣層中；以及 通孔，設置於所述內連線與所述主動接觸件之間，以將所述內連線電性連接至所述主動接觸件， 其中所述主動接觸件在所述第一方向上延伸， 其中所述主動接觸件的所述頂表面包括：第一突起；第二突起；以及位於所述第一突起與所述第二突起之間的第一凹部。
  17. 如請求項16所述的半導體裝置，更包括： 第二主動圖案，位於所述基底的第二主動區上；以及 第二源極/汲極圖案，位於所述第二主動圖案上， 其中所述第二源極/汲極圖案相鄰於所述閘極電極， 其中所述第一主動區是p通道金屬氧化物半導體場效電晶體（PMOSFET）區，且 其中所述第二主動區是p通道金屬氧化物半導體場效電晶體（NMOSFET）區。
  18. 如請求項16所述的半導體裝置，其中所述主動接觸件包括：導電圖案；以及設置於所述導電圖案與所述第一層間絕緣層之間的障壁圖案，且 其中所述障壁圖案是凹陷的，使得所述障壁圖案的最頂端低於所述第一層間絕緣層的頂表面。
  19. 如請求項18所述的半導體裝置，其中所述主動接觸件包括：擴張部分，設置於所述第一層間絕緣層的上部部分中；以及貫穿部分，自所述擴張部分垂直地延伸至所述一對第一源極/汲極圖案中的所述至少一者，且 其中所述擴張部分在第二方向上的寬度大於所述貫穿部分在所述第二方向上的最大寬度，其中所述第二方向與所述第一方向交叉。
  20. 如請求項16所述的半導體裝置，更包括： 閘極接觸件，穿透所述第一層間絕緣層及所述閘極頂蓋圖案，以電性連接至所述閘極電極， 其中所述閘極接觸件在與所述第一方向交叉的第二方向上延伸，且 其中所述閘極接觸件的頂表面包括：第三突起；第四突起；以及位於所述第三突起與所述第四突起之間的第二凹部。
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