TW202018829A - 封裝方法及封裝結構 - Google Patents
封裝方法及封裝結構 Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims description 74
- 238000012858 packaging process Methods 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 205
- 239000002184 metal Substances 0.000 claims abstract description 205
- 238000000034 method Methods 0.000 claims description 55
- 238000005553 drilling Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000002470 thermal conductor Substances 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 8
- 238000009826 distribution Methods 0.000 abstract description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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Abstract
本案係提供一種封裝方法及封裝結構,首先,提供半封裝單元,半封裝單元包含嵌於絕緣結構內之電子元件、導熱結構、第一金屬層及第二金屬層,第一金屬層係貼附於電子元件,第二金屬層係貼附於導熱結構,接著,移除部分的絕緣結構以形成設置於半封裝單元之邊緣處之至少一凹部,並移除部分的絕緣結構使得於半封裝單元之一側形成複數個第一開孔,以暴露出第一金屬層及第二金屬層,接著,形成一第一金屬重佈線層以連接絕緣結構、第一金屬層及第二金屬層,接著,於第一金屬重佈線層上形成複數個第二開孔,並於複數個第二開孔上形成第一遮罩。
Description
本案係關於一種封裝方法及封裝結構,尤指一種電子元件具有可潤濕側翼結構(wettable flank structure)的封裝方法及封裝結構。
近年來,電子裝置設計朝向小尺寸、輕薄及易於攜帶之趨勢發展。再者,隨著電子工業技術之日益進步,電子裝置之內部電路已逐漸朝向模組化發展,換言之,複數個電子元件係整合在單一電子模組中。舉例而言,功率模組(power module)為廣泛使用的電子模組之一,功率模組可包括例如但不限於直流-直流轉換器(DC to DC converter)、直流-交流轉換器(DC to AC converter)或交流-直流轉換器(AC to DC converter)。於複數個電子元件(例如積體電路晶片、電容器、電阻器、電感器、變壓器、二極體及電晶體)整合為一功率模組之後,功率模組便可安裝於主機板或系統電路板上。
目前,方形扁平無引腳 (quad flat no leads, QFN) 封裝結構是一種非常普及的嵌入式結構,而該封裝結構的導線架係從該封裝結構的底部及側邊暴露出來,此外,方形扁平無引腳封裝結構不會從不同側邊伸出引腳,且因具有較小的體積、較低的成本、較高的製作過程良率及較好的散熱效果等優勢,而廣泛的被應用。
然而,傳統方形扁平無引腳封裝結構的底部係以電鍍方式而經由焊料與印刷電路板相連接,傳統方形扁平無引腳封裝結構之導線架被切割而在方形扁平無引腳封裝結構的側翼暴露出導線架的表面,使得方形扁平無引腳封裝結構的側翼表面無法被電鍍,因此,方形扁平無引腳封裝結構的側翼沒有被電鍍而難以鍍上焊料。此外,未被電鍍之方形扁平無引腳封裝結構的側翼表面容易被氧化。更甚者,連接於方形扁平無引腳封裝結構的導線架及印刷電路板之間的焊料,容易造成突出於印刷電路板表面的突起物,而該突起物使得自動光學檢測難以實施。
因此,實有必要提供一種改良之封裝方法及封裝結構,以解決上述先前技術所面臨之問題。
本案之目的在於提供一種封裝方法及封裝結構,其中該封裝結構具有可潤濕側翼,而封裝結構的可潤濕側翼係容易鍍上導電材料,且能使焊腳的結構位於功率模組的側壁,以達成自動光學檢測。
本案實施例之構想在於提供一種封裝方法,首先,提供半封裝單元,半封裝單元包含嵌於絕緣結構內之電子元件、導熱結構、第一金屬層及第二金屬層,第一金屬層係貼附於電子元件,第二金屬層係貼附於導熱結構。接著,移除部分的絕緣結構以於半封裝單元之邊緣處形成至少一凹部,並於半封裝單元之一側形成複數個第一開孔,以暴露出第一金屬層及第二金屬層。接著,於絕緣結構上形成一第一金屬重佈線層以連接第一金屬層及第二金屬層。接著,於第一金屬重佈線層上形成複數個第二開孔,並於複數個第二開孔上形成第一遮罩。
本案實施例另一構想在於提供一種封裝結構,係包含電子元件、導熱結構、第一金屬層、第二金屬層、絕緣結構及第一金屬重佈線層。第一金屬層係貼附於電子元件。導熱結構設於電子元件之一側。第二金屬層係貼附於導熱結構。絕緣結構包含凹陷處及複數個第一開孔,其中電子元件、導熱結構、第一金屬層及第二金屬層係嵌入於絕緣結構中,且凹陷處係設於絕緣結構之邊緣。第一金屬重佈線層係經由凹陷處連接導熱結構及第二金屬層的一側,並經由複數個第一開孔連接第一金屬層及第二金屬層的另一側。
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非架構於限制本案。
第1A至1X圖為本案之第一實施例之電子元件之封裝方法之截面結構示意圖。
首先,如第1A圖所示,提供至少一導熱結構11,第一凹槽111形成於對應的導熱結構11之一側,尤其是形成於對應的導熱結構11之一邊緣處。在一實施例中,第一凹槽111係利用化學蝕刻方法形成。然後,如第1B圖所示,提供第一載體12及電子元件13。在一實施例中,第一載體12係為散熱膠帶或聚醯亞胺(polyimide)膠帶。電子元件13之一側包含至少一第一導接端131及至少一第二導接端132。在一些實施例中,導熱結構11可由金屬導線架構成。在一些實施例中,導熱結構11可由具有良好導熱特性的印刷電路板或陶瓷基板(ceramic substrate)構成。在一些實施例中,第一導接端131及第二導接端132是以銅、鋁、銀、金或任何其他適當的金屬材料所構成。
電子元件13可為主動元件或是被動元件,例如但不限於積體電路(Integrated Circuit,IC)晶片、整合性功率元件、金屬氧化物半導體場效電晶體(MOSFET)、高電子遷移率電晶體(HEMT)、絕緣閘雙極性電晶體(Insulated-gate bipolar transistor,IGBT)、二極體(Diode)、電容器、電阻器、電感器或保險絲。電子元件13之第一導接端131及第二導接端132之數目可依據電子元件13之種類及架構而定,例如第1B圖所示,電子元件13示例可為積體電路晶片,根據該積體電路晶片之架構,電子元件13具有一個第一導接端131及兩個第二導接端132。在一實施例中,電子元件13為功率積體電路晶片,而第一導接端131為閘極端(gate),第二導接端132為源極(Source)端與汲極(Drain)端。
請再參閱第1B圖,導熱結構11及電子元件13之另一側係貼附於第一載體12,因此,使得導熱結構11之第一凹槽111、電子元件13之第一導接端131及第二導接端132係暴露出來。此外,導熱結構11之第一凹槽111係設置於導熱結構11遠離電子元件13之一邊緣處或在導熱結構11內。
然後,如第1C圖所示,提供第一絕緣層141,並將第一絕緣層141層壓於導熱結構11之一側及電子元件13之一側,使導熱結構11及電子元件13嵌於第一絕緣層141上,換言之,導熱結構11之第一凹槽111、電子元件13之第一導接端131及第二導接端132被第一絕緣層141所覆蓋。在一實施例中,第一絕緣層141可由例如但不限於樹脂或任何其他適當的絕緣材料所構成。
接著,如第1D圖所示,第一載體12被移除,因此,電子元件13之另一側及導熱結構11之另一側被暴露出來。接著,如第1E圖所示,部分的導熱結構11被移除, 因此,第二凹槽112形成於對應的導熱結構11之另一側,尤其是形成於對應的導熱結構11之另一邊緣處。在一實施例中,第二凹槽112係利用化學蝕刻方法形成。第一凹槽111及對應的第二凹槽112組成而形成導熱結構11上的一尖銳結構。
接著,如第1F圖所示,提供第一金屬層151及第二金屬層152,第一金屬層151係形成於電子元件13之另一側,第二金屬層152係形成於導熱結構11之另一側。
接著,如第1G圖所示,提供第二絕緣層142,而第二絕緣層142係形成以覆蓋第一金屬層151及第二金屬層152。此外,第一絕緣層141及第二絕緣層142可形成一絕緣結構14。更甚者,絕緣結構14、電子元件13、導熱結構11、第一金屬層151及第二金屬層152形成一半封裝單元100。在一實施例中,第二絕緣層142可由例如但不限於樹脂或任何其他具有適當結構強度與熱導性之適當絕緣材料所構成。
接著,如第1H圖所示,複數個第三開孔143形成於半封裝單元100之一側,而複數個第三開孔143係對應於導熱結構11、第一導接端131及第二導接端132設置。部分的導熱結構11、電子元件13之第一導接端131及第二導接端132係經由對應的第三開孔143所暴露出來。在一實施例中,部分的第一絕緣層141利用雷射鑽孔製程或化學蝕刻製程移除以形成複數個第三開孔143。
接著,如第1I圖所示,提供第二金屬重佈線層16,第二金屬重佈線層16係形成於絕緣結構14之第一絕緣層141上。第二金屬重佈線層16係經由對應的第三開孔143連接導熱結構11、電子元件13之第一導接端131及第二導接端132。
接著,如第1J圖所示,提供第二載體17,而第二載體17係貼附於第二金屬重佈線層16上。
接著,如第1K圖所示,移除部分的絕緣結構14,使得絕緣結構14之邊緣處形成一凹陷處,並定義絕緣結構14之凹陷處為一凹部181,而凹部181係設置於半封裝單元100之邊緣處。於一實施例中,凹部181係利用切割製程而形成,而凹部181的深度H可為但不限為100μm。
接著,如第1L圖所示,移除部分的絕緣結構14,例如部分的第二第二絕緣層142,以形成複數個第一開孔182,而複數個第一開孔182係設置於半封裝單元100的一側,因此部分的第一金屬層151及部分的第二金屬層152係經由對應的第一開孔182而暴露。在一實施例中,部分的第二絕緣層142係利用雷射鑽孔製程或化學蝕刻製程移除。
接著,如第1M圖所示,移除第二載體17,而使得第二金屬重佈線層16暴露出來。
接著,如第1N圖所示,提供第三金屬層191,而第三金屬層191係形成於第二絕緣層142上,因此第三金屬層191係貼附於凹部181,並經由對應的第一開孔182而貼附於第一金屬層151及第二金屬層152。
接著,如第1O圖所示,提供至少一第一薄膜201,而第一薄膜201係形成在部分的第三金屬層191上。在一實施例中,第一薄膜201係形成在對應於電子元件13及導熱結構11之間的區域的部分第三金屬層191上。
接著,如第1P圖所示,提供第一金屬重佈線層21,而第一金屬重佈線層21係形成以覆蓋在第三金屬層191上。第一金屬重佈線層21經由第三金屬層191連接絕緣結構14、第一金屬層151及第二金屬層152。
接著,如第1Q圖所示,移除第一薄膜201,使得複數個第二開孔211形成於第一金屬重佈線層21上。
接著,如第1R圖所示,提供第一遮罩22,而第一遮罩22形成於對應的第二開孔211上,使得第一遮罩22的位置係用以隔離連接第一金屬層151的第一金屬重佈線層21及連接第二金屬層152的第一金屬重佈線層21。在一實施例中,第一遮罩22係為樹脂或任何具有適當絕緣性質的材料。
接著,如第1S圖所示,提供複數個第四開孔161,而複數個第四開孔161係形成在第二金屬重佈線層16上,使得部分的第一絕緣層141暴露出來。
接著,如第1T圖所示,提供第二遮罩23,而第二遮罩23形成在第二金屬重佈線層16上。複數個第五開孔231係形成在第二遮罩23上,使得連接導熱結構11的部分的第二金屬重佈線層16及連接電子元件13之第二導接端132的第二金屬重佈線層16係經由對應的第五開孔231暴露出來。在一實施例中,第二遮罩23係為樹脂或任何具有適當絕緣性質的材料。
接著,如第1U圖所示,提供第三金屬重佈線層24,而第三金屬重佈線層24形成在第二遮罩23上,並經由對應的第五開孔231接觸與導熱結構11相連接的第二金屬重佈線層16及與電子元件13之第二導接端132相連接的第二金屬重佈線層16。
接著,如第1V圖所示,提供第三遮罩25,而第三遮罩25形成在第三金屬重佈線層24上,而複數個第六開孔251係形成在第三遮罩25上。此外,第三金屬重佈線層24係經由第六開孔251暴露出來,而第三金屬重佈線層24係與導熱結構11連接之第二金屬重佈線層16相連接。於一實施例中,第三遮罩25係為樹脂或任何具有適當絕緣性質的材料。
接著,如第1W圖所示,複數個嵌入式結構被分離,而製造出具有嵌入式封裝結構之電源模組2。
接著,如第1X圖所示,將電源模組2設置於電路板26上,而電源模組2之第一金屬重佈線層21經由導電材料27,例如焊料,與電路板26相連接,而使得導電材料27形成焊腳,故焊腳係形成電源模組2之可潤濕側翼結構。經由第一金屬重佈線層21與第一金屬層151相連接之導電材料27及經由第一金屬重佈線層21與第二金屬層152相連接之導電材料27被相對應的第一遮罩22分離。在一實施例中,複數個有色光束,例如紅光R、綠光G及藍光B,利用不同角度以照射導電材料27的斜面,而一自動光學檢測系統(未圖示)設置在電源模組2上方以接收自導電材料27表面所反射出的複數個有色光束,並根據所接收到的光束的分布狀態,進而得知導電材料27的斜率,藉以避免不良的填充品質。在一實施例中,導電層28係設置於電源模組2上。
在一些實施例中,本案之封裝方法所揭露之第1K圖至第1X圖可替換為不同的封裝方法。第2A圖至第2N圖為本案之第二實施例之電子元件之部分封裝方法之截面結構示意圖。於一實施例中,本案之封裝方法所揭露之第1K圖至第1X圖可替換為第2A圖至第2N圖之封裝方法,而封裝方法的組成部分及元件相似於前述第一實施例的封裝方法的組成部分及元件,其中相同元件符號代表相同的元件,於此不再贅述。
於實施第1A圖至第1J圖的封裝方法後,如第2A圖所示,移除部分的絕緣結構14。結緣結構14之一側、導熱結構11之第二凹槽112及第二金屬層152的一側係定義為凹部181,而凹部181係設置於半封裝單元100的邊緣處,而部分的導熱結構11及部分的第二金屬層152經由對應的凹部181暴露出來。
於實施第2A圖的封裝方法後,再實施第2B圖至第2N圖的封裝方法,而第2B圖至第2N圖的步驟相似於第1L圖至第1X圖的步驟,故於此不再贅述。
在一些實施例中,本案之封裝方法所揭露之第1I圖至第1S圖可替換為不同的封裝方法。第3A圖至第3F圖為本案之第三實施例之電子元件之部分封裝方法之截面結構示意圖。於一實施例中,本案之封裝方法所揭露之第1I圖至第1S圖可替換為第3A圖至第3F圖之封裝方法,而封裝方法的組成部分及元件相似於前述第一實施例的封裝方法的組成部分及元件,其中相同元件符號代表相同的元件,於此不再贅述。
於實施第1A圖至第1H圖的封裝方法後,如第3A圖所示,移除部分的絕緣結構14,而絕緣結構14的邊緣處形成凹陷處,導熱結構11的一側、絕緣結構14的凹陷處及第二金屬層152的一側定義為凹部181,而凹部181係設置於半封裝單元100一側的邊緣處,此外,部分的導熱結構11及部分的第二金屬層152經由對應的凹部181暴露出來。在一實施例中,凹部181係利用雷射凹槽鑽孔製程形成,而凹部181的深度H可為但不限為100μm。另外,移除部分的絕緣結構14,例如部分的第二絕緣層142,以形成複數個第一開孔182,而複數個第一開孔182係設置於半封裝單元100的一側,因此,第一金屬層151及第二金屬層152係經由對應的第一開孔182暴露出來。
接著,如第3B圖所示,提供第三金屬層191及第四金屬層192,而第三金屬層191係形成於第二絕緣層142上,使得第三金屬層191經由凹部181貼附於導熱結構11及第一金屬層151,而第三金屬層191經由對應的第一開孔182貼附於第一金屬層151及第二金屬層152。第四金屬層192則係形成於第一絕緣層141上,使得第四金屬層192經由對應的第三開孔143貼附於導熱結構11、第一導接端131及第二導接端132。
接著,如第3C圖所示,提供至少一第一薄膜201及至少一第二薄膜202,而第一薄膜201係形成於部分的第三金屬層191上。在一實施例中,第一薄膜201係形成在對應於電子元件13及導熱結構11之間的區域的部分第三金屬層191上。第二薄膜202則係形成在部分的第四金屬層192上。
接著,如第3D圖所示,提供第一金屬重佈線層21及第二金屬重佈線層16,而第一金重佈線層21係形成以覆蓋第三金屬層191,第一金屬重佈線層21經由第三金屬層191連接導熱結構11、第一金屬層151及第二金屬層152,而第二金屬重佈線層16係形成以覆蓋第四金屬層192,第二金屬重佈線層16係經由第四金屬層192連接導熱結構11、第一導接端131及第二導接端132。而第四金屬層192的材料與第二金屬重佈線層16的材料可為但不限為相同,因此第四金屬層192及第二金屬重佈線層16可為一體成形之結構。
接著,如第3E圖所示,移除第一薄膜201及第二薄膜202,而複數個第二開孔211係形成於第一金屬重佈線層21上,而複數個第四開孔161則係形成在第二金屬重佈線層16上。
接著,如第3F圖所示,提供第一遮罩22,而第一遮罩22係形成在第二開孔211上,使得第一遮罩22的位置係用以隔離連接第一金屬層151的第一金屬重佈線層21及連接第二金屬層152的第一金屬重佈線層21。於實施第3F圖的封裝方法後,再實施第1T圖至第1X圖的封裝方法,於此不再贅述。
第4圖為本案之嵌入式封裝結構之功率模組之部分結構示意圖。如第4圖所示,第一薄膜201設置於半封裝單元100的一側,而第一遮罩22係設置於第一薄膜201的一側。
第5圖為本案第二實施例之嵌入式封裝結構之功率模組之第一上視圖。如第5圖所示,第二開孔211的寬度L1係小於凹部181的寬度L2。在一實施例中,第二開孔211的寬度L1為400 um,而凹部181的寬度L2為600 um。
第6圖為本案第二實施例之嵌入式封裝結構之功率模組之第二上視圖。如第6圖所示,第二開孔211的寬度L1係大於凹部181的寬度L2。在一實施例中,第二開孔211的寬度L1為400 um,而凹部181的寬度L2為320 um。在另一實施例中,第二開孔211的寬度L1為480 um,而凹部181的寬度L2為400 um。
綜上所述,本案之實施例係提供一種封裝方法及封裝結構,根據本案之封裝方法及封裝結構,導熱結構的凹槽或絕緣層的凹槽係被第一金屬重佈線層所覆蓋,因此,導熱結構的側翼或絕緣層的側翼較容易塗佈導電材料。此外,由於導熱結構的側翼或絕緣層的側翼塗佈導電材料,導熱結構的側翼表面或絕緣層的側翼表面較不易氧化。更甚者,介於導熱結構與電路板之間或介於絕緣層與電路板之間的導電材料較為平坦,使得本案之封裝結構實施自動光學檢測時較為容易。
100:半封裝單元11:導熱結構111:第一凹槽112:第二凹槽12:第一載體13:電子元件131:第一導接端132:第二導接端14:絕緣結構141:第一絕緣層142:第二絕緣層143:第三開孔151:第一金屬層152:第二金屬層16:第二金屬重佈線層161:第四開孔17:第二載體181:凹部182:第一開孔191:第三金屬層192:第四金屬層201:第一薄膜202:第二薄膜21:第一金屬重佈線層211:第二開孔22:第一遮罩23:第二遮罩231:第五開孔24:第三金屬重佈線層25:第三遮罩251:第六開孔26:電路板27:導電材料28:導電層2:電源模組R:紅光G:綠光B:藍光H:深度L1、L2:寬度
第1A至1X圖為本案之第一實施例之電子元件之封裝方法之截面結構示意圖。
第2A至2N圖為本案之第二實施例之電子元件之部分封裝方法之截面結構示意圖。
第3A至3F圖為本案之第三實施例之電子元件之部分封裝方法之截面結構示意圖。
第4圖為本案之嵌入式封裝結構之功率模組之部分結構示意圖。
第5圖為本案第二實施例之嵌入式封裝結構之功率模組之第一上視圖。
第6圖為本案第二實施例之嵌入式封裝結構之功率模組之第二上視圖。
11:導熱結構
111:第一凹槽
112:第二凹槽
13:電子元件
131:第一導接端
132:第二導接端
141:第一絕緣層
151:第一金屬層
152:第二金屬層
16:第二金屬重佈線層
21:第一金屬重佈線層
22:第一遮罩
23:第二遮罩
24:第三金屬重佈線層
25:第三遮罩
26:電路板
27:導電材料
28:導電層
R:紅光
G:綠光
B:藍光
Claims (21)
- 一種封裝方法,包含步驟: (a) 提供一半封裝單元,該半封裝單元包含嵌於一絕緣結構內之一電子元件、一導熱結構、一第一金屬層及一第二金屬層,該第一金屬層係貼附於該電子元件,該第二金屬層係貼附於該導熱結構; (b) 移除部分的該絕緣結構以於該半封裝單元之一邊緣處形成至少一凹部,並於該半封裝單元之一側形成複數個第一開孔,以暴露出該第一金屬層及該第二金屬層; (c) 於該絕緣結構上形成一第一金屬重佈線層以連接該該第一金屬層及該第二金屬層;以及 (d) 於該第一金屬重佈線層上形成複數個第二開孔,並於該複數個第二開孔上形成一第一遮罩。
- 如請求項1所述之封裝方法,其中該步驟(a)前更包含步驟: 形成一第一凹槽於該導熱結構之一邊緣處; 提供一第一載體及該電子元件,其中該電子元件之一側包含至少一第一導接端及至少一第二導接端,且該導熱結構及該電子元件之另一側係貼附於該第一載體; 提供一第一絕緣層於該導熱結構之一側及該電子元件之該側; 移除該第一載體; 形成一第二凹槽於該導熱結構之另一邊緣處; 形成該第一金屬層於該電子元件之該另一側,並形成該第二金屬層於該導熱結構之另一側;以及 形成一第二絕緣層於該第一金屬層及該第二金屬層上,而該第一絕緣層及該第二絕緣層係形成該絕緣結構。
- 如請求項2所述之封裝方法,其中該步驟(a)中更包含步驟: 形成複數個第三開孔於該半封裝單元之該側以暴露出該導熱結構、該第一導接端及該第二導接端; 形成一第二金屬重佈線層於該第一絕緣層上,其中該第二金屬重佈線層係連接該導熱結構、該第一導接端及該第二導接端;以及 提供一第二載體於該第二金屬重佈線層上。
- 如請求項3所述之封裝方法,其中該步驟(b)中更包含步驟: 移除部分的該絕緣結構,以形成設置於該半封裝單元的該邊緣處的該至少一凹部。
- 如請求項3所述之封裝方法,其中該步驟(b)中更包含步驟: 移除該第二載體以暴露出該第二金屬重佈線層; 形成一第三金屬層於該第二絕緣層上;以及 形成至少一第一薄膜於部分的該第三金屬層上。
- 如請求項5所述之封裝方法,其中該步驟(c)中,該第三金屬層係被第一金屬重佈線層覆蓋,其中該第一金屬重佈線層經由該第三金屬層以連接該導熱結構、該第一金屬層及該第二金屬層。
- 如請求項5所述之封裝方法,其中該步驟(c)中更包含步驟:移除該第一薄膜。
- 如請求項5所述之封裝方法,其中該步驟(d)中更包含步驟: 形成複數個第四開孔於該第二金屬重佈線層上; 形成一第二遮罩於該第二金屬重佈線層上,其中複數個第五開孔係形成於該第二遮罩上,其中部分的該第二金屬重佈線層係經由該複數個第五開孔而暴露; 形成一第三金屬重佈線層於該第二遮罩上,其中該第三金屬重佈線層係與部分的該第二金屬重佈線層相連接;以及 形成一第三遮罩於該第三金屬重佈線層上,並形成複數個第六開孔以暴露該第三金屬重佈線層。
- 如請求項2所述之封裝方法,其中該步驟(a)中更包含步驟:形成複數個第三開孔於該半封裝單元之該側以暴露部分的該導熱結構、該第一導接端及該第二導接端。
- 如請求項9所述之封裝方法,其中該步驟(b)中更包含步驟: 形成一第三金屬層於該第二絕緣層上,以接觸該導熱結構、該第一金屬層及該第二金屬層; 形成一第四金屬層於該第一絕緣層上,以接觸該導熱結構、該第一導接端及該第二導接端; 形成至少一第一薄膜於部分的該第三金屬層上;以及 形成至少一第二薄膜於部分的該第四金屬層上。
- 如請求項10所述之封裝方法,其中該步驟(c)中,該第三金屬層係被該第一金屬重佈線層所覆蓋,其中該第一金屬重佈線層係經由該第四金屬層連接該導熱結構、部分的該第一金屬層及部分的該第二金屬層。
- 如請求項10所述之封裝方法,其中該步驟(c)中更包含步驟: 形成一第二金屬重佈線層於該第一絕緣層上,其中該第二金屬重佈線層係經由對應的該第三開孔連接該導熱結構、該第一導接端及該第二導接端;以及 移除該第一薄膜以形成複數個第四開孔,並移除該第二薄膜以形成該複數個第二開孔。
- 如請求項10所述之封裝方法,其中該步驟(c)中,該導熱結構及該電子元件係設置於該第一金屬重佈線層及該第二金屬重佈線層之間。
- 如請求項1所述之封裝方法,其中該步驟(b)中,該凹部係利用切割製程或雷射凹槽鑽孔製程形成。
- 如請求項1所述之封裝方法,其中該凹部之一深度為100μm。
- 一種封裝結構,係包含: 一電子元件; 一導熱結構,設於該電子元件之一側; 一第一金屬層,係貼附於該電子元件; 一第二金屬層,係貼附於該導熱結構; 一絕緣結構,包含一凹陷處及複數個第一開孔,其中該電子元件、該導熱結構、該第一金屬層及該第二金屬層係嵌入於該絕緣結構中,且該凹陷處係設於該絕緣結構之邊緣;以及 一第一金屬重佈線層,係經由該凹陷處連接該導熱結構及該第二金屬層的一側,並經由該複數個第一開孔連接該第一金屬層及該第二金屬層的另一側。
- 如請求項16所述之封裝結構,其中該導熱結構之一側、該絕緣結構之一第二凹槽及該第二金屬層之該側係定義為一凹部。
- 如請求項16所述之封裝結構,其中該封裝結構包含一第一遮罩,該第一金屬重佈線層包含複數個第二開孔,該第一遮罩係設置於該第二開孔上。
- 如請求項16所述之封裝結構,其中該導熱結構的一邊緣處包含一第一凹槽,該導熱結構的另一邊緣處包含一第二凹槽。
- 如請求項16所述之封裝結構,其中該電子元件包含一第一導接端及一第二導接端,該絕緣結構包含複數個第三開孔,其中該複數個第三開孔係對應該導熱結構、該第一導接端及該第二導接端設置。
- 如請求項20所述之封裝結構,其中該封裝結構更包含: 一第二金屬重佈線層,係設置於該絕緣結構上,並經由對應的該第三開孔與該導熱結構、該第一導接端及該第二導接端連接,其中該第二金屬重佈線層包含複數個第四開孔; 一第二遮罩,係設置於該第二金屬重佈線層上,並經由該複數個第四開孔與該絕緣結構連接,其中該第二遮罩包含複數個第五開孔; 一第三金屬重佈線層,係設置於該第二遮罩上,並經由該複數個第五開孔與該第二金屬重佈線層連接,其中該第三金屬重佈線層包含複數個第六開孔;以及 一第三遮罩,係設置於該第三金屬重佈線層上,並經由該複數個第六開孔與該第二遮罩相連接。
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CN105895611B (zh) | 2014-12-17 | 2019-07-12 | 恩智浦美国有限公司 | 具有可湿性侧面的无引线方形扁平半导体封装 |
SG10201501021PA (en) * | 2015-02-10 | 2016-09-29 | Delta Electronics Int L Singapore Pte Ltd | Package structure |
CN106356351B (zh) * | 2015-07-15 | 2019-02-01 | 凤凰先驱股份有限公司 | 基板结构及其制作方法 |
SG10201608773PA (en) * | 2016-10-19 | 2018-05-30 | Delta Electronics Intl Singapore Pte Ltd | Method Of Packaging Semiconductor Device |
US9972558B1 (en) * | 2017-04-04 | 2018-05-15 | Stmicroelectronics, Inc. | Leadframe package with side solder ball contact and method of manufacturing |
US10903148B2 (en) * | 2018-04-10 | 2021-01-26 | Microchip Technology Incorporated | High performance multi-component electronics power module |
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2018
- 2018-11-12 SG SG10201810052WA patent/SG10201810052WA/en unknown
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2019
- 2019-01-18 TW TW108102091A patent/TWI686878B/zh active
- 2019-01-30 US US16/262,363 patent/US11121110B2/en active Active
- 2019-01-31 CN CN201910097526.9A patent/CN111180348B/zh active Active
-
2020
- 2020-03-19 US US16/824,021 patent/US11081461B2/en active Active
Cited By (4)
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TWI723932B (zh) * | 2020-08-06 | 2021-04-01 | 強茂股份有限公司 | 側面可潤濕封裝元件及其製法 |
US11916030B2 (en) | 2020-09-08 | 2024-02-27 | Panjit International Inc. | Method for manufacturing side wettable package |
TWI751008B (zh) * | 2021-01-27 | 2021-12-21 | 鴻鎵科技股份有限公司 | 雙電晶體的封裝結構 |
TWI777389B (zh) * | 2021-01-27 | 2022-09-11 | 鴻鎵科技股份有限公司 | 雙電晶體的封裝結構 |
Also Published As
Publication number | Publication date |
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CN111180348B (zh) | 2024-04-09 |
US11121110B2 (en) | 2021-09-14 |
TWI686878B (zh) | 2020-03-01 |
CN111180348A (zh) | 2020-05-19 |
SG10201810052WA (en) | 2020-06-29 |
US20200219837A1 (en) | 2020-07-09 |
US20200152593A1 (en) | 2020-05-14 |
US11081461B2 (en) | 2021-08-03 |
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