TW202017889A - 一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法 - Google Patents
一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法 Download PDFInfo
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- 239000010949 copper Substances 0.000 title claims abstract description 151
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 150
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- 239000000758 substrate Substances 0.000 title claims abstract description 98
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 title claims abstract description 75
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 235000012431 wafers Nutrition 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
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- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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Abstract
本發明採用黃光微影製程與電鍍製程進行TAV填銅與圖樣化之雙面銅鍍層製作,在TAV穿孔處預先鍍製具對稱結構之雙面銅鍍層作為與氮化鋁基板間的應力緩衝層,再客製化進行後續的銅鍍層圖樣設計,依模擬理論計算佐證如此可有效降低具不對稱結構之雙面銅鍍層TAV氮化鋁基板的應力累積在短邊銅鍍層面,有利於提升氮化鋁基板的可靠度。
Description
本發明乃提出一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的對稱緩衝層結構,使用黃光微影製程與電鍍製程完成此結構製備,可有效降低具不對稱結構之雙面銅鍍層TAV氮化鋁基板的應力累積在短邊銅鍍層面,有利於提升氮化鋁基板的可靠度。
目前半導體產業之3DIC構裝最熱門的研究方向為矽穿孔(Through-Silicon Via)之填銅技術,因為矽穿孔技術應用於IC封裝體中,擁有電性佳、低功率、小尺寸、高密度、高性能等優勢,所以目前主要應用於DRAM之產品。但矽材料能承受之電流大小有限,絕緣效果差,且過大的電流將導致材料之破壞。而氮化鋁材料具有高熱傳導性、高電絕緣性及熱膨脹係數與GaN、AlGaN等半導體材料相近等優越特性,故可取代矽與藍寶石基板於功率元件(IGBT、MOSFET)與高功率LED封裝等領域應用,幫助元件能有更佳的性能表現。
穿孔技術應用於氮化鋁(AlN)晶圓上,將其定義為TAV(Through Aluminum Nitride via)技術,係先在氮化鋁基板上利用雷射或乾蝕刻(ICP)方式形成通孔,再以濺鍍或化學
鍍(無電電鍍)方式於基板整體表面與通孔中形成導電晶種層,最後使用電鍍製程結合銅材料或者其他導電材料(如鎢材料)以全填滿或者孔壁鍍層之方式產生於TAV中及基板表面。TAV不僅可以提供電性的連接,亦可提供散熱路徑,增加整個系統之散熱能力。
在氮化鋁基板的TAV製程與金屬化薄膜鍍製中必須經過多道高溫製程,此高溫製程可能導致填孔材料之突出現象而降低其良率。因填孔製程是從通孔側壁向通孔中心填滿導電材料,若未全部填滿而形成孔隙,則會造成整體之電阻上升降低電訊號的傳導效率,若在高溫的環境下則會使孔隙中的空氣膨脹而產生爆孔現象。製程後產出之晶圓將存在著殘留應力,此殘留應力將影響後續LED封裝體應用之可靠度,如填孔材料與銅壁之脫層現象,以及LED封裝體與基板之接合應力等。
氮化鋁基板的表面金屬線路與穿孔填銅製程如下:先在氮化鋁基板上利用雷射或乾蝕刻(ICP)方式形成通孔,再以濺鍍或化學鍍(無電電鍍)方式於基板整體表面與通孔中形成導電晶種層,最後使用電鍍製程結合銅材料或者其他導電材料(如鎢材料)以全填滿或者孔壁鍍層之方式產生於TAV中及基板表面。為提升散熱能力與導電效率,會增加陶瓷基板表面之金屬線路的銅層厚度,一般市售的金屬化陶瓷基板的銅鍍層厚度為50~100um,若有特殊的散熱與電性需求
則會持續提高銅鍍層的厚度。
第1圖為自製圖樣化TAV金屬化之氮化鋁基板,每一小片TAV基板尺寸為3mmx3mm並有兩個雷射穿孔,因此穿孔的上下寬度會不一樣。
將TAV金屬化之氮化鋁基板進行可靠度試驗,包含壓力鍋蒸煮試驗PCT(Pressure Cooker Test),採用JEDEC-22-A102之試驗規範:121℃/100%R.H./33psia(2atm),96hrs;及冷熱衝擊試驗TST(Thermal Shock Test),試驗規範為:-40℃~125℃,200cycles。結果顯示銅鍍層有發生脫層現象,而且在脫層後的位置有裂痕產生,如第2圖所示。
利用有限元素模擬分析所得最大主軸應力分布結果,如第3圖所示,可知當TAV基板處於一降溫負載下(△T=-110℃)(第3圖(a)),在銅鍍層發生脫層(Delamination)後的位置,氮化鋁受到最大主軸應力為一張應力(Tension);當TAV基板處於一升溫負載下(△T=45℃)(第3圖(b)),氮化鋁受到最大主軸應力為一壓應力(Compression)。由於脆性材料多半是因為受到一張應力而導致破壞情形發生,因此推測TAV基板是在降溫的過程中受到最大張應力而發生破壞。由圖中可以看出最有可能發生裂痕之位置與成長之方向和可靠度測試結果(第2圖)相符合。
若氮化鋁基板內部存在著填充導電材料之穿孔時,基板兩側皆會有銅鍍層之形成,基板兩側皆存在銅鍍層
之結構可以避免結構之不對稱性,並且大幅降低試片於溫度負載下之熱變形量。雖然試片變形量問題可利用此結構予以克服。然而,我們利用有限元素法模擬四種銅鍍層厚度之TAV基板在TST(Thermal shock test;熱衝擊試驗)降溫過程中(△T=-110℃)氮化鋁與銅鍍層之間所受到的Y方向之應力大小,如第4圖所示。銅鍍層厚度30um、60um、120um及180um之應力分別為48(MPa)、128(MPa)、203(MPa)及263(MPa),會隨著厚度增加,應力也越大。雖雙邊銅鍍層的非對稱結構(如第6圖所示)可以使長邊的應力值降低,但是其降低幅度很小,而且短邊的應力值會以較大的幅度逐漸上升,容易造成TAV基板因應力過高而產生破壞,如第5圖所示。
如第5圖所示,依有限元素模擬分析結果顯示,當銅鍍層厚度為30um時,雙面銅鍍層之對稱結構所造成基板應力略大於單面鍍層結構之基板應力。然而,當雙面銅鍍層呈現不對稱時,短邊銅鍍層面之基板應力高於長邊銅鍍層面之基板應力,兩者應力皆隨著長度差異量λ之增加而達到一穩定值。另發現當銅鍍層厚度為200um時,對稱銅鍍層結構所造成氮化鋁基板之應力明顯高於單面銅鍍層結構之氮化鋁基板應力,幅度高達30%,即可推斷此幅度增加量將隨著銅鍍層厚度之增大而增加。同樣地,當雙面銅鍍層呈現不對稱時,短邊銅鍍層面之基板應力明顯高於長邊銅鍍層面之基板應力,兩者應力皆隨著長度差異量λ之增加而達到一穩定值。
因此,由上述結果可推斷不對稱銅鍍層結構氮化鋁基板之最大應力發生處位於短邊銅鍍層面,即表示該處為基板破裂起始點。
接續著上述結果,亦針對銅鍍層厚度為50um、100um與300um之情況進行模擬分析,並且針對氮化鋁基板之最大主軸應力值進行探討。結果如圖五所示,可知當銅鍍層之厚度越小,單面鍍層或雙面鍍層所造成氮化鋁基板之最大主軸應力值差異越小,換句話說,隨著銅鍍層厚度之增加,銅鍍層結構設計(單面或雙面、對稱或不對稱)所造成氮化鋁基板應力之差異性隨之增加。對於存在著不對稱雙面銅鍍層之氮化鋁基板之穩定應力值而言,短邊處之穩定應力值明顯大於長邊處之穩定應力值,且其差異量隨著銅鍍層厚度之增加而增加。
緣是,發明人有鑑於此,秉持多年該相關行業之豐富設計開發及實際製作經驗,針對現有之結構及缺失予以研究改良,提供一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法,以期達到更佳實用價值性之目的者。
鑒於上述習知技術之缺點,本發明主要之目的在於提供一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法,利用黃光微影製程與電鍍製程進行TAV填銅與圖樣化之雙面銅鍍層製作,在TAV穿孔處先鍍製具對稱結構之雙面
銅鍍層作為與氮化鋁基板間的應力緩衝層,再客製化進行後續的銅鍍層圖樣設計,依模擬理論計算佐證如此可有效降低具不對稱結構之雙面銅鍍層之氮化鋁基板的應力累積在短邊銅鍍層面,有利於提升氮化鋁基板的可靠度之目的。
為達上述目的,本發明係提供一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法,包括:提供一氮化鋁基板;使用濺鍍方式鍍製一厚度為100nm至500nm的一附著層於該氮化鋁基板上,該附著層為鈦合金或鈦/鎢合金;使用濺鍍方式鍍製一厚度為0.8um至1um的一銅晶種層於該附著層上;使用電鍍方式鍍製一厚度為30um至100um的一對稱結構銅緩衝層於該銅晶種層上;使用電鍍方式鍍製一厚度為30um至150um的一銅鍍層於該對稱結構銅緩衝層上;包覆一厚度為100nm至500nm的一鎳鍍層於該附著層、該銅晶種層、該對稱結構銅緩衝層及該銅鍍層上。
亦就是說,本案特點為在氮化鋁基板穿孔處先鍍製具對稱結構之雙面銅鍍層作為與氮化鋁基板間的應力緩衝層,具有降低應力累積之功效,可有效提升陶瓷基板在應用上的可靠度。
以上之概述與接下來的詳細說明及附圖,皆是為了能進一步說明本創作達到預定目的所採取的方式、手段及功效。而有關本創作的其他目的及優點,將在後續的說明及圖式中加以闡述。
1‧‧‧氮化鋁基板
2‧‧‧附著層
3‧‧‧銅晶種層
4‧‧‧對稱結構銅緩衝層
5‧‧‧銅鍍層
6‧‧‧鎳鍍層
S1-S6‧‧‧步驟
第1圖係為TAV金屬化之氮化鋁基板表面與穿孔結構及位置示意圖。
第2圖係為TAV金屬化之氮化鋁基板經過PCT與TST可靠度試驗之破壞顯微圖。
第3圖係為利用有限元素模擬分析所得主軸應力大小與方向之結果(a)△T=-110℃(b)△T=45℃分析圖。
第4圖係為利用有限元素模擬四種銅鍍層厚度之氮化鋁基板在TST(Thermal shock test;熱衝擊試驗)降溫過程中(△T=-110℃)氮化鋁與銅鍍層之間的最大Y方向之應力大小分析圖。
第5圖係為銅鍍層厚度、單面鍍層、雙面對稱及不對稱鍍層所造成氮化鋁基板最大主軸應力σprincipal之差異結果分析圖。
第6圖係為習知不具對稱結構的雙面銅鍍層結構示意圖。
第7圖係為本發明之雙面銅鍍層結構示意圖。
第8圖係為本發明之降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法流程圖。
以下係藉由特定的具體實例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容瞭解本發明之其他優點與功效。
依先前技術及理論計算得知,雙面對稱銅層之氮化鋁基板所承受之最大應力大於單面銅層氮化鋁基板之最大應力,且銅層厚度越大,其效應越明顯。若要降低具雙面銅鍍層之TAV氮化鋁基板的應力累積在不對稱結構之短邊處,則必需改變氮化鋁基板在穿孔處的雙面銅鍍層為對稱結構,才能有效避免應力累積在短邊銅鍍層面。
請參閱第7圖及第8圖,第7圖係為本發明之雙面銅鍍層結構示意圖。第8圖係為本發明之降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法流程圖,如圖所示,一種降低雙面銅鍍層5與氮化鋁基板1之界面應力累積的方法,包括:步驟S1:提供一氮化鋁基板1。步驟S2:使用濺鍍方式鍍製附著層2於氮化鋁基板1上,附著層2為鈦合金或鈦/鎢合金、附著層2之厚度可為100nm至500nm。步驟S3:使用濺鍍方式鍍製銅晶種層3於附著層2上,銅晶種層3之厚度可為0.8um至1um。步驟S4:使用電鍍方式鍍製對稱結構銅緩衝層4於銅晶種層3上,對稱結構銅緩衝層4之厚度可為30um至100um,所謂的對稱結構是指雙邊的銅緩衝層彼此呈對稱結構。步驟
S5:使用電鍍方式鍍製銅鍍層5於對稱結構銅緩衝層4上,銅鍍層5之厚度可為30um至150um,而雙邊的銅鍍層5彼此呈非對稱結構。步驟S6:包覆鎳鍍層6於附著層2、銅晶種層3、對稱結構銅緩衝層4及銅鍍層5上,鎳鍍層6之厚度可為100nm至500nm。
本發明採用黃光微影製程與電鍍製程進行TAV填銅與圖樣化之雙面銅鍍層5製作,在TAV穿孔處先鍍製具對稱結構之銅緩衝層作為與氮化鋁基板1間的應力緩衝層,再客製化進行後續的銅鍍層5圖樣設計,依模擬理論計算佐證如此可有效降低具不對稱結構之雙面銅鍍層5之氮化鋁基板1的應力累積在短邊銅鍍層5面,有利於提升氮化鋁基板1的可靠度。
本發明之銅鍍層5是無法直接鍍製在氮化鋁基板1上,會很容易剝落,通常須先鍍製鈦合金或鈦/鎢合金作為附著層2,接著會使用濺鍍製程鍍製一層較薄的銅鍍層是為銅晶種層3(Cu seed layer),這層的用意是有助於後續在電鍍製程時銅離子結合電子後能緊密附著在此表面上與穿孔中;而銅緩衝層4是本案為了解決應力累積問題而提出的結構,在穿孔處先鍍製具對稱結構之銅鍍層是為對稱結構銅緩衝層4,目的為降低後續電鍍製程所製備的厚膜銅鍍層5與氮化鋁基板1間的應力累積,兩者的作用是不同的,銅晶種層3為緊密接合後續電鍍製程所製備的薄膜銅鍍層,對稱結構銅緩衝層4為降低厚膜銅鍍層5與氮化鋁基板1間的應力累積問題。
此外,本發明之詳細製程如下:提供一氮化鋁基板1;利用黃光微影製程在氮化鋁基板1上定義出圖形,黃光微影製程如下:(1)提供一圖樣化之光罩,在氮化鋁基板1上使用旋轉塗佈方法佈滿光阻或是貼上光阻膜,將光罩和佈滿光阻之氮化鋁基板1使用曝光機進行對準校正,執行曝光後利用顯影液預先在穿孔處定義出對稱的圖形結構;(2)以濺鍍方式在氮化鋁基板1上鍍製鈦合金或鈦/鎢合金(Ti或Ti/W)作為附著層2(附著層2厚度:100~500nm);(3)以濺鍍或化學鍍(無電電鍍)方式在氮化鋁基板1上鍍製銅晶種層3(厚度:0.8~1um);(4)使用電鍍方式進行對稱結構銅緩衝層4鍍製(厚度:30~100um);(5)使用剝離液(如丙酮)將不需要的光阻去除,留下所定義的具對稱結構圖樣化鍍銅之TAV氮化鋁基板1;(6)再使用黃光微影製程在圖樣化鍍銅之氮化鋁基板1上定義出新圖形,使用電鍍方式進行後續圖樣化銅鍍層5鍍製;(7)最後鍍製鎳(Ni)金屬層做為銅鍍層5的保護/阻障層(厚度:100~500nm),避免銅氧化及擴散。
綜上所述,本案利用黃光微影製程與電鍍製程進行TAV填銅與圖樣化之雙面銅鍍層5製作,在TAV穿孔處先鍍製具對稱結構之銅緩衝層作為與氮化鋁基板1間的應力緩衝層,再客製化進行後續的銅鍍層5圖樣設計,依模擬理論計算佐證如此可有效降低具不對稱結構之雙面銅鍍層5之氮化鋁基板1的應力累積在短邊銅鍍層5面,有利於提升氮化鋁基板1
的可靠度之功效。另外,本發明是因為將圖樣化氮化鋁基板1做可靠度試驗後發現有應力累積的問題而造成基板破裂,是為了解決應力累積問題而提出在穿孔處先鍍製具對稱結構銅緩衝層4,可降低銅鍍層5與陶瓷基板間的應力累積,後續再客製化鍍製具不對稱結構結構之銅鍍層5,與業界所用相比一樣具不對稱結構之銅鍍層5,但本發明多了可降低應力累積之功效,可有效提升陶瓷基板在應用上的可靠度。
上述之實施例僅為例示性說明本發明之特點及其功效,而非用於限制本發明之實質技術內容的範圍。任何熟習此技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與變化。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。
1‧‧‧氮化鋁基板
2‧‧‧附著層
3‧‧‧銅晶種層
4‧‧‧對稱結構銅緩衝層
5‧‧‧銅鍍層
6‧‧‧鎳鍍層
Claims (3)
- 一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法,包括:提供一氮化鋁基板;使用濺鍍方式鍍製一附著層於該氮化鋁基板上,該附著層為鈦合金或鈦/鎢合金;使用濺鍍方式鍍製一銅晶種層於該附著層上;使用電鍍方式鍍製一對稱結構銅緩衝層於該銅晶種層上;使用電鍍方式鍍製一銅鍍層於該對稱結構銅緩衝層上;包覆一鎳鍍層於該附著層、該銅晶種層、該對稱結構銅緩衝層及該銅鍍層上。
- 如申請專利範圍第1項所述之方法,其中該對稱結構銅緩衝層厚度為30um至100um。
- 一種降低雙面銅鍍層與氮化鋁基板之界面應力累積的方法,包括:提供一氮化鋁基板;使用濺鍍方式鍍製一厚度為100nm至500nm的一附著層於該氮化鋁基板上,該附著層為鈦合金或鈦/鎢合金;使用濺鍍方式鍍製一厚度為0.8um至1um的一銅晶種層於該附著層上;使用電鍍方式鍍製一厚度為30um至100um的一對稱結構銅緩衝層於該銅晶種層上; 使用電鍍方式鍍製一厚度為30um至150um的一銅鍍層於該對稱結構銅緩衝層上;包覆一厚度為100nm至500nm的一鎳鍍層於該附著層、該銅晶種層、該對稱結構銅緩衝層及該銅鍍層上。
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JP2909856B2 (ja) * | 1991-11-14 | 1999-06-23 | 日本特殊陶業株式会社 | セラミックス基板と金属の接合体 |
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