TW201935642A - 包含通孔插塞的半導體裝置及其形成方法 - Google Patents

包含通孔插塞的半導體裝置及其形成方法 Download PDF

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TW201935642A
TW201935642A TW107127491A TW107127491A TW201935642A TW 201935642 A TW201935642 A TW 201935642A TW 107127491 A TW107127491 A TW 107127491A TW 107127491 A TW107127491 A TW 107127491A TW 201935642 A TW201935642 A TW 201935642A
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insulating layer
layer
hole
intermediate insulating
semiconductor device
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TWI752253B (zh
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李義福
白宗玟
安商燻
吳赫祥
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南韓商三星電子股份有限公司
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Abstract

本發明提供一種半導體裝置，所述半導體裝置包含安置在基底上的下部絕緣層。導電圖案形成於下部絕緣層中。中間絕緣層安置在下部絕緣層及導電圖案上。通孔控制區形成於中間絕緣層中。上部絕緣層安置在中間絕緣層及通孔控制區上。通孔插塞經形成穿過通孔控制區且連接至導電圖案。通孔控制區具有比中間絕緣層更低的蝕刻速率。

Description

包含通孔插塞的半導體裝置及其形成方法
本申請是關於一種包含通孔插塞的半導體裝置及形成所述半導體裝置的方法。
隨著半導體裝置的集成密度的增加，用於電性連接多個主動/被動元件的互連技術面臨多種侷限性。已嘗試使用多層互連技術來提高集成效率。
本申請的一實施例是關於一種半導體裝置，所述半導體裝置包含：下部絕緣層，安置在基底上；導電圖案，形成於所述下部絕緣層中；中間絕緣層，安置在所述下部絕緣層及所述導電圖案上；通孔控制區，形成於所述中間絕緣層中；上部絕緣層，安置於所述中間絕緣層及所述通孔控制區上；以及通孔插塞，經設置成穿過所述通孔控制區且連接至所述導電圖案。通孔控制區具有比中間絕緣層更低的蝕刻速率。
本申請的一實施例亦是關於一種半導體裝置，所述半導體裝置包含：下部絕緣層，安置在基底上；多個導電圖案，形成於所述下部絕緣層中；中間絕緣層，安置在所述下部絕緣層及所述多個導電圖案上；多個通孔控制區，形成於所述中間絕緣層中；上部絕緣層，安置在所述中間絕緣層及所述多個通孔控制區上；以及通孔插塞，形成於所述多個通孔控制區之間且連接至選自所述多個導電圖案中的一個導電圖案。所述多個通孔控制區配置在所述多個導電圖案之間，且通孔控制區具有比中間絕緣層更低的孔隙率。
本申請的一實施例亦是關於一種半導體裝置，所述半導體裝置包含：下部絕緣層，安置在基底上；導電圖案，形成於所述下部絕緣層中；中間絕緣層，安置在所述下部絕緣層及所述導電圖案上；通孔控制區，形成於所述中間絕緣層中；上部絕緣層，安置在所述中間絕緣層及所述通孔控制區上；通孔插塞，經設置成穿過所述通孔控制區且連接至所述導電圖案；以及上部互連件，形成於所述上部絕緣層中且連接至所述通孔插塞。所述通孔控制區包含具有比所述中間絕緣層更低的蝕刻速率的材料。
本申請的一實施例亦是關於一種形成半導體裝置的方法，所述方法包含在基底上形成下部絕緣層及在下部絕緣層中形成導電圖案。中間絕緣層形成於下部絕緣層及導電圖案上。使用選擇性緻密化製程（selective densification process）使通孔控制區形成於中間絕緣層中。上部絕緣層形成於中間絕緣層及通孔控制區上。通孔插塞經形成穿過通孔控制區且連接至導電圖案。通孔控制區具有比中間絕緣層更低的蝕刻速率。
圖1至圖4是根據本申請的實施例的半導體裝置的橫截面視圖。
參看圖1，半導體裝置可包含基底21、下部絕緣層33、第一障壁金屬層34、多個導電圖案35、罩蓋層36、蝕刻終止層42、黏合層45、中間絕緣層46、多個通孔控制區47、上部絕緣層56、通孔62H、溝槽64T、第二障壁金屬層65、晶種層66以及上部導電層67。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔62H內部的通孔插塞71，且構成溝槽64T內部的上部互連件72。
所述多個導電圖案35可經形成在下部絕緣層33中彼此間隔開。所述多個導電圖案35的側表面可由第一障壁金屬層34包圍。罩蓋層36可形成於所述多個導電圖案35上。蝕刻終止層42、黏合層45、中間絕緣層46以及上部絕緣層56可依序堆疊在下部絕緣層33及罩蓋層36上。
所述多個通孔控制區47可形成於中間絕緣層46中。所述多個通孔控制區47及中間絕緣層46的頂部表面可實質上共面。所述多個通孔控制區47可佈置在所述多個導電圖案35之間。所述多個通孔控制區47的底部表面可形成於比中間絕緣層46的底部表面更高的位置處。中間絕緣層46可保持在所述多個通孔控制區47與黏合層45之間。在本申請的實施例中，所述多個通孔控制區47可佈置在所述多個導電圖案35之間的部分的上方。
中間絕緣層46可具有第一厚度T1。黏合層45可具有第二厚度T2。第二厚度T2可小於第一厚度T1。所述多個通孔控制區47可呈現第三厚度T3。第三厚度T3可小於第一厚度T1。第三厚度T3可大於第二厚度T2。在本申請的實施例中，第三厚度T3可在約20奈米至約100奈米的範圍內。舉例而言，所述多個通孔控制區47的第三厚度T3可為約50奈米。
中間絕緣層46可包含低介電係數介電材料。在本申請的實施例中，中間絕緣層46可包含使用可流動化學氣相沈積（flowable chemical vapor deposition；FCVD）法形成的SiOCH層。所述多個通孔控制區47可包含SiOCH、SiOH或其組件的組合。相較中間絕緣層46，所述多個通孔控制區47可具有更高「氧」（O）含量以及更低「碳」（C）含量。所述多個通孔控制區47可具有相對於中間絕緣層46的蝕刻選擇性。所述多個通孔控制區47可具有比中間絕緣層46更低的蝕刻速率。所述多個通孔控制區47可具有比中間絕緣層46更高的硬度。所述多個通孔控制區47可具有比中間絕緣層46更低的孔隙率。
在本申請的實施例中，中間絕緣層46可包含SiOx Cy H層。所述多個通孔控制區47可包含SiOm Cn H層。此處，x、y、m以及n可呈x ＞ 0、y ＞ 0、m ＞ 0、n ≥ 0、x ＜ m以及y ＞ n的關係。
溝槽64T可形成於上部絕緣層56中。通孔62H可與溝槽64T的底部表面連通。通孔62H可穿過所述多個通孔控制區47之間的部分，且完全穿過中間絕緣層46、黏合層45以及蝕刻終止層42。可藉由所述多個通孔控制區47與中間絕緣層46之間的蝕刻選擇性來形成通孔62H的形狀。所述多個通孔控制區47可用以控制通孔62H的構型。所述多個通孔控制區47可用以減小通孔62H的對準誤差。所述多個通孔控制區47可用以防止通孔62H的特定區域非正常擴大。舉例而言，所述多個通孔控制區47可用以防止通孔62H的上部區域非正常擴大。
通孔62H的側壁可為傾斜的。從橫截面看，通孔62H的側壁可包含曲面或反曲點。通孔62H的側壁上的一個點處的切線與平行於基底21的表面的橫線之間的交叉角θ1可在45°至90°的範圍內。在本申請的實施例中，交叉角θ1可在82°至88°的範圍內。舉例而言，交叉角θ1可為約85°。在本申請的實施例中，交叉角θ1可對應於倒角。
上部互連件72可形成於溝槽64T內部。通孔插塞71可形成於通孔62H內部。通孔62H及通孔插塞71中的每一個的高度可大於其側面寬度。通孔插塞71可與上部互連件72的底部表面相接。通孔插塞71可穿過所述多個通孔控制區47之間的部分，且穿過中間絕緣層46、黏合層45以及蝕刻終止層42以與罩蓋層36直接接觸。通孔插塞71可電性連接至選自所述多個導電圖案35中的一個導電圖案。通孔插塞71的側表面可與所述多個通孔控制區47、中間絕緣層46、黏合層45以及蝕刻終止層42直接接觸。可由通孔62H來形成通孔插塞71的形狀。所述多個通孔控制區47可用以控制通孔插塞71的形狀。上部互連件72的底部表面可與所述多個通孔控制區47及中間絕緣層46的頂部表面直接接觸。
在本申請的實施例中，所述多個通孔控制區47可在中間絕緣層46中彼此連接。通孔插塞71可被視為穿過通孔控制區47。
參看圖2，所述多個通孔控制區47可與中間絕緣層46具有實質上相同的厚度。所述多個通孔控制區47的底部表面可與黏合層45接觸。所述多個通孔控制區47及中間絕緣層46的底部表面可實質上共面。通孔62H可穿過所述多個通孔控制區47之間的部分，且完全穿過黏合層45及蝕刻終止層42。通孔插塞71可穿過所述多個通孔控制區47之間的部分，且穿過黏合層45及蝕刻終止層42以與罩蓋層36直接接觸。通孔插塞71的側表面可與所述多個通孔控制區47、黏合層45以及蝕刻終止層42直接接觸。
在本申請的實施例中，可省略黏合層45。所述多個通孔控制區47的底部表面可與蝕刻終止層42接觸。
參看圖3，下部絕緣層33可形成於比第一障壁金屬層34及所述多個導電圖案35的頂部末端更低的位置處。第一障壁金屬層34及所述多個導電圖案35可突出至比下部絕緣層33的頂部表面更高的位置。中間絕緣層46的底部末端可形成於比所述多個導電圖案35的頂部末端更低的位置處。中間絕緣層46可安置在所述多個導電圖案35的側表面旁邊。所述多個通孔控制區47的底部表面可與黏合層45及中間絕緣層46接觸。通孔62H可穿過所述多個通孔控制區47之間的部分，且完全穿過黏合層45及蝕刻終止層42。通孔插塞71可穿過所述多個通孔控制區47之間的部分，且穿過黏合層45及蝕刻終止層42以與罩蓋層36直接接觸。通孔插塞71的側表面可與所述多個通孔控制區47、黏合層45以及蝕刻終止層42直接接觸。
參看圖4，所述多個通孔控制區47的底部表面可形成於比黏合層45的頂部末端更高的位置處。所述多個通孔控制區47的底部表面可與中間絕緣層46直接接觸。通孔62H可穿過所述多個通孔控制區47之間的部分，且完全穿過中間絕緣層46、黏合層45以及蝕刻終止層42。通孔插塞71可穿過所述多個通孔控制區47之間的部分，且穿過中間絕緣層46、黏合層45以及蝕刻終止層42以與罩蓋層36直接接觸。通孔插塞71的側表面可與所述多個通孔控制區47、中間絕緣層46、黏合層45以及蝕刻終止層42直接接觸。
圖5至圖8是根據本申請的實施例的半導體裝置的橫截面視圖。
參看圖5，通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可形成於通孔62H內部。通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可構成通孔插塞71。通孔插塞71、所述多個通孔控制區47及中間絕緣層46的頂部表面可實質上共面。上部絕緣層56可形成於中間絕緣層46、所述多個通孔控制區47以及通孔插塞71上。溝槽64T可形成於上部絕緣層56中。上部障壁金屬層65B、上部晶種層66B以及上部導電層67B可形成於溝槽64T中。上部障壁金屬層65B、上部晶種層66B以及上部導電層67B可構成上部互連件72。上部互連件72可與通孔插塞71接觸。上部障壁金屬層65B可與通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A的頂部表面直接接觸。
參看圖6，通孔62H可穿過上部絕緣層56、穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。第二障壁金屬層65、晶種層66以及上部導電層67可形成於通孔62H中。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔插塞71。通孔插塞71可與罩蓋層36接觸。通孔插塞71的側表面可與上部絕緣層56、所述多個通孔控制區47、中間絕緣層46、黏合層45以及蝕刻終止層42直接接觸。
參看圖7，下部絕緣層33可形成於比第一障壁金屬層34及所述多個導電圖案35的頂部末端更低的位置處。第一障壁金屬層34及所述多個導電圖案35可突出至比下部絕緣層33的頂部表面更高的位置。通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可形成於通孔62H內部。通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可構成通孔插塞71。通孔插塞71、所述多個通孔控制區47及中間絕緣層46的頂部表面可實質上共面。
參看圖8，下部絕緣層33可形成於比第一障壁金屬層34及所述多個導電圖案35的頂部末端更低的位置處。第一障壁金屬層34及所述多個導電圖案35可突出至比下部絕緣層33的頂部表面更高的位置。通孔62H可穿過上部絕緣層56、穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。第二障壁金屬層65、晶種層66以及上部導電層67可形成於通孔62H內部。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔插塞71。通孔插塞71可與罩蓋層36接觸。
圖9至圖19示出根據本申請的實施例的形成半導體裝置的方法中的各階段的橫截面視圖。在本申請的實施例中，形成半導體裝置的方法可包含雙嵌刻製程（dual damascene process）。
參看圖9，下部絕緣層33、第一障壁金屬層34以及所述多個導電圖案35可形成於基底21上。所述多個導電圖案35中的每一個可對應於下部互連件或下部通孔插塞。所述多個導電圖案35中的每一個可對應於重佈層（redistribution layer；RDL）或重佈插塞。多個主動/被動元件可形成於基底21中或基底21上。所述多個導電圖案35中的每一個可連接至選自所述多個主動/被動元件中的一個主動/被動元件。
基底21可包含例如單晶矽晶圓或絕緣體上矽（silicon-on-insulator；SOI）晶圓的半導體基底。下部絕緣層33可覆蓋基底21。下部絕緣層33可包含絕緣材料，諸如氧化矽、氮化矽、氮氧化矽、碳氮氧化矽（silicon oxycarbonitride；SiOCN）、低介電係數介電材料、高介電係數介電材料或其組合。在本申請的實施例中，下部絕緣層33可包含低介電係數介電材料，諸如SiOCH。
第一障壁金屬層34及所述多個導電圖案35可形成於下部絕緣層33中。形成第一障壁金屬層34及所述多個導電圖案35可包含薄膜形成製程及平坦化製程。平坦化製程可包含化學機械拋光（chemical mechanical polishing；CMP）製程、回蝕製程或其組合。下部絕緣層33、第一障壁金屬層34以及所述多個導電圖案35的頂部表面可暴露於實質上相同的平坦表面處。所述多個導電圖案35中的每一個可由第一障壁金屬層34包圍。第一障壁金屬層34可包含鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）、錳（Mn）、氧化錳（MnO）、氮化錳（MnN）、釕（Ru）、氧化釕（RuO）、氮化釕（RuN）或其組合。所述多個導電圖案35可包含導電材料，諸如金屬、金屬氧化物、金屬氮化物、金屬矽化物、多晶矽（poly-Si）、導電碳或其組合。舉例而言，所述多個導電圖案35可包含銅（Cu）、釕（Ru）、氧化釕（RuO）、氮化釕（RuN）、鈷（Co）、鎢（W）、氮化鎢（WN）、鈦（Ti）、氮化鈦（TiN）、鉭（Ta）、氮化鉭（TaN）、氮化錳（Mn）、氧化錳（MnO）、氮化錳（MnN）或其組合。在本申請的實施例中，所述多個導電圖案35可包含使用電鍍製程形成的銅（Cu）層。
參看圖10，罩蓋層36可形成於所述多個導電圖案35上。可應用選擇性沈積製程來形成罩蓋層36。罩蓋層36可覆蓋所述多個導電圖案35及第一障壁金屬層34。罩蓋層36可包含導電材料，諸如鈷（Co）、鈷鎢（CoW）、磷化鈷鎢（CoWP）、氮化鈷釕（CoRuN）、釕（Ru）、碳基石墨烯或其組合。在本申請的實施例中，罩蓋層36可包含厚度為約5奈米的鈷（Co）層。
參看圖11，可形成蝕刻終止層42以覆蓋罩蓋層36、所述多個導電圖案35、第一障壁金屬層34以及下部絕緣層33。形成蝕刻終止層42的製程可包含化學氣相沈積（chemical vapor deposition；CVD）製程、環狀CVD製程、原子層沈積（atomic layer deposition；ALD）製程或其組合。
參看圖12，黏合層45及中間絕緣層46可形成於蝕刻終止層42上。黏合層45可形成於蝕刻終止層42與中間絕緣層46之間。中間絕緣層46可經形成為具有20奈米至100奈米的厚度。在本申請的實施例中，中間絕緣層46可經形成為具有約50奈米的厚度。黏合層45可具有比中間絕緣層46更小的厚度。在實施中，可省略黏合層45。蝕刻終止層42可包含具有相對於黏合層45及中間絕緣層46的蝕刻選擇性的材料。蝕刻終止層45可包含具有相對於中間絕緣層46的蝕刻選擇性的材料。中間絕緣層46可包含低介電係數介電材料。
在本申請的實施例中，中間絕緣層46可包含使用FCVD製程形成的SiOCH層。黏合層45可包含SiOCH、SiOH或其組件的組合。相較中間絕緣層46，黏合層45可具有更高「O」含量及更低「C」含量。可使用原位製程來形成黏合層45及中間絕緣層46。黏合層45可具有比中間絕緣層46更小的蝕刻速率。黏合層45可具有比中間絕緣層46更高的硬度。黏合層45可具有比中間絕緣層46更低的孔隙率。蝕刻終止層42可包含氮化矽（silicon nitride；SiN）、碳氮化矽（silicon carbonitride；SiCN）、碳氮氧化矽（SiOCN）、氮氧化矽（silicon oxynitride；SiON）、氮化鋁（aluminum nitride；AlN）、氧化鋁（aluminum oxide；AlO）、碳氧化鋁（aluminum oxycarbide；AlOC）或其組合。
在本申請的實施例中，中間絕緣層46可包含SiOx Cy H層。黏合層45可包含SiOm Cn H層。此處，x、y、m以及n可呈x ＞ 0、y ＞ 0、m ＞ 0、n ≥ 0、x ＜ m以及y ＞ n的關係。
參看圖13，第一罩幕圖案47M可形成於中間絕緣層46上。第一罩幕圖案47M可包含光致抗蝕劑圖案、硬罩幕圖案或其組合。在本申請的實施例中，第一罩幕圖案47M可包含氮氧化矽（SiON）、氧化鈦（titanium oxide；TiO）、氧化鋁（AlO）或其組合。
參看圖14，所述多個通孔控制區47可形成於中間絕緣層46中。形成所述多個通孔控制區47可包含選擇性緻密化製程。用於形成所述多個通孔控制區47的選擇性緻密化製程可包含O2 灰化製程、紫外線（ultraviolet；UV）照射製程或其組合。舉例而言，在選擇性緻密化製程期間，歸因於第一罩幕圖案47M，中間絕緣層46可經部分暴露於O2 電漿。O2 電漿可由各種類型的偏壓電源控制。
所述多個通孔控制區47可包含SiOCH、SiOH或其組件的組合。相較中間絕緣層46，所述多個通孔控制區47可具有更高「O」含量以及更低「C」含量。所述多個通孔控制區47可具有相對於中間絕緣層46的蝕刻選擇性。所述多個通孔控制區47可具有比中間絕緣層46更低的蝕刻速率。所述多個通孔控制區47可具有比中間絕緣層46更高的硬度。所述多個通孔控制區47可具有比中間絕緣層46更低的孔隙率。
在本申請的實施例中，中間絕緣層46可包含SiOx Cy H層。所述多個通孔控制區47可包含SiOm Cn H層。此處，x、y、m以及n可呈x ＞ 0、y ＞ 0、m ＞ 0、n ≥ 0、x ＜ m以及y ＞ n的關係。
所述多個通孔控制區47中的每一個可經形成為具有各種構型。在本申請的實施例中，所述多個通孔控制區47中的每一個可具有梯形形狀、橢圓形狀或廣口瓶形狀。所述多個通孔控制區47可經形成為具有20奈米至100奈米的厚度。在本申請的實施例中，所述多個通孔控制區47可經形成為約50奈米的厚度。所述多個通孔控制區47可佈置在所述多個導電圖案35之間。
所述多個通孔控制區47可經形成為在中間絕緣層46中彼此間隔開。在本申請的實施例中，所述多個通孔控制區47可在中間絕緣層46中彼此連接。
參看圖15，可移除第一罩幕圖案47M以暴露中間絕緣層46及所述多個通孔控制區47。可對中間絕緣層46及所述多個通孔控制區47執行UV照射。
參看圖16，上部絕緣層56可形成於中間絕緣層46及所述多個通孔控制區47上。上部絕緣層56可包含低介電係數介電材料。可使用FCVD製程、電漿增強型CVD（plasma-enhanced CVD；PECVD）製程、ALD製程或其組合形成上部絕緣層56。上部絕緣層56可經形成為20奈米至100奈米的厚度。在本申請的實施例中，上部絕緣層56可經形成為具有約50奈米的厚度。
上部絕緣層56可包含具有相對於所述多個通孔控制區47的蝕刻選擇性的材料。上部絕緣層56可具有比所述多個通孔控制區47更高的蝕刻速率。在本申請的實施例中，上部絕緣層56可包含SiOCH層。
參看圖17，第二罩幕圖案61M可形成於上部絕緣層56上。可使用作為蝕刻罩幕的第二罩幕圖案61M來形成通孔62H以完全穿過上部絕緣層56、穿過所述多個通孔控制區47之間的部分以及部分地穿過中間絕緣層46。可藉由所述多個通孔控制區47與中間絕緣層46之間的蝕刻選擇性來增強第二罩幕圖案61M的對準界限。形成通孔62H可包含各向異性蝕刻製程。
參看圖18，可移除第二罩幕圖案61M，且第三罩幕圖案63M可形成於上部絕緣層56上。可使用第三罩幕圖案63M作為蝕刻罩幕將溝槽64T形成於上部絕緣層56中。形成溝槽64T可包含各向異性蝕刻製程。在將溝槽64T形成於上部絕緣層56中期間，通孔62H可向下擴大。通孔62H可穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。罩蓋層36可暴露於通孔62H的底部表面。通孔62H可與溝槽64T的底部表面連通。
可藉由所述多個通孔控制區47與中間絕緣層46之間的蝕刻選擇性來形成通孔62H的形狀。所述多個通孔控制區47可用以控制通孔62H的構型。所述多個通孔控制區47可用以減小通孔62H的對準誤差。所述多個通孔控制區47可幫助防止通孔62H的特定區域非正常擴大。舉例而言，所述多個通孔控制區47可用以防止通孔62H的上部區域非正常擴大。
參看圖19，可移除第三罩幕圖案63M。第二障壁金屬層65、晶種層66以及上部導電層67可形成於通孔62H及溝槽64T內部。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔62H內部的通孔插塞71，且構成溝槽64T內部的上部互連件72。第二障壁金屬層65可經形成以包圍上部導電層67的側表面及底部表面。晶種層66可介於第二障壁金屬層65與上部導電層67之間。形成通孔插塞71及上部互連件72可包含薄膜形成製程及平坦化製程。上部絕緣層56、第二障壁金屬層65、晶種層66以及上部導電層67的頂部表面可暴露於實質上相同的平坦表面。
第二障壁金屬層65可包含Ti、TiN、Ta、TaN、Mn、MnO、MnN、Ru、RuO、RuN或其組合。晶種層66及上部導電層67可包含導電材料，諸如金屬、金屬氧化物、金屬氮化物、金屬矽化物、多晶矽、導電碳或其組合舉例而言，晶種層66及上部導電層67可包含Cu、Ru、RuO、RuN、Co、W、WN、Ti、TiN、Ta、TaN、Mn、MnO、MnN或其組合。在本申請的實施例中，晶種層66可包含使用CVD製程或物理氣相沈積（physical vapor deposition；PVD）製程形成的銅（Cu）層。上部導電層67可包含使用電鍍製程形成的銅（Cu）層。
在本申請的實施例中，襯墊可形成於第二障壁金屬層65與晶種層66之間。襯墊可包含Mn、Co、Ru或其組合。
圖20至圖27是用於描述根據本申請的實施例的形成半導體裝置的方法的橫截面視圖。
參看圖20，下部絕緣層33、第一障壁金屬層34、多個導電圖案35以及罩蓋層36可形成於基底21上。下部絕緣層33可凹進至比第一障壁金屬層34及所述多個導電圖案35的頂部末端更低的位置。第一障壁金屬層34及所述多個導電圖案35可突出至比下部絕緣層33的頂部表面更高的位置。罩蓋層36可覆蓋第一障壁金屬層34及所述多個導電圖案35的頂部表面。
參看圖21，蝕刻終止層42可形成於下部絕緣層33、第一障壁金屬層34、所述多個導電圖案35、以及罩蓋層36上。蝕刻終止層42可共形地沿下部絕緣層33、第一障壁金屬層34以及罩蓋層36的暴露表面形成。
參看圖22，黏合層45及中間絕緣層46可形成於蝕刻終止層42上。黏合層45可共形地覆蓋蝕刻終止層42的表面。中間絕緣層46可比黏合層45更厚。
參看圖23，第一罩幕圖案47M可形成於中間絕緣層46上。
參看圖24，多個通孔控制區47可形成於中間絕緣層46中。
參看圖25，可移除第一罩幕圖案47M以暴露中間絕緣層46及所述多個通孔控制區47。
參看圖26，上部絕緣層56可形成於中間絕緣層46及所述多個通孔控制區47上。
參看圖27，可形成溝槽64T及通孔62H。溝槽64T可形成於上部絕緣層56中。通孔62H可與溝槽64T的底部表面連通。通孔62H可穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。罩蓋層36可暴露於通孔62H的底部表面。
返回參看圖3，第二障壁金屬層65、晶種層66以及上部導電層67可形成於通孔62H及溝槽64T中。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔62H內部的通孔插塞71，且構成溝槽64T內部的上部互連件72。
圖28至圖30示出根據本申請的實施例的形成半導體裝置的方法中的階段的橫截面視圖。在本申請的實施例中，形成半導體裝置的方法可包含單金屬鑲嵌製程。
參看圖28，下部絕緣層33、第一障壁金屬層34、所述多個導電圖案35、罩蓋層36、蝕刻終止層42、黏合層45、中間絕緣層46、所述多個通孔控制區47以及通孔62H可形成於基底21上。通孔62H可穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。罩蓋層36可暴露於通孔62H的底部表面。
參看圖29，通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可形成於通孔62H內部。通孔障壁金屬層65A、通孔晶種層66A以及通孔導電層67A可構成通孔插塞71。通孔插塞71、所述多個通孔控制區47以及中間絕緣層46的頂部表面可暴露於實質上相同的平坦表面。
參看圖30，上部絕緣層56可形成於中間絕緣層46、所述多個通孔控制區47以及通孔插塞71上。溝槽64T可形成於上部絕緣層56中。中間絕緣層46、所述多個通孔控制區47以及通孔插塞71可暴露於溝槽64T的底部表面。
返回參看圖5，上部障壁金屬層65B、上部晶種層66B以及上部導電層67B可形成於溝槽64T內部。上部障壁金屬層65B、上部晶種層66B以及上部導電層67B可構成上部互連件72。上部互連件72可與通孔插塞71接觸。上部障壁金屬層65B可與通孔插塞71的頂部表面直接接觸。
通孔障壁金屬層65A及上部障壁金屬層65B可包含Ti、TiN、Ta、TaN、Mn、MnO、MnN、Ru、RuO、RuN或其組合。通孔晶種層66A、上部晶種層66B、通孔導電層67A以及上部導電層67B可包含導電材料，諸如金屬、金屬氧化物、金屬氮化物、金屬矽化物、多晶矽、導電碳或其組合。舉例而言，通孔晶種層66A、上部晶種層66B、通孔導電層67A以及上部導電層67B可包含Cu、Ru、RuO、RuN、Co、W、WN、Ti、TiN、Ta、TaN、Mn、MnO、MnN或其組合。在本申請的實施例中，通孔晶種層66A及上部晶種層66B可包含使用CVD製程或PVD製程形成的銅（Cu）層。通孔導電層67A及上部導電層67B可包含使用電鍍製程形成的銅（Cu）層。
在本申請的實施例中，襯墊可進一步形成於通孔障壁金屬層65A與通孔晶種層66A之間以及上部障壁金屬層65B與上部晶種層66B之間。襯墊可包含Mn、Co、Ru或其組合。
圖31是示出根據本申請的實施例的形成半導體裝置的方法的橫截面視圖。
參看圖31，下部絕緣層33、第一障壁金屬層34、多個導電圖案35、罩蓋層36、蝕刻終止層42、黏合層45、中間絕緣層46、多個通孔控制區47、上部絕緣層56以及通孔62H可形成於基底21上。通孔62H可穿過上部絕緣層56、穿過所述多個通孔控制區47之間的部分、完全穿過中間絕緣層46、穿過黏合層45以及穿過蝕刻終止層42。罩蓋層36可暴露於通孔62H的底部表面。
返回參看圖6，第二障壁金屬層65、晶種層66以及上部導電層67可形成於通孔62H內部。第二障壁金屬層65、晶種層66以及上部導電層67可構成通孔插塞71。通孔插塞71及上部絕緣層56的頂部表面可暴露於實質上相同的平坦表面。
藉由總結及回顧，上部互連層可經由通孔插塞連接至下部互連層。A 通孔插塞的結構及形成通孔插塞的方法可顯著影響批量生產效率及半導體裝置的可靠性。
如上所述，實施例是關於提供具有通孔插塞的半導體裝置，所述通孔插塞可提供提高批量生產效率及可靠性的優勢。
另外，實施例是關於提供形成具有通孔插塞的半導體裝置的方法，所述通孔插塞可提供提高批量生產效率及可靠性的優勢。
根據本申請的實施例，多個通孔控制區可設置在中間絕緣層中。可使用選擇性緻密化製程來形成所述多個通孔控制區。通孔可經形成以穿過所述多個通孔控制區之間的部分。通孔插塞可形成於通孔內部。所述多個通孔控制區可控制通孔的形狀。
本文中已揭露本申請的實施例，且儘管利用特定術語，但這些術語是僅在一般以及描述性意義上而非出於限制目的使用且應僅在一般以及描述性意義上而非出於限制目的解釋。在一些情況下，如所屬領域中具通常知識者截至本申請案申請時所顯而易見，除非另外具體指示，否則關於特定實施例所描述的特徵、特性及/或要素可單獨使用或與關於其他實施例所描述的特徵、特性及/或要素組合使用。因此，在所屬領域中具通常知識者應理解，在不脫離如在以下申請專利範圍中所闡述的本發明的精神及範疇的情況下，可進行各種形式與細節改變。
21‧‧‧基底
33‧‧‧下部絕緣層
34‧‧‧第一障壁金屬層
35‧‧‧導電圖案
36‧‧‧罩蓋層
42‧‧‧蝕刻終止層
45‧‧‧黏合層
46‧‧‧中間絕緣層
47‧‧‧通孔控制區
47M‧‧‧第一罩幕圖案
56‧‧‧上部絕緣層
61M‧‧‧第二罩幕圖案
62H‧‧‧通孔
63M‧‧‧第三罩幕圖案
64T‧‧‧溝槽
65‧‧‧第二障壁金屬層
65A‧‧‧通孔障壁金屬層
65B‧‧‧上部障壁金屬層
66‧‧‧晶種層
66A‧‧‧通孔晶種層
66B‧‧‧上部晶種層
67‧‧‧上部導電層
67A‧‧‧通孔導電層
67B‧‧‧上部導電層
71‧‧‧通孔插塞
72‧‧‧上部互連件
T1‧‧‧第一厚度
T2‧‧‧第二厚度
T3‧‧‧第三厚度
θ1‧‧‧交叉角
藉由參看隨附圖式詳細地描述實施例，特徵將對於所屬領域中具通常知識者變得顯而易見，其中： 圖1至圖8示出根據本申請的實施例的半導體裝置的橫截面視圖。 圖9至圖31示出根據本申請的實施例的形成半導體裝置的方法中的各階段的橫截面視圖。

Claims (20)

  1. 一種半導體裝置，包括： 下部絕緣層，位於基底上； 導電圖案，位於所述下部絕緣層中； 中間絕緣層，位於所述下部絕緣層及所述導電圖案上； 通孔控制區，位於所述中間絕緣層中，所述通孔控制區具有比所述中間絕緣層更低的蝕刻速率； 上部絕緣層，位於所述中間絕緣層及所述通孔控制區上；以及 通孔插塞，穿過所述通孔控制區且連接至所述導電圖案。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述通孔控制區及所述中間絕緣層的頂部表面實質上共面。
  3. 如申請專利範圍第1項所述的半導體裝置，其中： 所述中間絕緣層包含低介電係數（low-k）介電材料；以及 所述通孔控制區具有比所述中間絕緣層更低的孔隙率（porosity）。
  4. 如申請專利範圍第1項所述的半導體裝置，其中： 所述中間絕緣層包含SiOx Cy H層；以及 所述通孔控制區包含SiOm Cn H層， 其中x ＞ 0，y ＞ 0，m ＞ 0，n ≥ 0，x ＜ m，以及y ＞ n。
  5. 如申請專利範圍第1項所述的半導體裝置，其中所述通孔控制區的底部表面處於比所述中間絕緣層的底部表面更高的位置。
  6. 如申請專利範圍第5項所述的半導體裝置，其中所述通孔控制區的所述底部表面與所述中間絕緣層接觸。
  7. 如申請專利範圍第1項所述的半導體裝置，其中所述通孔控制區及所述中間絕緣層的底部表面實質上共面。
  8. 如申請專利範圍第1項所述的半導體裝置，其中： 所述下部絕緣層的頂部表面處於比所述導電圖案的頂部末端更低的位置；以及 所述中間絕緣層的底部末端處於比所述導電圖案的所述頂部末端更低的位置。
  9. 如申請專利範圍第1項所述的半導體裝置，更包括所述下部絕緣層與所述中間絕緣層之間的黏合層，其中： 所述通孔插塞穿過所述黏合層； 所述中間絕緣層包含SiOx Cy H層；以及 所述黏合層包含SiOm Cn H層， 其中x ＞ 0，y ＞ 0，m ＞ 0，n ≥ 0，x ＜ m，以及y ＞ n。
  10. 如申請專利範圍第9項所述的半導體裝置，其中所述中間絕緣層介於所述通孔控制區與所述黏合層之間。
  11. 如申請專利範圍第9項所述的半導體裝置，其中所述通孔插塞的側表面與所述通孔控制區、所述中間絕緣層以及所述黏合層接觸。
  12. 如申請專利範圍第9項所述的半導體裝置，其中所述通孔控制區的底部表面與所述黏合層接觸。
  13. 如申請專利範圍第12項所述的半導體裝置，其中所述通孔插塞的側表面與所述通孔控制區及所述黏合層接觸。
  14. 如申請專利範圍第9項所述的半導體裝置，其中所述黏合層比所述中間絕緣層更薄。
  15. 如申請專利範圍第9項所述的半導體裝置，其中所述通孔控制區比所述黏合層更厚。
  16. 如申請專利範圍第9項所述的半導體裝置，更包括所述下部絕緣層與所述黏合層之間的蝕刻終止層，所述蝕刻終止層具有相對於所述中間絕緣層及所述黏合層的蝕刻選擇性。
  17. 如申請專利範圍第16項所述的半導體裝置，其中所述通孔插塞的側表面與所述通孔控制區、所述中間絕緣層、所述黏合層以及所述蝕刻終止層接觸。
  18. 一種半導體裝置，包括： 下部絕緣層，位於基底上； 多個導電圖案，位於所述下部絕緣層中； 中間絕緣層，位於所述下部絕緣層及所述多個導電圖案上； 多個通孔控制區，位於所述中間絕緣層中，所述多個通孔控制區配置在所述多個導電圖案之間，且所述多個通孔控制區具有比所述中間絕緣層更低的孔隙率； 上部絕緣層，位於所述中間絕緣層及所述多個通孔控制區上；以及 通孔插塞，位於所述多個通孔控制區之間且連接至選自所述多個導電圖案中的一個導電圖案。
  19. 一種半導體裝置，包括： 下部絕緣層，位於基底上； 導電圖案，位於所述下部絕緣層中； 中間絕緣層，位於所述下部絕緣層及所述導電圖案上； 通孔控制區，形成於所述中間絕緣層中，所述通孔控制區包含具有比所述中間絕緣層更低的蝕刻速率的材料； 上部絕緣層，位於所述中間絕緣層及所述通孔控制區上； 通孔插塞，穿過所述通孔控制區且連接至所述導電圖案；以及 上部互連件，位於所述上部絕緣層中且連接至所述通孔插塞。
  20. 如申請專利範圍第19項所述的半導體裝置，其中所述通孔控制區的頂部表面與所述上部互連件接觸。
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