TW201916273A - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

Info

Publication number
TW201916273A
TW201916273A TW106131708A TW106131708A TW201916273A TW 201916273 A TW201916273 A TW 201916273A TW 106131708 A TW106131708 A TW 106131708A TW 106131708 A TW106131708 A TW 106131708A TW 201916273 A TW201916273 A TW 201916273A
Authority
TW
Taiwan
Prior art keywords
dielectric layer
semiconductor package
package structure
layer
item
Prior art date
Application number
TW106131708A
Other languages
English (en)
Other versions
TWI636533B (zh
Inventor
郭書瑋
鄭惟元
楊鎮在
林玠模
Original Assignee
財團法人工業技術研究院
創智智權管理顧問股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 財團法人工業技術研究院, 創智智權管理顧問股份有限公司 filed Critical 財團法人工業技術研究院
Priority to TW106131708A priority Critical patent/TWI636533B/zh
Priority to CN201711223474.2A priority patent/CN109509724A/zh
Priority to US15/849,593 priority patent/US10461035B2/en
Application granted granted Critical
Publication of TWI636533B publication Critical patent/TWI636533B/zh
Publication of TW201916273A publication Critical patent/TW201916273A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種半導體封裝結構，包括重佈線路結構、半導體晶片、上介電層、複數個導電件以及封裝膠層。重佈線路結構包括重佈線路層以及配置於重佈線路層上的第一介電層。上介電層配置於半導體晶片與重佈線路結構的第一介電層之間，其中第一介電層與上介電層為有機材料。複數個導電件配置於重佈線路層與半導體晶片之間，各導電件具有鄰近於半導體晶片的第一端以及鄰近於重佈線路結構的第二端，其中各導電件的第一端與上介電層接觸且各導電件的第二端與第一介電層接觸。

Description

半導體封裝結構
本發明是有關於一種半導體封裝結構。
因應未來行動載具及物聯網(Internet of Things，IoT)產品輕巧化、細緻化與多功能需求，相關IC功能關鍵組件之功能整合度提高，伴隨晶圓製程線路微細化，晶片輸入/輸出(I/O)數大幅提升，原有橋接IC/PCB之封裝整合技術已漸不敷使用，具有高解析度、低成本與低應力之晶片封裝結構將為產業需求。
晶片封裝結構的可靠度對於晶片整體效能的表現上一直是重要議題。現行封裝製程，應力容易集中在導電凸塊周圍，特別是當輸入輸出金屬接墊的分布密度越來越高。當晶片封裝結構被撓曲，由於應力會集中在導電凸塊角落，容易發生斷裂的問題，而使可靠度失效。另外，在晶片封裝模組的取下過程，也容易因為應力過於集中於導電凸塊而使得封裝結構脫層的風險提高。
據此，如何解決現有因應力分佈不均導致晶片封裝結構可靠度不佳之問題為目前所欲研究的主題。
本發明實施例提供一種半導體封裝結構，可以提高元件可靠度，並降低晶片封裝模組取下過程結構脫層( delamination)的風險。
本發明一實施例提供一種半導體封裝結構，包括重佈線路結構、半導體晶片、上介電層、複數個導電件以及封裝膠層。重佈線路結構包括重佈線路層以及配置於重佈線路層上的第一介電層。半導體晶片配置於重佈線路結構上。上介電層配置於半導體晶片與重佈線路結構的第一介電層之間，其中第一介電層與上介電層的材料為有機材料。複數個導電件配置於重佈線路層與半導體晶片之間，重佈線路結構透過各個導電件與半導體晶片電性連接，且各個導電件具有鄰近於半導體晶片的第一端以及鄰近於重佈線路結構的第二端，其中，各個導電件的第一端與上介電層接觸且各個導電件的第二端與第一介電層接觸。封裝膠層填充於重佈線路結構、半導體晶片與複數個導電件之間。
基於上述，在本發明的實施例中，半導體封裝結構包括複數個導電件，導電件兩端分別配置有機上介電層與有機第一介電層，可使導電件下方的金屬接墊之角落的應力大幅降低，減少導電件角落斷裂的機率以及提高晶片封裝結構的可靠度。本發明的實施例之半導體封裝結構，搭配第二介電層的材料採用無機材料，可以使半導體封裝結構達到高解析度或細節距(fine pitch)，進而應用於需要高密度或較高接腳數的半導體晶片封裝產品。
為讓本發明能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
有關本揭露實施例之前述及其他技術內容，在以下配合參考圖式之各實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明，而並非用來限制本揭露。並且，在下列各實施例中，相同或相似的元件將採用相同或相似的標號。
圖1A為本發明的一實施例的半導體封裝結構剖面示意圖。在本實施例中，半導體封裝結構100包括一重佈線路結構110、一半導體晶片120、一上介電層130以及複數個導電件140。重佈線路結構110包括一重佈線路層112以及配置於重佈線路層112上的一第一介電層114。半導體晶片120配置於重佈線路結構110上。上介電層130配置於半導體晶片120與重佈線路結構110的第一介電層114之間，其中第一介電層114與上介電層130的材料為有機材料。有機材料可為聚亞醯胺(PI)、聚苯并噁唑(PBO)、苯環丁烯聚合物(BCB) 或其他適合的材料。第一介電層114與上介電層130的製造方式可為塗布製程，例如狹縫塗布(slit coating)、旋轉塗布(spin coating)等濕式製程、化學氣相沉積(chemical vapor deposition，CVD)製程、其他可應用的製程、或前述之組合而形成，本發明不限於此。
半導體封裝結構100之複數個導電件140，配置於重佈線路層112與半導體晶片120之間。重佈線路結構110透過複數個導電件140與半導體晶片120電性連接，且各個導電件140具有鄰近於半導體晶片120的第一端E1以及鄰近於重佈線路結構110的第二端E2。其中，各個導電件140的第一端E1與上介電層130接觸且各個導電件140的第二端E2與第一介電層114接觸。半導體封裝結構100更包括一封裝膠層150，填充於重佈線路結構110、半導體晶片120與複數個導電件140之間。封裝膠層150可為環氧樹脂(epoxy)、聚甲基丙烯酸甲酯(Polymethylmethacrylate)、其他聚合物或其組合，但本發明不限於此。
各個導電件140更包括具有第一端E1的一上冶金層148、一導電柱142、一錫球凸塊(solder)144以及具有第二端E2的一下冶金層146。錫球凸塊144配置於導電柱142與下冶金層146之間，且錫球凸塊144的相對兩端分別與導電柱142與下冶金層146接觸。上冶金層148之第一端E1與金屬接墊170接觸，亦即上冶金層148同時接觸上介電層130與金屬接墊170，且上冶金層148透過金屬接墊170與半導體晶片120電性連接。導電件140之第二端E2同時接觸第一介電層114與重佈線路層112且與重佈線路層112電性連接。導電件140中的錫球凸塊144的材料可為錫銀合金或錫鉛合金等等。上冶金層148與下冶金層146的材料可為球下金屬層(Under Bump Metallurgy)所採用的材料，例如為一銅層、或一鈦層及一晶種層(可由銅或銅合金所構成)。
重佈線路結構110包括複數個導電貫孔V。重佈線路層112更包括複數個圖案化線路層160及複數個介電層。如圖1所示，這些介電層包括第二介電層116以及第三介電層118，其中第二介電層116與第一介電層114接觸，且該第三介電層118為最遠離該些導電件140的介電層，這些圖案化線路層160與第一介電層114、第二介電層116以及第三介電層118彼此交替堆疊，且這些圖案化線路層160透過這些導電貫孔V與相對應的導電件140電性連接。第三介電層118下方設置一球底支撐層190。在進行封裝製程中，先在載板(未繪示)上形成球底支撐層190，在本實施例中，球底支撐層190的材料可包括有機高分子材料、無機高分子材料或有機無機混合材料，厚度約介於1微米至50微米之間，以及形成圖案化線路層160與第一介電層114、第二介電層116以及第三介電層118彼此交替堆疊，以形成重佈線路結構110。移除載板之後，可形成具有開口O的球底支撐層190。如此，在先形成重佈線路結構110而後設置半導體晶片120的封裝製程中，所形成的半導體封裝結構100，得以具有球底支撐層190，因而可對銲球(solder ball，未繪示)提供結構支撐並可幫助銲球對位，提升半導體封裝結構100的可靠度。此外，球底支撐層190可防止水氣進入半導體封裝結構100內，因而可增加半導體封裝結構100的阻擋水氣及/或抗氧化的能力。
半導體封裝結構100還包括頂封裝膠層180包覆半導體晶片120。頂封裝膠層180的材料可採用環氧模壓樹脂(Epoxy Molding Compound)，但不限於此。在本發明之一實施例中，複數個導電件140中任二相鄰的導電件140之間的間距S約介於10至30微米之間。
在本發明的一實施例中，半導體封裝結構100之上介電層130的楊氏係數為A，封裝膠層150的楊氏係數為B，第二介電層116的楊氏係數為C，第一介電層114的楊氏係數為D，其中，半導體封裝結構100滿足以下的不等式： A＜B≦C；以及 D＜B≦C。
在本發明的另一實施例中，半導體封裝結構100除了滿足以上不等式外，更進一步更滿足以下的不等式： D≦A＜9吉帕(GPa)， 其中第一介電層114與上介電層130的材料為有機材料。
在本發明的又一實施例中，半導體封裝結構100除了滿足以上不等式外，更進一步更滿足以下的不等式： D≦A＜5吉帕(GPa)， 其中第一介電層114與上介電層130的材料為有機材料。
在本實施例中，當導電件140的第一端E1與第二端E2周圍分別配置楊氏係數小於封裝膠層150的楊氏係數的上介電層130與第一介電層114，可使導電件140下方的金屬接墊角落的應力大幅降低，減少導電件140角落斷裂的機率，提升元件可靠度。
在本發明的另一實施例中，半導體封裝結構100更滿足以下的不等式： A/B＜1；以及 D/B＜1。
在本發明的又一實施例中，半導體封裝結構100更滿足以下的不等式： A＜9吉帕(GPa)；以及 D＜9吉帕(GPa)。 其中第一介電層114與上介電層130的材料為有機材料。
在本發明的再一實施例中，半導體封裝結構100之第三介電層118的楊氏係數為F，且第二介電層116的楊氏係數為C，其中，半導體封裝結構100更滿足以下的不等式： F≦C。
第二介電層116的材料可為無機材料，例如為二氧化矽、氮化矽、氮氧化矽、聚矽氮氧烷或聚矽氮烷等，但本發明不限於此。在本發明的另一實施例中，半導體封裝結構100之封裝膠層150的楊氏係數介於約5吉帕(GPa)至15吉帕(GPa)之間。在又一實施例中，封裝膠層150的楊氏係數介於約7吉帕(GPa)至12吉帕(GPa)之間。
圖1B為本發明的另一實施例的半導體封裝結構剖面示意圖。圖1B的半導體封裝結構200與圖1A的半導體封裝結構100相似，其主要差異在於，圖1B的上介電層130a是連續的，而圖1A的上介電層130為不連續的。
圖2A為圖1A沿剖線I-I’的局部上視圖。圖2B為圖1B沿剖線I-I’的局部上視圖。圖1B的半導體封裝結構200僅繪示圖2B的半導體封裝結構200的局部，也就是上介電層130a為連續的部分。請同時參照圖2A與圖2B。半導體晶片120上配置有上介電層130以及金屬接墊170。請參照圖2A，上介電層130包圍金屬接墊170。由於金屬接墊170排列疏散，在任二相鄰的金屬接墊170之間，上介電層130的圖案分布為非連續圖案A1。請參照圖2B，半導體晶片120包括金屬接墊170排列疏散與排列緊密的兩區。在金屬接墊170排列疏散的區域，上介電層130a的圖案分布可為非連續圖案A1。在金屬接墊170排列緊密的區域，上介電層130a的圖案分布可為連續圖案A2。在另一實施例中，在金屬接墊170排列疏散的區域，上介電層130的圖案分布亦可為連續圖案A2。上介電層130的圖案分布可依照金屬接墊170排列方式與密度不同而有不同設計。
請同時參照圖1與圖2A。在一實施例中，圖1之半導體封裝結構100之上介電層130中的一圖案的寬度W2大於對應此圖案的第一端E1與金屬接墊170接觸的開口的寬度W1的兩倍。
在一實施例中，請參照圖1，導電件140的寬度為W，導電件的高度為H，其中，半導體封裝結構100更滿足以下的不等式： W/H＜1， 當半導體封裝結構100滿足以上不等式，可提高封裝膠層150填充於重佈線路結構110、半導體晶片120與複數個導電件140之間的均勻度，使氣泡不容易產生。在半導體封裝結構朝向細節距(fine pitch)的趨勢下，可以達到較佳的可靠度。
圖3A為本發明的一實施例的半導體封裝結構的比較例之應力分布模擬示意圖。圖3B為本發明的一實施例的半導體封裝結構的實驗例的應力分布模擬示意圖。為了證明本揭露的半導體封裝結構可用以解決應力過於集中之問題，特別以比較例以及實驗例作為說明。請同時參照圖3A與圖3B，圖3A之比較例與圖3B之實驗例的半導體封裝結構與本文圖1A實施例的半導體封裝結構100類似。圖3A與圖3B的模擬結構採用相同的尺寸，其中導電件140寬度W為55μm，高度H為60μm，相鄰的兩個導電件140間距S為25μm。導電件140上方的上介電層130的材料均採用聚亞醯胺(PI)，導電件140下方則繪示厚度均為5μm的介電層310與模擬等效層312。模擬等效層主要是模擬重佈線路結構110的圖案化線路層160與介電層複合的等效層，為了簡化圖示以清楚表示各層構件，圖3A與圖3B中只繪示部分的模擬等效層。
在此模擬實驗中，導電件140上方的金屬接墊170的材料採用鋁，也可選用金、銅、鉛、錫或鎳基合金，導電件140下方的金屬接墊170A的材料採用銅，也可選用金、鋁、鉛、錫或鎳基合金。比較例與實驗例的差異在於，圖3A之比較例的介電層310的材料採用無機的二氧化矽(SiO2 )，圖3B實驗例的介電層310的材料採用有機的聚亞醯胺(PI)。比較例與實驗例的模擬等效層312的材料與厚度均相同。
請同時參照圖3A與圖3B。網點的分布越密，代表應力越強。不同應力區塊之間則以虛線區分。在同一虛線區塊內的應力值相同。在圖3A的金屬接墊170A的右側角落之深色塊，為此圖3A之應力最大處，應力值約為103MPa。請參照圖3B，整體的應力分布均勻，且金屬接墊170A的應力值大幅降低，應力值約為51MPa。由以上模擬結果可知，當第一介電層材料由無機的二氧化矽(SiO2 )置換為有機的聚亞醯胺(PI)，其餘條件不變，可大幅降低導電件下方的金屬接墊的應力，已經低於金屬接墊的降伏強度(本模擬實施例導電件下方的金屬接墊材料係選用銅)。換言之，上述結構可用以解決應力過於集中之問題，並且可增加半導體封裝結構之可靠度。
當半導體晶片端的開口間距(例如相鄰二金屬接墊之間距)小於50微米，若僅藉由錫球凸塊(solder)做為電性連接半導體晶片與重佈線路結構，將會無法達到良好的解析度與良率，因而例如是採用包括銅柱(Cu pillar)的導電件，以做為電性連接半導體晶片與重佈線路結構會是較佳的選擇。另一方面，當重佈線路結構端的相鄰二導電件的間距小於30微米時，重佈線路層採用無機介電層(例如為二氧化矽、氮化矽、氮氧化矽、聚矽氮氧烷或聚矽氮烷等)做為支撐，搭配銅柱可以達到良好解析度與可靠度，進一步搭配本發明實施例於導電件的上、下端設置低楊式係數的有機介電層，可大幅降低導電件下方的金屬接墊角落的應力，減少導電件角落斷裂的機率以及提高晶片封裝結構的可靠度。綜上所述，在本發明的實施例中，半導體封裝結構包括複數個導電件，導電件兩端分別配置有機上介電層與有機第一介電層，可使導電件下方的金屬接墊角落的應力大幅降低，降低導電件角落斷裂的機率，提升可撓曲性，以及提高晶片封裝結構的可靠度。本發明實施例之半導體封裝結構，搭配第二介電層的材料採用無機材料，可以使半導體封裝結構做到細節距(fine pitch)，進而應用於需要高密度或較高接腳數的半導體晶片封裝產品。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200‧‧‧半導體封裝結構
110‧‧‧重佈線路結構
112‧‧‧重佈線路層
114‧‧‧第一介電層
116‧‧‧第二介電層
118‧‧‧第三介電層
120‧‧‧半導體晶片
130、130a‧‧‧上介電層
140‧‧‧導電件
142‧‧‧導電柱
144‧‧‧錫球凸塊
146‧‧‧上冶金層
148‧‧‧下冶金層
150‧‧‧封裝膠層
160‧‧‧圖案化線路層
170、170A‧‧‧金屬接墊
180‧‧‧頂封裝膠層
190‧‧‧球底支撐層
310‧‧‧介電層
312‧‧‧模擬等效層
A1‧‧‧非連續圖案
A2‧‧‧連續圖案
E1‧‧‧第一端
E2‧‧‧第二端
W、W1、W2‧‧‧寬度
H‧‧‧高度
I-I’‧‧‧剖線
O‧‧‧開口
V‧‧‧導電貫孔
S‧‧‧間距
圖1A為本發明的一實施例的半導體封裝結構剖面示意圖。 圖1B為本發明的另一實施例的半導體封裝結構剖面示意圖。 圖2A為圖1A沿剖線I-I’的局部上視圖。 圖2B為圖1B沿剖線I-I’的局部上視圖。 圖3A為本發明的一實施例的半導體封裝結構的比較例之應力分布模擬示意圖。 圖3B為本發明的一實施例的半導體封裝結構的實驗例的應力分布模擬示意圖。

Claims (17)

  1. 一種半導體封裝結構，包括： 一重佈線路結構，包括一重佈線路層以及配置於該重佈線路層上的一第一介電層； 一半導體晶片，配置於該重佈線路結構上； 一上介電層，配置於該半導體晶片與該重佈線路結構的該第一介電層之間，其中該第一介電層與該上介電層的材料為有機材料； 複數個導電件，配置於該重佈線路層與該半導體晶片之間，該重佈線路結構透過該些導電件與該半導體晶片電性連接，且各該導電件具有鄰近於該半導體晶片的一第一端以及鄰近於該重佈線路結構的一第二端， 其中，各該導電件的該第一端與該上介電層接觸且各該導電件的該第二端與該第一介電層接觸；以及 一封裝膠層，填充於該重佈線路結構、該半導體晶片與該些導電件之間。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中各該導電件更包括具有該第一端的一上冶金層、一導電柱、一錫球凸塊以及具有該第二端的一下冶金層，該錫球凸塊配置於該導電柱與該下冶金層之間且該錫球凸塊的相對兩端分別與該導電柱與該下冶金層接觸。
  3. 如申請專利範圍第2項所述的半導體封裝結構，其中該上冶金層的該第一端與一金屬接墊接觸，且該上冶金層透過該金屬接墊與該半導體晶片電性連接。
  4. 如申請專利範圍第1項所述的半導體封裝結構，其中該些導電件中任二相鄰的該導電件之間的間距介於10至30微米之間。
  5. 如申請專利範圍第1項所述的半導體封裝結構，其中該重佈線路層包括一第二介電層以及一第三介電層，其中該第二介電層與該第一介電層接觸，且該第三介電層為最遠離該些導電件的介電層。
  6. 如申請專利範圍第5項所述的半導體封裝結構，其中該上介電層的楊氏係數為A，該封裝膠層的楊氏係數為B，該第二介電層的楊氏係數為C，該第一介電層的楊氏係數為D， 其中，該半導體封裝結構更滿足以下的不等式： A＜B≦C；以及 D＜B≦C。
  7. 如申請專利範圍第6項所述的半導體封裝結構，其中該半導體封裝結構更滿足以下的不等式： D≦A＜9吉帕(GPa)。
  8. 如申請專利範圍第6項所述的半導體封裝結構，其中該半導體封裝結構更滿足以下的不等式： D≦A＜5吉帕(GPa)。
  9. 如申請專利範圍第5項所述的半導體封裝結構，其中該第三介電層的楊氏係數為F，且該第二介電層的楊氏係數為C， 其中，該半導體封裝結構更滿足以下的不等式： F≦C。
  10. 如申請專利範圍第5項所述的半導體封裝結構，其中該第二介電層的材料為無機材料。
  11. 如申請專利範圍第1項所述的半導體封裝結構，其中該重佈線路結構包括複數個導電貫孔，該重佈線路層更包括複數個圖案化線路層，該些圖案化線路層與該些介電層彼此交替堆疊，且該些圖案化線路層透過該些導電貫孔與該些導電件電性連接。
  12. 如申請專利範圍第1項所述的半導體封裝結構，其中該上介電層的楊氏係數為A，該封裝膠層的楊氏係數為B，該第一介電層的楊氏係數為D， 其中，該半導體封裝結構更滿足以下的不等式： A/B＜1；以及 D/B＜1。
  13. 如申請專利範圍第1項所述的半導體封裝結構，其中該上介電層的楊氏係數為A，且該第一介電層的楊氏係數為D， 其中，該半導體封裝結構更滿足以下的不等式： A＜9吉帕(GPa)；以及 D＜9吉帕(GPa)。
  14. 如申請專利範圍第1項所述的半導體封裝結構，其中該封裝膠層的楊氏係數落在5吉帕(GPa)至15吉帕(GPa)的範圍內。
  15. 如申請專利範圍第1項所述的半導體封裝結構，其中該上介電層的圖案分布為非連續圖案。
  16. 如申請專利範圍第15項所述的半導體封裝結構，其中該上介電層中的一圖案的寬度大於該對應該圖案的該第一端與該金屬接墊接觸的開口的寬度的兩倍。
  17. 如申請專利範圍第1項所述的半導體封裝結構，其中該導電件的寬度為W，該導電件的高度為H， 其中，該半導體封裝結構更滿足以下的不等式： W/H＜1。
TW106131708A 2017-09-15 2017-09-15 半導體封裝結構 TWI636533B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW106131708A TWI636533B (zh) 2017-09-15 2017-09-15 半導體封裝結構
CN201711223474.2A CN109509724A (zh) 2017-09-15 2017-11-29 半导体封装结构
US15/849,593 US10461035B2 (en) 2017-09-15 2017-12-20 Semiconductor package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106131708A TWI636533B (zh) 2017-09-15 2017-09-15 半導體封裝結構

Publications (2)

Publication Number Publication Date
TWI636533B TWI636533B (zh) 2018-09-21
TW201916273A true TW201916273A (zh) 2019-04-16

Family

ID=64453187

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106131708A TWI636533B (zh) 2017-09-15 2017-09-15 半導體封裝結構

Country Status (3)

Country Link
US (1) US10461035B2 (zh)
CN (1) CN109509724A (zh)
TW (1) TWI636533B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI731517B (zh) * 2019-12-18 2021-06-21 財團法人工業技術研究院 軟性混合電子系統及降低此軟性混合電子系統衝擊的方法
US11270921B2 (en) * 2020-01-30 2022-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including dies having high-modulus dielectric layer and manufacturing method thereof

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440239A (en) 1994-04-25 1995-08-08 Rockwell International Corporation Transferable solder bumps for interconnect and assembly of MCM substrates
KR100216839B1 (ko) 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US6179198B1 (en) 1996-09-18 2001-01-30 Matsushita Electric Industrial Co., Ltd. Method of soldering bumped work by partially penetrating the oxide film covering the solder bumps
US20010024127A1 (en) 1998-03-30 2001-09-27 William E. Bernier Semiconductor testing using electrically conductive adhesives
JP3506233B2 (ja) 2000-06-28 2004-03-15 シャープ株式会社 半導体装置及びその製造方法
US6518675B2 (en) 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
JP4656275B2 (ja) 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
US6543674B2 (en) 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US20030034565A1 (en) 2001-08-18 2003-02-20 Lan James Jaen-Don Flip chip substrate with metal columns
KR100431181B1 (ko) 2001-12-07 2004-05-12 삼성전기주식회사 표면 탄성파 필터 패키지 제조방법
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
TW589727B (en) 2003-06-30 2004-06-01 Advanced Semiconductor Eng Bumping structure and fabrication process thereof
JP3811160B2 (ja) 2004-03-09 2006-08-16 株式会社東芝 半導体装置
US7312261B2 (en) 2004-05-11 2007-12-25 International Business Machines Corporation Thermal interface adhesive and rework
FR2876244B1 (fr) 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant muni d'un ensemble de micropointes conductrices dures et procede de connexion electrique entre ce composant et un composant muni de protuberances conductrices ductiles
KR100568496B1 (ko) 2004-10-21 2006-04-07 삼성전자주식회사 주석-인듐 합금층을 갖는 필름 회로 기판
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
DE102005046280B4 (de) 2005-09-27 2007-11-08 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip sowie Verfahren zur Herstellung desselben
KR100719905B1 (ko) 2005-12-29 2007-05-18 삼성전자주식회사 Ｓｎ-Ｂｉ계 솔더 합금 및 이를 이용한 반도체 소자
KR100713928B1 (ko) 2006-02-08 2007-05-07 주식회사 하이닉스반도체 반도체 칩 패키지
TW200839999A (en) * 2007-03-30 2008-10-01 Phoenix Prec Technology Corp Packaging substrate structure
WO2008144922A1 (en) 2007-06-01 2008-12-04 Trojan Technologies Ultraviolet radiation light emitting diode device
FR2928033B1 (fr) 2008-02-22 2010-07-30 Commissariat Energie Atomique Composant de connexion muni d'inserts creux.
TWI401775B (zh) * 2008-07-24 2013-07-11 Chipmos Technologies Inc 具基板支柱之封裝結構及其封裝方法
CN201421840Y (zh) * 2009-05-26 2010-03-10 江阴长电先进封装有限公司 低应力芯片凸点封装结构
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
TWI414047B (zh) * 2010-03-17 2013-11-01 Ind Tech Res Inst 電子元件封裝結構及其製造方法
KR101209980B1 (ko) * 2010-12-09 2012-12-07 주식회사 네패스 반도체 패키지 및 그 제조 방법
TWI418269B (zh) 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
US9137903B2 (en) * 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
FR2971081B1 (fr) 2011-02-02 2013-01-25 Commissariat Energie Atomique Procédé de fabrication de deux substrats relies par au moins une connexion mécanique et électriquement conductrice obtenue
TWI575684B (zh) * 2011-06-13 2017-03-21 矽品精密工業股份有限公司 晶片尺寸封裝件
US8373282B2 (en) 2011-06-16 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package with reduced stress on solder balls
US8912649B2 (en) * 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress
US8779588B2 (en) 2011-11-29 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for multi-chip packaging
DE112011105967T5 (de) 2011-12-20 2014-09-25 Intel Corporation Mikroelektronisches Gehäuse und gestapelte mikroelektronische Baugruppe und Rechensystem mit denselben
US8698308B2 (en) * 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
JPWO2014033977A1 (ja) 2012-08-29 2016-08-08 パナソニックＩｐマネジメント株式会社 半導体装置
FR3003688B1 (fr) 2013-03-22 2016-07-01 Commissariat Energie Atomique Procede d'assemblage flip chip comportant le pre-enrobage d'elements d'interconnexion
US9147661B1 (en) 2014-02-03 2015-09-29 Xilinx, Inc. Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same
US20160064254A1 (en) 2014-08-27 2016-03-03 Dyi-chung Hu High density ic package
TWI595613B (zh) 2014-11-18 2017-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
SE1650769A1 (sv) * 2016-06-01 2017-10-24 Fingerprint Cards Ab Fingerprint sensing device and method for manufacturing a fingerprint sensing device
TWI584428B (zh) * 2016-06-08 2017-05-21 力成科技股份有限公司 降低封裝翹曲之散熱型半導體封裝構造

Also Published As

Publication number Publication date
US20190088600A1 (en) 2019-03-21
US10461035B2 (en) 2019-10-29
CN109509724A (zh) 2019-03-22
TWI636533B (zh) 2018-09-21

Similar Documents

Publication Publication Date Title
US11626296B2 (en) Fan-out structure and method of fabricating the same
US11387183B2 (en) Semiconductor package having a semiconductor device bonded to a circuit substrate through connection terminals and dummy conductors and method of manufacturing the same
US10777531B2 (en) Package contact structure, semiconductor package and manufacturing method thereof
TWI710085B (zh) 半導體結構及其製造方法
US11913121B2 (en) Fabrication method of substrate having electrical interconnection structures
TWI442524B (zh) 覆晶封裝以及半導體晶片
US10818615B2 (en) Semiconductor structure
US8729700B2 (en) Multi-direction design for bump pad structures
US9941260B2 (en) Fan-out package structure having embedded package substrate
TWI569390B (zh) 電子封裝件及其製法
US20210167027A1 (en) Semiconductor Package
US11488894B2 (en) Semiconductor device having planarized passivation layer and method of fabricating the same
CN110896062B (zh) 再分布基板、制造再分布基板的方法和半导体封装件
TWI644401B (zh) 晶片封裝及其製造方法
TWI579984B (zh) 電子封裝件及其製法
TWI778961B (zh) 半導體結構及其製造方法
TWI636533B (zh) 半導體封裝結構
US9524944B2 (en) Method for fabricating package structure
US20140170850A1 (en) UBM Structures for Wafer Level Chip Scale Packaging
US20230411349A1 (en) Semiconductor device packages and methods of manufacturing the same
TWI647798B (zh) 電子封裝件及其製法
TWI600132B (zh) 電子封裝件及其製法
TWI549230B (zh) 半導體結構及其製法
US10535591B2 (en) Semiconductor device and method of manufacturing the same