TW201904019A - 具有阻抗分壓電路的半導體裝置 - Google Patents

具有阻抗分壓電路的半導體裝置 Download PDF

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TW201904019A
TW201904019A TW107110753A TW107110753A TW201904019A TW 201904019 A TW201904019 A TW 201904019A TW 107110753 A TW107110753 A TW 107110753A TW 107110753 A TW107110753 A TW 107110753A TW 201904019 A TW201904019 A TW 201904019A
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南志昌
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日商艾普凌科有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605Resistors with PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本發明能夠形成如下的阻抗分壓電路,即,由於N型多晶矽與P型多晶矽對於應力顯示出反方向的偏移量,故若阻抗分壓電路的全部阻抗是將N型多晶矽與P型多晶矽交替配置且並聯或串聯連接而構成,則利用各個阻抗自身便能夠消除安裝時從樹脂接收的應力,因而較之先前可減少安裝時的分壓比變動。

Description

具有阻抗分壓電路的半導體裝置
本發明是有關於一種具有阻抗分壓電路的半導體裝置。
對於作為定電壓輸出積體電路(integrated circuit,IC)或鋰電池保護IC等類比IC的電源IC,近年來要求輸出電壓或監控電壓的進一步的高精度化,其精度為±1%或±0.5%,或者為±1%或±0.5%以上。為了實現高精度,而採用如下方法等,即,在晶圓測試步驟(後步驟)中,藉由雷射等選擇性地切斷多晶矽製保險絲來修整(trimming)晶圓製造步驟(前步驟)階段中所發生的製造差異,而校準特性值。
使用圖4對使用了阻抗分壓電路的定電壓輸出電路的一例進行說明。定電壓輸出電路包含基準電壓生成電路、放大器、阻抗分壓電路及輸出電晶體。定電壓輸出電路供給一定的輸出電壓。放大器接收來自基準電壓生成電路及阻抗分壓電路的兩個輸入電壓,且以該兩個電壓相等的方式動作。例如,若基準電壓為1.0 V,阻抗分壓電路的分壓比為1:1,則定電壓輸出電路的輸出電壓為2.0 V。若所要求的定電壓輸出電路的輸出電壓的精度為±1%,則輸出電壓必須處於±1%的範圍,即1.98 V~2.02 V的範圍。高精度地校準該輸出電壓的值的是阻抗分壓電路。
將阻抗分壓電路的原理表示於圖5。與利用植入了P型雜質的多晶矽6製作而成的阻抗1並聯而配置著修整用的保險絲2。藉由切斷保險絲2來調整阻抗分壓電路的分壓比,而高精度地實現輸出電壓的校準。
圖6中表示阻抗分壓電路的具體的構成。所述阻抗分壓電路是將單位阻抗設為1R,組合著單位阻抗的阻抗構件即1/8R 7、1/4R 8、1/2R 9、1R 10、2R 11、4R 12、Rref(A) 13、及Rref(B) 14串聯連接而成的電路。此處,阻抗構件1/8R 7由8個1R的並聯連接而實現,阻抗構件4R 12由4個1R的串聯連接而實現。其他也相同,均包含同型的單位阻抗。即,該些多個阻抗構件分別具有利用二進制加權的阻抗值。而且,阻抗分壓電路中,多個保險絲2與Rref(A) 13、Rref(B) 14以外的各個阻抗構件並聯連接。藉由選擇性地切斷保險絲2並調整阻抗分壓電路的分壓比,而實現輸出電壓的校準。
然而,即便是如此高精度製作而成的晶圓,在包裝(packaging)步驟或對印刷基板的安裝步驟中有時會發生特性變化,會出現視情況而不滿足製品規格的情形。包裝步驟或基板安裝步驟中的特性變化的原因是由熱應力引起的元件特性的變化,認為是壓電阻抗效果。即,藉由經過該些步驟而應力施加至半導體晶圓,或因被施加的熱而應力的施加方式發生變化,由此多晶矽阻抗的阻抗值或電晶體的臨限值電壓等發生變化。在安裝到印刷基板後可調整半導體製品的特性的發明用於防止所述變化(例如參照專利文獻1)。然而,專利文獻1記載的步驟複雜,期望更簡單的特性值的穩定化方法。 [現有技術文獻] [專利文獻]
[專利文獻1]日本專利特開2000-124343號公報
[發明所欲解決之課題] 對於類比IC的包裝而言,近年來,因零件的小型化要求,盛行安裝到小型封裝體,而伴隨此,亦推進半導體晶圓的薄型化。半導體晶圓越薄型化,施加相同應力的情況下,半導體晶圓應變越大,從而有發生更大的特性變化的擔心。
阻抗分壓電路發揮著在定電壓輸出電路中高精度地校準輸出電壓的作用。不均勻的應力施加至阻抗分壓電路,分壓比例如理想應為1:1,但由於是1:1.02,所以不滿足輸出電壓的精度±1%。
本發明的目的在於提供一種能夠減小由該些應力引起的分壓比變動的阻抗分壓電路。 [解決課題之手段]
本發明為了解決所述課題,是一種具有阻抗分壓電路的半導體裝置,其特徵在於包括: 多個阻抗構件,串聯連接且分別具有以二進制加權的阻抗值;以及 多個短路控制元件,與所述多個阻抗構件分別對應地設置,分別對所述多個阻抗構件的短路進行控制; 所述多個阻抗構件分別是將N型多晶矽與P型多晶矽交替配置且串聯或並聯連接而構成。 [發明的效果]
由於N型多晶矽與P型多晶矽對於應力顯示出反方向的偏移量,故構成阻抗分壓電路的全部阻抗是將N型多晶矽與P型多晶矽交替配置且並聯或串聯連接而構成,由此利用各個阻抗自身便能夠消除安裝時從樹脂接收的應力從而較之先前可減少阻抗分壓電路的安裝時的分壓比變動。
以下,參照圖式對本發明的實施形態進行說明。 本實施形態中,如下方面與先前相同,即,配置構成阻抗分壓電路的阻抗構件1/8R 7、1/4R 8、1/2R 9、1R 10、2R 11、4R 12、Rref(A) 13及Rref(B) 14且將各個阻抗構件串聯連接。不同點在於:當構成各個阻抗構件時,先前如使用圖6說明般,所有阻抗是使用植入了P型雜質的多晶矽6而形成,與此相對,本實施形態中,例如,若為1/8R 7,則是將包含植入了N型雜質的多晶矽5的單位阻抗與包含植入了P型雜質的多晶矽6的單位阻抗交替配置,且經由接點4並利用金屬配線3並聯連接而製作,若為4R 12,則是藉由將植入了N型雜質的多晶矽5與植入了P型雜質的多晶矽6交替地配置,且經由接點4並利用金屬配線3串聯連接而製作。其他阻抗亦同樣地製作。
然而,關於阻抗構件1R 10,可藉由將設為構成其他阻抗的1R的長度一半的N型短條多晶矽15與P型短條多晶矽16串聯連接而包含N型多晶矽與P型多晶矽。據此,可將N型多晶矽與P型多晶矽以相同數量組合而構成全部的阻抗構件。進而,除阻抗構件1R 10外的其他阻抗構件包含相同形狀的單位阻抗。
將阻抗構件1R 10的其他構成方法表示於圖2。圖2中,將與其他單位阻抗同型的N型多晶矽5與P型多晶矽6逐個並聯連接而獲得的1/2R串聯連接兩個,由此構成阻抗構件1R 10。該構成方法中,全部阻抗構件能夠包括具有相同形狀的包含N型多晶矽5的單位阻抗及包含P型多晶矽6的單位阻抗。包含N型多晶矽5的單位阻抗與包含P型多晶矽6的單位阻抗較佳為具有相同的阻抗值,但即便不具有相同的阻抗值,由於全部阻抗構件包括相同數量的包含N型多晶矽5的單位阻抗及包含P型多晶矽6的單位阻抗,故阻抗值之比可正確地設定,而不會有問題。
如圖3所示,確認N型多晶矽5與P型多晶矽6對於安裝時從樹脂接收的應力,安裝前後的阻抗值的變動(偏移方向)具有為相反方向的傾向。本發明利用了該傾向。如此,由於N型多晶矽5與P型多晶矽6對於應力顯示出相反方向的偏移量,故藉由將N型多晶矽5與P型多晶矽6交替配置且並聯或串聯連接而構成阻抗,以各個阻抗構件自身便能夠消除安裝時從樹脂接收的應力。由此,因零件的小型化要求而推進半導體晶圓的薄型化,即便更大的應力施加至半導體晶圓,亦能夠消除應力,從而可維持由阻抗分壓電路高精度設定的分壓比。
1‧‧‧阻抗
2‧‧‧修整用保險絲(保險絲)
3‧‧‧金屬配線
4‧‧‧接點
5‧‧‧N型多晶矽
6‧‧‧P型多晶矽
7‧‧‧1/8R
8‧‧‧1/4R
9‧‧‧1/2R
10‧‧‧1R
11‧‧‧2R
12‧‧‧4R
13‧‧‧Rref(A)
14‧‧‧Rref(B)
15‧‧‧N型短條多晶矽
16‧‧‧P型短條多晶矽
圖1是表示本發明的阻抗分壓電路的圖。 圖2是表示本發明的阻抗分壓電路的圖。 圖3是表示N型多晶矽與P型多晶矽的安裝前後的阻抗值偏移率的圖。 圖4是表示定電壓輸出電路的圖。 圖5是表示阻抗分壓電路的示意圖。 圖6是表示先前的阻抗分壓電路的圖。

Claims (3)

  1. 一種具有阻抗分壓電路的半導體裝置,其特徵在於包括: 多個阻抗構件,串聯連接且分別具有以二進制加權的阻抗值;以及 多個短路控制元件,與所述多個阻抗構件分別對應地設置,分別對所述多個阻抗構件的短路進行控制; 所述多個阻抗構件分別是將N型多晶矽與P型多晶矽交替配置且串聯或並聯連接而構成。
  2. 如申請專利範圍第1項所述的具有阻抗分壓電路的半導體裝置,其中 所述多個阻抗構件中的與所述以二進制加權的阻抗值的1對應的阻抗構件是藉由如下而構成,即,將具有構成其他阻抗構件的N型多晶矽的長度的1/2的長度的N型短條多晶矽與具有構成其他阻抗構件的P型多晶矽的長度的1/2的長度的P型短條多晶矽串聯連接。
  3. 如申請專利範圍第1項所述的具有阻抗分壓電路的半導體裝置,其中 所述多個阻抗構件中的與所述以二進制加權的阻抗值的1對應的阻抗構件是將構成其他阻抗構件的N型多晶矽與構成其他阻抗構件的P型多晶矽逐個地並聯連接而成者串聯連接兩個而構成。
TW107110753A 2017-03-30 2018-03-28 具有阻抗分壓電路的半導體裝置 TW201904019A (zh)

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US5663860A (en) * 1996-06-28 1997-09-02 Harris Corporation High voltage protection circuits
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JP2002043916A (ja) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd 電圧検出回路および半導体装置
JP3539373B2 (ja) * 2000-09-06 2004-07-07 セイコーエプソン株式会社 半導体装置
JP2002124629A (ja) * 2000-10-13 2002-04-26 Seiko Instruments Inc 半導体装置
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JP2010118548A (ja) * 2008-11-13 2010-05-27 Mitsubishi Electric Corp 半導体装置
JP5477407B2 (ja) * 2012-02-16 2014-04-23 株式会社デンソー ゲート駆動回路
JP6014357B2 (ja) * 2012-04-26 2016-10-25 ルネサスエレクトロニクス株式会社 半導体装置
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