CN108695318A - 具有电阻分压电路的半导体装置 - Google Patents
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Abstract
本发明提供具有电阻分压电路的半导体装置，N型多晶硅和P型多晶硅相对于应力显示出相反方向的偏移量，因此若电阻分压电路的所有电阻是将N型多晶硅和P型多晶硅交替配置并并联或串联连接而构成的，则利用各个电阻本身将安装时从树脂受到的应力消除，因此能够制成比以往降低安装时的分压比变动的电阻分压电路。
Description
技术领域
本发明涉及具有电阻分压电路的半导体装置。
背景技术
对于恒压输出IC、锂电池保护IC等作为模拟IC的电源IC而言，近年来，进一步要求输出电压或监视电压的高精度化，其精度为±1％或±0.5％、或者在此之上。为了实现高精度，采用下述方法等：在晶片测试工序(后工序)中通过激光等选择地切断多晶硅制的熔断器而对在晶片制造工序(前工序)阶段所产生的制造偏差进行修整，从而调节特性值。
使用图4对采用了电阻分压电路的恒压输出电路的一例进行说明。恒压输出电路由基准电压生成电路、放大器、电阻分压电路以及输出晶体管构成。恒压输出电路供给恒定的输出电压。放大器接收来自基准电压生成电路和电阻分压电路的这两个输入电压，并进行工作，以使得这两个电压相等。例如当基准电压为1.0V且电阻分压电路的分压比为1:1时，恒压输出电路的输出电压为2.0V。当所要求的恒压输出电路的输出电压的精度为±1％时，输出电压需要在±1％的范围，即在1.98V～2.02V的范围内。电阻分压电路高精度地调节该输出电压的值。
图5中示出电阻分压电路的原理。在利用注入了P型杂质的多晶硅6制作的电阻1上并联地配置有修整用的熔断器2。通过将熔断器2切断来调整电阻分压电路的分压比，从而高精度地实现输出电压的调节。
图6中示出电阻分压电路的具体结构。电阻分压电路是将单位电阻设为1R而将单位电阻组合而成的作为电阻要素的1/8R7、1/4R8、1/2R9、1R10、2R11、4R12、Rref(A)13以及Rref(B)14串联连接的电路。这里，电阻要素1/8R7是通过8个1R的并联连接而实现的，电阻要素4R12是通过4个1R的串联连接而实现的。其他也同样，均由同型的单位电阻构成。即，这些多个电阻要素分别具有利用二进制法进行赋予权重的电阻值。另外，在电阻分压电路中与除了Rref(A)13、Rref(B)14以外的各个电阻要素并联连接有多个熔断器2。通过选择地切断熔断器2，调整电阻分压电路的分压比，可实现输出电压的调节。
但是，即使是如此高精度地制成的芯片，在封装工序或对印刷基板的安装工序中有时也产生特性变化，根据场合产生不满足制品规格的情况。封装工序或基板安装工序中的特性变化的原因是热应力所导致的元件特性的变化，被认为是压电电阻效应。即，由于经过这些工序而对半导体芯片施加应力、或者由于所施加的热使应力的施加方式发生变化，从而多晶硅电阻的电阻值或晶体管的阈值电压等发生变化。为了防止这些变化，完成了在对印刷基板的安装后能够预先调整半导体制品的特性的发明(例如，参照专利文献1)。但是，专利文献1所述的工序复杂，期望更简单的特性值的稳定化方法。
专利文献1：日本特开2000-124343号公报
对于模拟IC的封装而言，近年来，随着部件的小型化要求，正在盛行对小型的封装件的安装，与之相伴，半导体芯片的薄型化也在不断发展。半导体芯片越薄型化，则在施加相同的应力的情况下，越担心半导体芯片更大地变形、产生更大的特性变化。
电阻分压电路起到在恒压输出电路中高精度地调节输出电压的较大作用。对电阻分压电路施加不均匀的应力，分压比例如理想应该为1:1，但由于变为1:1.02，而不满足输出电压的精度±1％。
发明内容
本发明的目的在于提供电阻分压电路，能够降低由于这些应力所导致的分压比变动。
本发明为了解决上述课题，提供具有电阻分压电路的半导体装置，其特征在于，该具有电阻分压电路的半导体装置具有：
多个电阻要素，它们串联连接，并且分别具有利用二进制法赋予权重得到的电阻值；以及
多个短接控制元件，它们分别与所述多个电阻要素对应地设置，分别对所述多个电阻要素的短接进行控制，
所述多个电阻要素分别是将N型多晶硅与P型多晶硅交替配置并串联或并联连接而构成的。
N型多晶硅与P型多晶硅相对于应力显示出相反方向的偏移量，因此构成电阻分压电路的所有电阻是通过将N型多晶硅与P型多晶硅交替配置并并联或串联连接而构成的，能够利用各个电阻本身将安装时从树脂受到的应力消除，能够比以往降低电阻分压电路的安装时的分压比变动。
附图说明
图1是示出本发明的电阻分压电路的图。
图2是示出本发明的电阻分压电路的图。
图3是示出N型多晶硅和P型多晶硅在安装前后的电阻值偏移率的图。
图4是示出恒压输出电路的图。
图5是示出电阻分压电路的示意图。
图6是示出以往的电阻分压电路的图。
标号说明
1：电阻；2：修整用熔断器；3：金属配线；4：触点；5：N型多晶硅；6：P型多晶硅；7：1/8R；8：1/4R；9：1/2R；10：1R；11：2R；12：4R；13：Rref(A)；14：Rref(B)。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
本实施方式在配置构成电阻分压电路的电阻要素1/8R7、1/4R8、1/2R9、1R10、2R11、4R12、Rref(A)13以及Rref(B)14并将各个电阻要素串联连接的方面与以往是相同的。不同的方面在于，在构成各个电阻要素时，以往如使用图6所说明的那样，所有电阻均采用注入有P型杂质的多晶硅6来形成，与此相对，在本实施方式中，例如对于1/8R7，是以如下方式制作而成的：将由注入有N型杂质的多晶硅5构成的单位电阻和由注入有P型杂质的多晶硅6构成的单位电阻交替配置，并利用金属配线3经由触点4并联连接起来，对于4R12，是以如下方式制作而成的：通过将注入有N型杂质的多晶硅5和注入有P型杂质的多晶硅6交替配置，并利用金属配线3经由触点4串联连接起来。其他电阻也同样地制作而成。
但是，关于电阻要素1R10，通过将构成其他电阻的1R的长度减半的N型短尺寸多晶硅15和P型短尺寸多晶硅16串联连接，而能够由N型多晶硅和P型多晶硅构成。这样，能够组合相同数量的N型多晶硅和P型多晶硅来构成所有电阻要素。另外，除了电阻要素1R10以外的其他电阻要素也由相同形式的单位电阻构成。
图2中示出电阻要素1R10的其他构成方法。在图2中，将并联连接与其他单位电阻同型的一个N型多晶硅5和一个P型多晶硅6而得到的1/2R串联连接两个，从而构成电阻要素1R10。在该构成方法中，所有电阻要素能够由具有相同形式的、由N型多晶硅5构成的单位电阻和由P型多晶硅6构成的单位电阻构成。优选由N型多晶硅5构成的单位电阻和由P型多晶硅6构成的单位电阻具有相同的电阻值，但也可以不具有相同的电阻值，所有电阻要素由相同数量的由N型多晶硅5构成的单位电阻和由P型多晶硅6构成的单位电阻构成，因此能够正确地设定电阻值之比，没有问题。
如图3所示，确认到：N型多晶硅5和P型多晶硅6的安装前后的电阻值的变动(偏移方向)具有相对于安装时从树脂受到的应力成为相反方向的趋势。本发明利用了该趋势。这样，N型多晶硅5和P型多晶硅6相对于应力显示出相反方向的偏移量，因此通过将N型多晶硅5和P型多晶硅6交替配置并并联或串联连接而构成电阻，能够利用各个电阻要素本身将安装时从树脂受到的应力消除。由此，即使随着部件的小型化要求，半导体芯片的薄型化不断发展，更大的应力施加于半导体芯片，也能够将应力消除，利用电阻分压电路维持高精度地设定的分压比。
Claims (3)
1.一种具有电阻分压电路的半导体装置，其特征在于，该具有电阻分压电路的半导体装置具有：
多个电阻要素，它们串联连接，并且分别具有利用二进制法赋予权重得到的电阻值；以及
多个短接控制元件，它们分别与所述多个电阻要素对应地设置，分别对所述多个电阻要素的短接进行控制，
所述多个电阻要素分别是将N型多晶硅和P型多晶硅交替配置并串联或并联连接而构成的。
2.根据权利要求1所述的具有电阻分压电路的半导体装置，其中，
在所述多个电阻要素中，与利用所述二进制法赋予权重得到的电阻值的1对应的电阻要素是将N型短尺寸多晶硅和P型短尺寸多晶硅串联连接起来而构成的，其中，所述N型短尺寸多晶硅具有构成其他电阻要素的N型多晶硅的长度的1/2长度，所述P型短尺寸多晶硅具有构成其他电阻要素的P型多晶硅的长度的1/2长度。
3.根据权利要求1所述的具有电阻分压电路的半导体装置，其中，
在所述多个电阻要素中，与利用所述二进制法赋予权重得到的电阻值的1对应的电阻要素是串联地连接两个如下这样的结构而构成的：所述结构是将构成其他电阻要素的一个N型多晶硅和构成其他电阻要素的一个P型多晶硅并联连接而得到的。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017-068173 | 2017-03-30 | ||
| JP2017068173A JP2018170457A (ja) | 2017-03-30 | 2017-03-30 | 抵抗分圧回路を有する半導体装置 |
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| CN108695318A true CN108695318A (zh) | 2018-10-23 |
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| US (1) | US10205031B2 (zh) |
| JP (1) | JP2018170457A (zh) |
| KR (1) | KR20180111645A (zh) |
| CN (1) | CN108695318A (zh) |
| TW (1) | TW201904019A (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112530936A (zh) * | 2020-11-25 | 2021-03-19 | 清华大学 | 集成电路细致修调电阻阵列版图结构 |
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2017
- 2017-03-30 JP JP2017068173A patent/JP2018170457A/ja active Pending
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2018
- 2018-03-27 US US15/936,556 patent/US10205031B2/en not_active Expired - Fee Related
- 2018-03-28 CN CN201810263325.7A patent/CN108695318A/zh not_active Withdrawn
- 2018-03-28 TW TW107110753A patent/TW201904019A/zh unknown
- 2018-03-29 KR KR1020180036525A patent/KR20180111645A/ko unknown
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| US20020066912A1 (en) * | 2000-09-06 | 2002-06-06 | Masahiko Tsuchiya | Semiconductor device |
| US20020096739A1 (en) * | 2000-10-13 | 2002-07-25 | Hiroaki Takasu | Semiconductor device |
| US20020180453A1 (en) * | 2001-05-14 | 2002-12-05 | Kohzoh Itoh | Resistance hybrid, and voltage detection and constant voltage generating circuits incorporating such resistance hybrid |
| US20050285227A1 (en) * | 2004-06-29 | 2005-12-29 | Hiroaki Takasu | Semiconductor device |
| US20090212749A1 (en) * | 2008-02-26 | 2009-08-27 | Ricoh Company, Ltd. | Semiconductor device and voltage divider circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112530936A (zh) * | 2020-11-25 | 2021-03-19 | 清华大学 | 集成电路细致修调电阻阵列版图结构 |
| CN112530936B (zh) * | 2020-11-25 | 2022-03-18 | 清华大学 | 集成电路细致修调电阻阵列版图结构 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180286990A1 (en) | 2018-10-04 |
| JP2018170457A (ja) | 2018-11-01 |
| TW201904019A (zh) | 2019-01-16 |
| US10205031B2 (en) | 2019-02-12 |
| KR20180111645A (ko) | 2018-10-11 |
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