JP5341543B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5341543B2 JP5341543B2 JP2009026501A JP2009026501A JP5341543B2 JP 5341543 B2 JP5341543 B2 JP 5341543B2 JP 2009026501 A JP2009026501 A JP 2009026501A JP 2009026501 A JP2009026501 A JP 2009026501A JP 5341543 B2 JP5341543 B2 JP 5341543B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- region
- amorphous
- channel
- amorphous region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
また、前記アモルファス領域は、前記チャネル領域と略同じであることを特徴とする半導体装置とする。
10 P型ウェル領域
12 N型ウェル領域
20 ゲート酸化膜
22 ゲート電極
30 N型ソース・ドレイン領域
32 N型LDD領域
40 P型ソース・ドレイン領域
42 P型LDD領域
101 チャネル領域
102 アモルファス領域
Claims (5)
- 単結晶のシリコン基板と、
前記シリコン基板上に形成されたカレントミラー回路の対を形成する複数のMOSトランジスタと、を有し、
前記複数のMOSトランジスタの動作時に形成されるチャネル領域の深さよりも深く、前記複数のMOSトランジスタのソース・ドレイン領域の深さよりも浅いアモルファス領域を前記チャネル領域のみに有することを特徴とする半導体装置。 - 前記アモルファス領域は、前記チャネル領域と略同じ位置に配置されていることを特徴とする請求項1記載の半導体装置。
- 前記アモルファス領域は、アルゴンなどの希ガス元素のイオン注入により形成されたことを特徴とする請求項1または請求項2記載の半導体装置。
- 前記アモルファス領域は、シリコン原子のイオン注入にて形成したことを特徴とする請求項1または請求項2記載の半導体装置。
- 前記アモルファス領域は、堆積により形成されたアモルファスシリコン層であることを特徴とする請求項1または請求項2記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009026501A JP5341543B2 (ja) | 2009-02-06 | 2009-02-06 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009026501A JP5341543B2 (ja) | 2009-02-06 | 2009-02-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010182953A JP2010182953A (ja) | 2010-08-19 |
JP5341543B2 true JP5341543B2 (ja) | 2013-11-13 |
Family
ID=42764265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009026501A Expired - Fee Related JP5341543B2 (ja) | 2009-02-06 | 2009-02-06 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5341543B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013055238A (ja) * | 2011-09-05 | 2013-03-21 | Seiko Instruments Inc | 半導体装置 |
JP5777455B2 (ja) * | 2011-09-08 | 2015-09-09 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
CN114812878B (zh) * | 2022-04-07 | 2023-07-07 | 中北大学 | 一种高灵敏度压阻敏感单元及其制造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63142866A (ja) * | 1986-12-05 | 1988-06-15 | Nec Corp | 絶縁ゲ−ト電界効果トランジスタの製造方法 |
JP2666322B2 (ja) * | 1988-01-25 | 1997-10-22 | 富士通株式会社 | 電界効果型トランジスタ |
JPH06204419A (ja) * | 1992-12-28 | 1994-07-22 | Seiko Instr Inc | 半導体装置の製造方法 |
JP3395522B2 (ja) * | 1996-05-15 | 2003-04-14 | 株式会社豊田中央研究所 | 半導体装置およびその製造方法 |
JP2907128B2 (ja) * | 1996-07-01 | 1999-06-21 | 日本電気株式会社 | 電界効果型トランジスタ及びその製造方法 |
JP2005086120A (ja) * | 2003-09-11 | 2005-03-31 | Matsushita Electric Ind Co Ltd | 半導体装置 |
WO2007080647A1 (ja) * | 2006-01-13 | 2007-07-19 | Fujitsu Limited | 半導体装置の製造方法 |
-
2009
- 2009-02-06 JP JP2009026501A patent/JP5341543B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010182953A (ja) | 2010-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7217611B2 (en) | Methods for integrating replacement metal gate structures | |
US8969151B2 (en) | Integrated circuit system employing resistance altering techniques | |
US20080102650A1 (en) | Method of fabricating a nitrided silicon oxide gate dielectric layer | |
KR20090086329A (ko) | 반도체 장치 | |
KR20080057143A (ko) | 선택적으로 스트레스가 인가되어 안정도가 향상된sram셀을 포함하는 집적 회로 | |
US20100078645A1 (en) | Semiconductor device comprising a buried poly resistor | |
US9837439B1 (en) | Compensation of temperature effects in semiconductor device structures | |
US20130200466A1 (en) | Integrated circuit having silicide block resistor | |
JP5341543B2 (ja) | 半導体装置 | |
US8686478B2 (en) | Methods of forming and programming an electronically programmable resistor | |
JP2005049299A (ja) | 半導体素子の評価方法 | |
US9082662B2 (en) | SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask | |
US20070210421A1 (en) | Semiconductor device fabricated using a carbon-containing film as a contact etch stop layer | |
US20160064123A1 (en) | Temperature independent resistor | |
US7906819B2 (en) | Semiconductor device and method for producing the same | |
JP4717246B2 (ja) | 半導体装置 | |
US7335518B2 (en) | Method for manufacturing semiconductor device | |
JP2001320019A (ja) | 半導体装置の製造方法 | |
JP2013055238A (ja) | 半導体装置 | |
US9899319B2 (en) | Raised e-fuse | |
US6653688B2 (en) | Semiconductor device | |
JP2014145596A (ja) | 磁気センサ及び磁気センサの製造方法 | |
WO2008099565A1 (ja) | 半導体装置およびその製造方法 | |
US8669156B2 (en) | Method of manufacturing semiconductor circuit device | |
US20070164362A1 (en) | System and method for I/O ESD protection with floating and/or biased polysilicon regions |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20111205 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130423 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130425 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130620 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130730 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130808 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5341543 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |