TW201817087A - 各向異性導電材、電子元件、含半導體元件的結構體及電子元件的製造方法 - Google Patents

各向異性導電材、電子元件、含半導體元件的結構體及電子元件的製造方法 Download PDF

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Publication number
TW201817087A
TW201817087A TW106113345A TW106113345A TW201817087A TW 201817087 A TW201817087 A TW 201817087A TW 106113345 A TW106113345 A TW 106113345A TW 106113345 A TW106113345 A TW 106113345A TW 201817087 A TW201817087 A TW 201817087A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
anisotropic conductive
region
conductive member
electronic component
Prior art date
Application number
TW106113345A
Other languages
English (en)
Chinese (zh)
Inventor
堀田吉則
山下広祐
Original Assignee
富士軟片股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士軟片股份有限公司 filed Critical 富士軟片股份有限公司
Publication of TW201817087A publication Critical patent/TW201817087A/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • H01L23/4922Bases or plates or solder therefor having a heterogeneous or anisotropic structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R11/00Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
    • H01R11/01Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the form or arrangement of the conductive interconnection between the connecting locations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)
  • Laminated Bodies (AREA)
TW106113345A 2016-05-27 2017-04-21 各向異性導電材、電子元件、含半導體元件的結構體及電子元件的製造方法 TW201817087A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2016106384 2016-05-27
JP2016-106384 2016-05-27
JP2016156297 2016-08-09
JP2016-156297 2016-08-09

Publications (1)

Publication Number Publication Date
TW201817087A true TW201817087A (zh) 2018-05-01

Family

ID=60411231

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106113345A TW201817087A (zh) 2016-05-27 2017-04-21 各向異性導電材、電子元件、含半導體元件的結構體及電子元件的製造方法

Country Status (5)

Country Link
JP (1) JP6663487B2 (ja)
KR (1) KR102134135B1 (ja)
CN (1) CN109155259B (ja)
TW (1) TW201817087A (ja)
WO (1) WO2017203884A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677271B (zh) * 2018-08-31 2019-11-11 欣興電子股份有限公司 線路基板及其製作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114207793A (zh) * 2019-08-16 2022-03-18 富士胶片株式会社 结构体的制造方法
JP7357142B2 (ja) * 2020-03-06 2023-10-05 富士フイルム株式会社 充填微細構造体および搬送方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094222A (ja) * 2000-09-19 2002-03-29 Matsushita Electric Ind Co Ltd 電子部品接合用シート、電子部品実装方法、及び電子部品実装装置
JP5043621B2 (ja) * 2007-03-27 2012-10-10 富士フイルム株式会社 異方導電性部材およびその製造方法
JP2008124029A (ja) * 2007-11-26 2008-05-29 Hitachi Chem Co Ltd 接続部材
JP5145110B2 (ja) * 2007-12-10 2013-02-13 富士フイルム株式会社 異方導電性接合パッケージの製造方法
JP2011090865A (ja) * 2009-10-22 2011-05-06 Shinko Electric Ind Co Ltd 導電フィルムおよびその製造方法、並びに半導体装置およびその製造方法
JP5620865B2 (ja) * 2011-03-28 2014-11-05 信越ポリマー株式会社 異方導電性シート
KR20140100511A (ko) * 2011-12-16 2014-08-14 아사히 가세이 이-매터리얼즈 가부시키가이샤 이방 도전성 필름 부착 반도체칩, 이방 도전성 필름 부착 반도체 웨이퍼, 및 반도체 장치
JPWO2016006660A1 (ja) 2014-07-11 2017-04-27 富士フイルム株式会社 異方導電性部材および多層配線基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI677271B (zh) * 2018-08-31 2019-11-11 欣興電子股份有限公司 線路基板及其製作方法

Also Published As

Publication number Publication date
CN109155259B (zh) 2023-02-28
KR102134135B1 (ko) 2020-07-15
CN109155259A (zh) 2019-01-04
JPWO2017203884A1 (ja) 2019-02-21
KR20180134970A (ko) 2018-12-19
JP6663487B2 (ja) 2020-03-11
WO2017203884A1 (ja) 2017-11-30

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