TW201806148A - 半導體器件及其形成方法 - Google Patents

半導體器件及其形成方法 Download PDF

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TW201806148A
TW201806148A TW106106101A TW106106101A TW201806148A TW 201806148 A TW201806148 A TW 201806148A TW 106106101 A TW106106101 A TW 106106101A TW 106106101 A TW106106101 A TW 106106101A TW 201806148 A TW201806148 A TW 201806148A
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gate structure
well region
dielectric layer
conductivity type
conductive layer
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TWI656639B (zh
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林振華
季彥良
熊志文
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體器件及其形成方法。其中該半導體器件包括：一半導體基底，一第一阱區，一第二阱區，一第一閘極結構，一第一摻雜區，一第二摻雜區，以及一第二閘極結構。該第一阱區形成於該半導體基底中。該第二阱區形成於該第一阱區中。該第一閘極結構形成於該第二阱區的一部分和該第一阱區的一部分上。該第一摻雜區形成於該第二阱區中。該第二摻雜區形成於該第一阱區中。該第二閘極結構形成於該第一閘極結構的一部分和該第一阱區的一部分上。

Description

半導體器件及其形成方法
本發明涉及IC(Integrated Circuits，積體電路)，特別係涉及一種能夠高電壓操作的半導體器件及其形成方法。
近年來，隨著對高壓器件(諸如功率半導體器件)的需求增加，業界對應用於高壓器件中的HV MOSFET(High-Voltage Metal-Oxide-Semiconductor Field Effect Transistors，高電壓金屬氧化物半導體場效應電晶體)的研究已越來越有興趣。
在各種類型的HV MOSFET中，一般經常使用諸如LDMOS(Lateral Double Diffused Metal-Oxide-Semiconductor，橫向擴散金屬氧化物半導體)等半導體器件。
但是，隨著半導體製造的發展，需要進一步增加用於高壓器件的HV MOSFET的崩潰電壓(breakdown voltage)。如此，由於持續對高壓器件的半導體製造的需要，因此需要可靠的具有增強的崩潰電壓的高壓MOSFET來滿足設備性能要求，該高壓MOSFET用於高壓器件。
因此，本發明之主要目的即在於提供一種半導體器件及其形成方法，可以進行高壓操作。
根據本發明至少一個實施例一種半導體器件，包括：一半導體基底，具有一第一導電類型；一第一阱區，形成於該半導體基底中並且具有一第二導電類型，該第二導電類型相反於該第一導電類型；一第二阱區，形成於該第一阱區中並且具有該第一導電類型；一第一閘極結構，形成於該第二阱區和該第一阱區上；一第一摻雜區，形成於該第二阱區中並且具有該第二導電類型；一第二摻雜區，形成於該第一阱區中並且具有該第二導電類型；以及一第二閘極結構，形成於該第一閘極結構的一部分和第一阱區的一部分上。
根據本發明至少一個實施例一種形成半導體器件的方法，包括：提供一半導體結構，該半導體結構包括：一半導體基底，具有一第一導電類型；一第一阱區，形成於該半導體基底的位於第一區域中的一部分中並且具有一第二導電類型，該第二導電類型相反於該第一導電類型；一第二阱區，形成於該第一阱區中並且具有該第一導電類型；一第一閘極結構，形成於該第二阱區和該第一阱區上；一第一摻雜區，形成於該第二阱區中並且具有該第二導電類型；一第二摻雜區，形成於該第一阱區中並且具有該第二導電類型；以及，形成一第二閘極結構，位於該第一閘極結構的一部分和該第一阱區的一部分上。
本發明實施例，通過將第二閘極結構形成於第一閘極結構的一部分和第一阱區的一部分上，從而使得半導體器 件可以進行高電壓操作。
A、B‧‧‧區域
100‧‧‧半導體基底
108‧‧‧隔離元件
102‧‧‧深阱區
104、106、110、112‧‧‧阱區
114、116‧‧‧摻雜區
G1、G2、G3、G4‧‧‧閘極結構
118、122、122a、122b‧‧‧介電層
120、124、124a、124b‧‧‧導電層
126a、126b‧‧‧遮罩層
128、129‧‧‧蝕刻製程
128a、128b、128c、128d‧‧‧導電接觸結構
130a、130b、130c‧‧‧導電線
通過閱讀接下來的詳細描述以及參考所附的圖式所做的示例，能夠更全面地理解本發明，其中：第1~6圖為剖面示意圖，用來示出根據本發明實施例的半導體器件的形成方法的各個中間階段。
以下描述為實現本發明的較佳方式。該描述僅係說明本發明一般原理的目的，而不應視為限制。本發明的範圍最好通過參考所附的申請專利範圍來確定。
第1~6圖為剖面示意圖，示出了根據本發明實施例的半導體器件的形成方法的各個中間階段。通過第1~6圖所示的方法形成的半導體器件包括：一能夠高壓(例如，100V)操作的HV MOSFET。
在第1圖中，提供了一大致製造好的半導體結構。如第1圖所示，該提供的半導體結構具有兩個區域A和B。區域A與區域B相鄰或者區域A與區域B通過另一形成於他們之間的區域(未示出)隔開。
如第1圖所示，區域A中的半導體結構包括：一半導體基底100，諸如矽基底。該半導體基底100可以具有一第一導電類型，諸如P型。一隔離元件108分別設置在區域A內的半導體基底100的相對端部中。該隔離元件108可以是第1圖中所示的STI(shallow trench isolation，淺溝槽隔離)元件，但是不限制於此。在一些實施例中，該隔離元件108可以 為FOX(Field Oxide，場氧化物)隔離元件。該隔離元件108可以包括：諸如矽的氧化物等絕緣材料，但是不限制於此。一深阱區102形成於區域A內的半導體基底100的一部分中並且位於隔離元件108的下方。該深阱區102具有相反於該第一導電類型的一第二導電類型，例如N型。另外，阱區104形成於深阱區102與每個隔離元件108之間。一阱區106形成於半導體基底的位於阱區104之間的部分中，並且該阱區106位於深阱區102的上方。阱區104和阱區106均可以具有第一導電類型，例如P型。阱區110形成於隔離元件108、阱區106和阱區104之間的半導體基底100中。阱區110可以具有第二導電類型，例如N型。阱區112形成在阱區110的一部分中並且與一個隔離元件108相鄰。阱區112具有第一導電類型，例如P型。摻雜區114形成在阱區112的一部分中，並且具有第二導電類型，諸如N型。另一摻雜區116形成在阱區110的一部分中，並且相鄰右邊的隔離元件108。摻雜區116可以具有第二導電類型，諸如N型。摻雜區114和116的摻雜濃度大於阱區110的摻雜濃度。
在區域A中，在阱區112的一部分以及阱區110的一部分上形成一閘極結構G1，該閘極結構G1包括：一介電層118及一導電層120，其中該導電層120形成於該介電層118上。在一個實施例中，在區域A中，該介電層118可以包括：矽的氧化物、矽的氮化物，等等，並且該介電層118的厚度大約介於23~140Å(埃)之間。該導電層120可以包括：諸如多晶矽、金屬等導電材料，並且該導電層120的厚度大約介於 800~2000Å之間。
另外，在區域B中的半導體結構進一步包括：另一隔離元件108，形成於基底100的一部分中。另一閘極結構G2形成於該隔離元件108的一部分上，並且包括：介電層118和導電層120。在一實施例中，在區域B中，該介電層118可以包括：矽的氧化物、矽的氮化物，等等，並且該介電層118的厚度大約介於23~140Å之間。該導電層120可以包括：諸如多晶矽、金屬等導電材料，並且該導電層120的厚度大約介於800~2000Å之間。
在圖2中，一介電層122共形地(conformably)形成於第1圖所示的區域A和區域B上，並且覆蓋半導體基底100的頂面以及覆蓋半導體基底100上形成的閘極結構的露出的表面。在一個實施例中，該介電層122可以包括：矽的氧化物、矽的氮化物，等等，並且該介電層122的厚度大約介於200~1200Å之間。該介電層122比介電層118更厚。
在第3圖中，一導電層124共形地形成於第2圖所示的區域A和區域B中的半導體結構上，並且覆蓋介電層122的頂面。在一個實施例中，該導電層124可以包括：諸如多晶矽、金屬等導電材料，並且其厚度大約介於300~2000Å之間。該導電層124可以比導電層120更厚。
在第4圖中，分別於區域A和B內的導電層124的一部分上形成一圖案化的遮罩層126a和126b，並且執行蝕刻製程128以移除導電層124中未被圖案化的遮罩層126a和126b覆蓋的部分。如第4圖所示，該圖案化的遮罩層126a和 126b可以包括：諸如光阻或其類似物等材料，並且該蝕刻製程例如可以是乾式蝕刻製程。該蝕刻製程128停止在介電層122上，從而在區域A中形成圖案化的導電層124a和在區域B中形成圖案化的導電層124b。在區域A中的圖案化的導電層124a形成在區域A的閘極結構的一部分以及相鄰該閘極結構的半導體基底的一部分的上方，並且在區域B中的圖案化的導電層124b形成於閘極結構的一部分的上方，並且俯視時，該圖案化的導電層124b的整個投影均位於該閘極結構內。
在圖5中，接著執行另一蝕刻製程129以移除介電層122(見第4圖)中未被圖案化的遮罩層126a和126b以及圖案化的導電層124a和124b覆蓋的部分。該蝕刻製程129例如可以為乾式蝕刻製程。如第5圖所示，該蝕刻製程129停止在導電層120和半導體基底100上，從而分別在區域A內形成圖案化的介電層122a和在區域B內形成圖案化的介電層122b。在區域A內的圖案化的介電層122a形成在圖案化的導電層124a的下方，並且位於區域A內的閘極結構G1的一部分和半導體基底的相鄰於該閘極結構一部分上，並且圖案化的介電層122b形成於區域B內的圖案化的導電層124b的下方，並且形成於閘極結構G2上，並且俯視時，該圖案化的介電層122b的整個投影均位於該閘極結構G2內。
在第6圖中，在除去第5圖所示的圖案化的遮罩層126a和126b之後，在區域A內形成另一閘極結構G3，該閘極結構G3包括：圖案化的導電層124a和圖案化的介電層122a，並且該閘極結構G3覆蓋閘極結構G1的20%~80%的頂 面。另外，在區域B內形成另一閘極結構G4，該閘極結構G4包括：圖案化的導電層124b和圖案化的介電層122b，並且該閘極結構G4覆蓋閘極結構G2的70%~90%的頂面。
如第6圖所示，在區域A內，閘極結構G3和閘極結構G1可以組合以用作能夠進行高壓操作的半導體器件的組合閘極，並且摻雜區114和116可以分別用作源極區和汲極區。儘管第6圖示出了組合閘極的使用，但是當與另一半導體器件(該另一半導體器件類於與第6圖所示的半導體器件，但是僅包括閘極結構G1及介電層122)相比時，在第6圖所示的半導體器件的操作期間，可以在阱區110中位於組合閘極下方的部分中，觀察到更加均勻的電場分布。相應地，第6圖所示的能夠進行高電壓操作的半導體器件可以操作在大約9~100V的較高電壓，這大約比該另一半導體器件高大約100%~1100%，該另一半導體器件類於與第6圖所示的半導體器件，但是僅包括閘極結構G1及介電層122。
另外，在第6圖所示的區域B中，導電層124b、介電層122b和導電層120形成額外的電容；可以在第6圖的區域A中所示的能夠高電壓操作的半導體器件的形成期間，同時形成該額外的電容。
如第6圖所示，為了方便說明提供給區域A內的組合閘極和區域B內的電容的電位，導電接觸結構(如導電柱)128a、128b、128c和128d以及導電線130a、130b和130c可以進一步提供至半導體結構。在區域A中，導電接觸結構128a連接至導電層120，導電接觸結構128b連接至導電層124a， 並且導電接觸結構128a和128b均連接至導電線130a，因此在操作期間，可以將相等的電位提供至閘極結構G1和閘極結構G3。另外，在區域B中，導電層124b連接至導電接觸結構128c和導電線130b，並且導電層120連接至導電接觸結構128d和導電線130c。在操作期間，將不同的電位提供給導電線130b和130c，使得可以由導電層124b和120以及介電層122形成電容。在一個實施例中，導電接觸結構128a、128b、128c和128d可以包括：諸如鎢、銅等導電材料，並且導電線130a、130b和130c可以包括：鎢、銅等導電材料。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
A、B‧‧‧區域
100‧‧‧半導體基底
108‧‧‧隔離元件
102‧‧‧深阱區
104、106、110、112‧‧‧阱區
114、116‧‧‧摻雜區
G1、G2、G3、G4‧‧‧閘極結構
118、122a、122b‧‧‧介電層
120、124a、124b‧‧‧導電層
128a、128b、128c、128d‧‧‧導電接觸結構
130a、130b、130c‧‧‧導電線

Claims (19)

  1. 一種半導體器件，包括：一半導體基底，具有一第一導電類型；一第一阱區，形成於該半導體基底中並且具有一第二導電類型，該第二導電類型相反於該第一導電類型；一第二阱區，形成於該第一阱區中並且具有該第一導電類型；一第一閘極結構，形成於該第二阱區和該第一阱區上；一第一摻雜區，形成於該第二阱區中並且具有該第二導電類型；一第二摻雜區，形成於該第一阱區中並且具有該第二導電類型；以及一第二閘極結構，形成於該第一閘極結構的一部分和第一阱區的一部分上。
  2. 如申請專利範圍第1項所述的半導體器件，其中，該第二閘極結構還形成於該第二摻雜區的一部分上。
  3. 如申請專利範圍第1項所述的半導體器件，其中，該第一閘極結構包括：一第一介電層及形成於該第一介電層上的一第一導電層；以及該第二閘極結構包括：一第二介電層及形成於該第二介電層上的一第二導電層。
  4. 如申請專利範圍第3項所述的半導體器件，其中，進一步包括：一隔離元件，設置在該半導體基底中；一第三導電層，形成於該隔離元件上； 一第三介電層，形成於該第三導電層上；以及一第四導電層，形成於該第三介電層上。
  5. 如申請專利範圍第4項所述的半導體器件，其中，該第三導電層、該第三介電層以及該第四導電層形成一電容。
  6. 如申請專利範圍第1項所述的半導體器件，其中，該第一導電類型為P型，該第二導電類型為N型。
  7. 如申請專利範圍第4項所述的半導體器件，其中，該第一介電層的厚度介於23~140Å之間，該第二及第三介電層的厚度介於200~1200Å之間。
  8. 如申請專利範圍第1項所述的半導體器件，其中，該第二閘極結構覆蓋該第一閘極結構的20%~80%的頂面。
  9. 如申請專利範圍第1項所述的半導體器件，其中，該第一閘極結構與該第二閘極結構連接至相等的電位。
  10. 一種半導體器件的形成方法，包括：提供一半導體結構，該半導體結構包括：一半導體基底，具有一第一導電類型；一第一阱區，形成於該半導體基底的位於第一區域中的部分中並且具有一第二導電類型，該第二導電類型相反於該第一導電類型；一第二阱區，形成於該第一阱區中並且具有該第一導電類型；一第一閘極結構，形成於該第二阱區和該第一阱區上；一第一摻雜區，形成於該第二阱區中並且具有該第二導電類型；一第二摻雜區，形成於該第一阱區中並且具有該第二導電類型；以及，形成一第二閘極結構，位於該第一閘極結構的一部分和該 第一阱區的一部分上。
  11. 如申請專利範圍第10項所述的方法，其中，該第二閘極結構還位於該第二摻雜區的一部分上。
  12. 如申請專利範圍第10項所述的半導體器件，其中，該第二閘極結構覆蓋該第一閘極結構的20%~80%的頂面。
  13. 如申請專利範圍第10項所述的半導體器件，其中，該第一導電類型為P型，該第二導電類型為N型。
  14. 如申請專利範圍第10項所述的方法，其中，該半導體結構還包括：一隔離元件，形成於該半導體基底的位於第二區域中的部分中，其中該第二區域不同於該第一區域；以及一第三導電層，形成於該隔離元件上；所述方法還包括：在該第三導電層上形成一第三閘極結構。
  15. 如申請專利範圍第14項所述的方法，其中，該第二閘極結構與該第三閘極結構係同時形成。
  16. 如申請專利範圍第14項所述的方法，其中，該第一閘極結構包括：一第一介電層及一形成於該第一介電層上的第一導電層；該第二閘極結構包括：一第二介電層及一形成於該第二介電層上的第二導電層；該第三閘極結構包括：一第三介電層，形成於該第三導電層上；以及一第四導電層，形成於該第三介電層上。
  17. 如申請專利範圍第16項所述的方法，其中，該第一介電層的厚度介於23~140Å之間，該第二及第三介電層的厚度介於200~1200Å之間。
  18. 如申請專利範圍第16項所述的方法，其中，該第三導電層、 該第三介電層以及該第四導電層形成一電容。
  19. 如申請專利範圍第15項所述的方法，其中，同時形成該第二閘極結構及該第三閘極結構的步驟包括：在該半導體結構上形成一介電層；以及形成一覆蓋該介電層的一導電層；在該導電層上分別形成一第一圖案化的遮罩層和一第二圖案化的遮罩層；以及移除該導電層和該介電層中未被該第一圖案化的遮罩層和該第二圖案化的遮罩層覆蓋的部分，以分別和同時形成該第二閘極結構和該第三閘極結構。
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