TW201740223A - 圖案形成方法 - Google Patents

圖案形成方法 Download PDF

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TW201740223A
TW201740223A TW106103794A TW106103794A TW201740223A TW 201740223 A TW201740223 A TW 201740223A TW 106103794 A TW106103794 A TW 106103794A TW 106103794 A TW106103794 A TW 106103794A TW 201740223 A TW201740223 A TW 201740223A
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acrylic resin
layer
forming method
resin layer
pattern
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TW106103794A
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TWI773659B (zh
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Hidetami Yaegashi
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Tokyo Electron Ltd
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Abstract

本發明提供一種能夠降低所獲得之圖案之LER之值的圖案形成方法。 藉由如下之圖案形成方法而解決上述問題，該圖案形成方法具有如下步驟：於基底層上形成丙烯酸系樹脂層；於上述丙烯酸系樹脂層上形成中間層；於上述中間層上形成已被圖案化之EUV抗蝕劑層；藉由將上述EUV抗蝕劑層作為蝕刻遮罩對上述中間層及上述丙烯酸系樹脂層進行蝕刻，而於上述丙烯酸系樹脂層形成圖案；於在上述丙烯酸系樹脂層形成圖案之步驟之後，去除上述EUV抗蝕劑層及上述中間層；及於去除上述EUV抗蝕劑層及上述中間層之步驟之後，使上述丙烯酸系樹脂層之表面平滑化。

Description

圖案形成方法
本發明係關於一種圖案形成方法。
伴隨半導體裝置之高積體化，製造製程所要求之配線或分離寬度之圖案存在微細化之傾向。此種微細之圖案係藉由將抗蝕圖案作為蝕刻遮罩對基底層進行蝕刻而形成(例如，參照專利文獻1)。 抗蝕圖案例如係藉由於基底層上形成抗蝕劑層，使用光微影技術圖案化成特定形狀之後，使用例如電漿蝕刻使表面平滑化(smoothing)而形成。 又，作為使被圖案化成特定形狀之抗蝕劑層之表面平滑化之方法，亦有如下情形，即，代替電漿蝕刻，而使用例如藉由照射電子束或真空紫外光而將抗蝕劑層中所含之抗蝕劑材料之主鏈切斷之方法。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2011-060916號公報
[發明所欲解決之問題] 然而，就先前之使用電漿蝕刻使表面平滑化之方法而言，於使用EUV(Extreme Ultra Violet，極紫外光)抗蝕劑之情形時，無法獲得充分降低所獲得之抗蝕圖案之LER(Line Edge Roughness，線邊緣粗糙度)之值之效果。 又，就藉由照射電子束或真空紫外光而使表面平滑化之方法而言，於使用EUV抗蝕劑之情形時，難以切斷EUV抗蝕劑之主鏈，因此無法獲得充分降低所獲得之抗蝕圖案之LER之值之效果。 因此，本發明之一方案之目的在於提供一種能夠降低所獲得之圖案之LER之值的圖案形成方法。 [解決問題之技術手段] 為了達成上述目的，本發明之一態樣之圖案形成方法具有如下步驟： 於基底層上形成丙烯酸系樹脂層； 於上述丙烯酸系樹脂層上形成中間層； 於上述中間層上形成已被圖案化之EUV抗蝕劑層； 藉由將上述EUV抗蝕劑層作為蝕刻遮罩對上述中間層及上述丙烯酸系樹脂層進行蝕刻，而於上述丙烯酸系樹脂層形成圖案； 於在上述丙烯酸系樹脂層形成圖案之步驟之後，去除上述EUV抗蝕劑層及上述中間層；及 於去除上述EUV抗蝕劑層及上述中間層之步驟之後，使上述丙烯酸系樹脂層之表面平滑化。 [發明之效果] 根據所揭示之圖案形成方法，可降低所獲得之圖案之LER之值。
以下，一面參照隨附圖式一面對本發明之實施形態進行說明。再者，於本說明書及圖式中，對具有實質上相同之功能構成之構成要素，藉由標註相同之符號而省略重複之說明。 本實施形態之圖案形成方法係藉由利用極紫外光(EUV：Extreme Ultra Violet)進行圖案轉印之EUV微影技術而形成微細之圖案，例如形成ArF微影術之解像極限以下之微細之圖案。 於本實施形態之圖案形成方法中，藉由將已被圖案化之EUV抗蝕劑層作為蝕刻遮罩對丙烯酸系樹脂層進行蝕刻而於丙烯酸系樹脂層形成(轉印)有圖案之後，使丙烯酸系樹脂層之表面平滑化。藉此，可降低所獲得之圖案之LER之值。 以下，對在使用EUV抗蝕劑之圖案形成中可降低所獲得之圖案之LER之值之本實施形態之圖案形成方法進行說明。圖1係例示本實施形態之圖案形成方法之流程圖。 如圖1所示，本實施形態之圖案形成方法具有如下步驟：形成丙烯酸系樹脂層之步驟(步驟S101)、形成中間層之步驟(步驟S102)、形成已被圖案化之EUV抗蝕劑層之步驟(步驟S103)、於丙烯酸系樹脂層形成圖案之步驟(步驟S104)、去除EUV抗蝕劑層及中間層之步驟(步驟S105)及使丙烯酸系樹脂層之表面平滑化之步驟(步驟S106)。 以下，基於圖2至圖7，對各個步驟進行說明。圖2至圖7係說明本實施形態之圖案形成方法之各步驟之圖。再者，圖2至圖7中之(a)係各步驟中之概略立體圖，(b)係各步驟中之概略剖視圖。 步驟S101中，形成丙烯酸系樹脂層。具體而言，如圖2所示，於基底層11上，藉由塗佈例如包含丙烯酸系樹脂之溶液而形成丙烯酸系樹脂層12。再者，亦可於塗佈包含丙烯酸系樹脂之溶液之後，進行用以去除溶劑之預烘烤。作為丙烯酸系樹脂，例如可使用聚甲基丙烯酸甲酯(PMMA)、ArF抗蝕劑。 步驟S102中，形成中間層。具體而言，如圖3所示，於丙烯酸系樹脂層12上，藉由例如旋轉塗佈而形成中間層13。中間層13只要係藉由與丙烯酸系樹脂及EUV抗蝕劑不具有相容性之材料而形成，則並無特別限定。作為中間層13，例如可使用旋塗玻璃(SOG：Spin-On Glass)、含矽之抗反射膜(SiARC：Silicon-containing Anti-Reflective Coating)。 步驟S103中，形成已被圖案化之EUV抗蝕劑層。具體而言，如圖4所示，於中間層13上，藉由塗佈例如包含EUV抗蝕劑之溶液而形成EUV抗蝕劑層14。繼而，將具有特定圖案之遮罩作為曝光遮罩，利用波長13.5 nm之EUV對EUV抗蝕劑層14進行曝光、顯影，由此將EUV抗蝕劑層14圖案化。藉此，形成已被圖案化之EUV抗蝕劑層14。再者，亦可於塗佈包含EUV抗蝕劑之溶液之後，且於曝光之前進行用以去除溶劑之預烘烤。 步驟S104中，於丙烯酸系樹脂層形成圖案。具體而言，如圖5所示，將已被圖案化之EUV抗蝕劑層14作為蝕刻遮罩，藉由例如反應性離子蝕刻(RIE：Reactive Ion Etching)等乾式蝕刻而對中間層13及丙烯酸系樹脂層12進行蝕刻。藉此，於丙烯酸系樹脂層12形成圖案。 步驟S105中，去除EUV抗蝕劑層及中間層。具體而言，如圖6所示，藉由浸漬於例如氫氟酸溶液而去除殘留於丙烯酸系樹脂層12上之EUV抗蝕劑層14及中間層13。 步驟S106中，使丙烯酸系樹脂層之圖案側面平滑化。具體而言，如圖7所示，藉由賦予能夠將丙烯酸系樹脂層12中所含之丙烯酸系樹脂之主鏈切斷之能量以將丙烯酸系樹脂之主鏈切斷，而使丙烯酸系樹脂層12之表面平滑化(smoothing)。例如，亦可藉由對丙烯酸系樹脂層12照射電子束(EB：Electron Beam)而將丙烯酸系樹脂之主鏈切斷。又，亦可藉由對丙烯酸系樹脂層12照射波長為193 nm或172 nm之真空紫外光(VUV：Vacuum Ultra Violet)而將丙烯酸系樹脂之主鏈切斷。又，還可藉由將丙烯酸系樹脂層12加熱至特定溫度而將丙烯酸系樹脂之主鏈切斷。 藉由以上步驟，可形成所期望之圖案。 其次，對本實施形態之圖案形成方法之作用、效果進行說明。圖8係說明本實施形態之圖案形成方法之作用、效果之圖。具體而言，圖8(a)表示對已被圖案化之ArF抗蝕劑層照射電子束(EB)之前後之LER。圖8(b)表示對已被圖案化之ArF抗蝕劑層照射電子束(EB)之前後之線尺寸(CD：Critical Dimension)。 如圖8(a)所示，藉由對已被圖案化之ArF抗蝕劑層照射電子束，可降低LER之值。圖8(a)中，藉由對已被圖案化之ArF抗蝕劑層照射電子束，LER之值自約2.7 nm降低至約2.2 nm。認為其原因在於：藉由對已被圖案化之ArF抗蝕劑層照射電子束，ArF抗蝕劑層中所含之ArF抗蝕劑之主鏈被切斷，ArF抗蝕劑層收縮，ArF抗蝕劑層之表面平滑化。 如圖8(b)所示，藉由對已被圖案化之ArF抗蝕劑層照射電子束，可降低CD之值。圖8(b)中，藉由對已被圖案化之ArF抗蝕劑層照射電子束，CD之值自約50 nm降低至約44 nm。認為其原因在於：藉由對已被圖案化之ArF抗蝕劑層照射電子束，ArF抗蝕劑層中所含之ArF抗蝕劑之主鏈被切斷，ArF抗蝕劑層收縮。 如以上所說明般，於本實施形態之圖案形成方法中，藉由將已被圖案化之EUV抗蝕劑層14作為蝕刻遮罩對丙烯酸系樹脂層12進行蝕刻而於丙烯酸系樹脂層12形成圖案之後，使丙烯酸系樹脂層12之表面平滑化。藉此，可降低所獲得之圖案之LER之值。 又，於本實施形態之圖案形成方法中，當於丙烯酸系樹脂層12形成圖案時，丙烯酸系樹脂層12之上表面由中間層13保護，因此丙烯酸系樹脂層12之上表面未被蝕刻。藉此，可使已被圖案化之丙烯酸系樹脂層12之上表面平滑化。 以上，對本發明之較佳之實施形態進行了說明，但本發明並不限定於該特定之實施形態，能夠於申請專利範圍所記載之本發明之主旨之範圍內進行各種變化、變更。
11‧‧‧基底層
12‧‧‧丙烯酸系樹脂層
13‧‧‧中間層
14‧‧‧EUV抗蝕劑層
S101‧‧‧步驟
S102‧‧‧步驟
S103‧‧‧步驟
S104‧‧‧步驟
S105‧‧‧步驟
S106‧‧‧步驟
圖1係例示本實施形態之圖案形成方法之流程圖。 圖2(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(1) 圖3(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(2) 圖4(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(3) 圖5(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(4) 圖6(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(5) 圖7(a)、(b)係說明本實施形態之圖案形成方法之各步驟之圖。(6) 圖8(a)、(b)係說明本實施形態之圖案形成方法之作用、效果之圖。
S101‧‧‧步驟
S102‧‧‧步驟
S103‧‧‧步驟
S104‧‧‧步驟
S105‧‧‧步驟
S106‧‧‧步驟

Claims (9)

  1. 一種圖案形成方法，其具有如下步驟： 於基底層上形成丙烯酸系樹脂層； 於上述丙烯酸系樹脂層上形成中間層； 於上述中間層上形成已被圖案化之EUV抗蝕劑層； 藉由將上述EUV抗蝕劑層作為蝕刻遮罩對上述中間層及上述丙烯酸系樹脂層進行蝕刻，而於上述丙烯酸系樹脂層形成圖案； 於在上述丙烯酸系樹脂層形成圖案之步驟之後，去除上述EUV抗蝕劑層及上述中間層；及 於去除上述EUV抗蝕劑層及上述中間層之步驟之後，使上述丙烯酸系樹脂層之表面平滑化。
  2. 如請求項1之圖案形成方法，其中使上述丙烯酸系樹脂層之表面平滑化之步驟包含將上述丙烯酸系樹脂層中所含之丙烯酸系樹脂之主鏈切斷之步驟。
  3. 如請求項2之圖案形成方法，其中將上述丙烯酸系樹脂之主鏈切斷之步驟係對上述丙烯酸系樹脂層照射電子束或紫外光。
  4. 如請求項2之圖案形成方法，其中將上述丙烯酸系樹脂之主鏈切斷之步驟係將上述丙烯酸系樹脂層加熱至特定溫度。
  5. 如請求項1至4中任一項之圖案形成方法，其中上述丙烯酸系樹脂層係藉由聚甲基丙烯酸甲酯或ArF抗蝕劑而形成。
  6. 如請求項1至4中任一項之圖案形成方法，其中上述中間層係藉由與丙烯酸系樹脂及EUV抗蝕劑不具有相容性之材料而形成。
  7. 如請求項5之圖案形成方法，其中上述中間層係藉由與丙烯酸系樹脂及EUV抗蝕劑不具有相容性之材料而形成。
  8. 如請求項6之圖案形成方法，其中上述中間層係藉由旋塗玻璃或含矽之抗反射膜而形成。
  9. 如請求項7之圖案形成方法，其中上述中間層係藉由旋塗玻璃或含矽之抗反射膜而形成。
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WO2021131299A1 (ja) * 2019-12-24 2021-07-01 国立研究開発法人産業技術総合研究所 有機修飾金属酸化物ナノ粒子、その製造方法、ｅｕｖフォトレジスト材料およびエッチングマスクの製造方法
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Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04127157A (ja) * 1990-09-19 1992-04-28 Hitachi Ltd 半導体素子の製造方法
JP3264035B2 (ja) * 1993-04-26 2002-03-11 ソニー株式会社 ドライエッチング方法
JP4143023B2 (ja) * 2003-11-21 2008-09-03 株式会社東芝 パターン形成方法および半導体装置の製造方法
JP3857692B2 (ja) * 2004-01-15 2006-12-13 株式会社東芝 パターン形成方法
JP2005243681A (ja) * 2004-02-24 2005-09-08 Tokyo Electron Ltd 膜改質方法、膜改質装置及びスリミング量の制御方法
JP5203937B2 (ja) * 2005-05-24 2013-06-05 メルク セローノ ソシエテ アノニム チアゾール誘導体及びその使用
JP2007140151A (ja) * 2005-11-18 2007-06-07 Renesas Technology Corp 微細パターン形成用材料、微細パターン形成方法、それを用いた電子デバイスの製造方法、およびそれにより製造された電子デバイス
US20070269749A1 (en) * 2006-05-18 2007-11-22 Richard Elliot Schenker Methods to reduce the minimum pitch in a pattern
JP2008096880A (ja) * 2006-10-16 2008-04-24 Toppan Printing Co Ltd レジスト組成物
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
US7432191B1 (en) * 2007-03-30 2008-10-07 Tokyo Electron Limited Method of forming a dual damascene structure utilizing a developable anti-reflective coating
JP2009271259A (ja) * 2008-05-02 2009-11-19 Fujifilm Corp レジストパターン用表面処理剤および該表面処理剤を用いたレジストパターン形成方法
EP2154329A1 (en) * 2008-08-11 2010-02-17 Services Pétroliers Schlumberger Movable well bore cleaning device
EP2239238A1 (en) * 2009-04-06 2010-10-13 AGC Glass Europe Glass article
JP5486883B2 (ja) 2009-09-08 2014-05-07 東京エレクトロン株式会社 被処理体の処理方法
JP4733214B1 (ja) * 2010-04-02 2011-07-27 東京エレクトロン株式会社 マスクパターンの形成方法及び半導体装置の製造方法
JP2012028431A (ja) * 2010-07-21 2012-02-09 Toshiba Corp 半導体装置の製造方法
JP5674375B2 (ja) * 2010-08-03 2015-02-25 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP2012220638A (ja) * 2011-04-06 2012-11-12 Panasonic Corp パターン形成方法
US8647817B2 (en) * 2012-01-03 2014-02-11 Tokyo Electron Limited Vapor treatment process for pattern smoothing and inline critical dimension slimming
US20130189844A1 (en) * 2012-01-23 2013-07-25 Vigma Nanoelectronics Method to increase the pattern density of integrated circuits using near-field EUV patterning technique
JP5944302B2 (ja) * 2012-04-13 2016-07-05 富士フイルム株式会社 位相差フィルム、偏光板、及び液晶表示装置
JP2013235232A (ja) * 2012-04-13 2013-11-21 Fujifilm Corp 位相差フィルム、偏光板、及び液晶表示装置
US9086631B2 (en) * 2012-08-27 2015-07-21 Tokyo Electron Limited EUV resist sensitivity reduction
JP2014072226A (ja) * 2012-09-27 2014-04-21 Tokyo Electron Ltd パターン形成方法
JP2014160124A (ja) * 2013-02-19 2014-09-04 Tokyo Electron Ltd 半導体装置の製造方法及び半導体製造装置
WO2014159427A1 (en) * 2013-03-14 2014-10-02 Applied Materials, Inc Resist hardening and development processes for semiconductor device manufacturing
JP6284849B2 (ja) * 2013-08-23 2018-02-28 富士フイルム株式会社 積層体
JP6159348B2 (ja) * 2014-02-14 2017-07-05 富士フイルム株式会社 着色組成物、硬化膜、カラーフィルタ、パターン形成方法、カラーフィルタの製造方法、固体撮像素子、および、画像表示装置
JP6239466B2 (ja) * 2014-08-15 2017-11-29 東京エレクトロン株式会社 半導体装置の製造方法
US9791779B2 (en) * 2014-10-16 2017-10-17 Tokyo Electron Limited EUV resist etch durability improvement and pattern collapse mitigation
JP6394430B2 (ja) * 2015-02-13 2018-09-26 信越化学工業株式会社 化合物、高分子化合物、レジスト材料及びパターン形成方法
JP6431472B2 (ja) * 2015-12-24 2018-11-28 東京エレクトロン株式会社 パターン形成方法
US9869933B2 (en) * 2016-03-07 2018-01-16 Rohm And Haas Electronic Materials Llc Pattern trimming methods
US9929012B1 (en) * 2016-12-14 2018-03-27 International Business Machines Corporation Resist having tuned interface hardmask layer for EUV exposure
JP6827372B2 (ja) * 2017-06-22 2021-02-10 東京エレクトロン株式会社 パターン形成方法

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