TW201735204A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201735204A
TW201735204A TW106123252A TW106123252A TW201735204A TW 201735204 A TW201735204 A TW 201735204A TW 106123252 A TW106123252 A TW 106123252A TW 106123252 A TW106123252 A TW 106123252A TW 201735204 A TW201735204 A TW 201735204A
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Taiwan
Prior art keywords
electrode
connection wiring
wiring
layer
electrodes
Prior art date
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TW106123252A
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English (en)
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TWI676220B (zh
Inventor
Shinya Watanabe
Toshihiro NAMBU
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Toshiba Kk
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Publication of TW201735204A publication Critical patent/TW201735204A/zh
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Publication of TWI676220B publication Critical patent/TWI676220B/zh

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract

本發明之實施形態係使具有貫通電極之半導體晶片之配線佈局之自由度提高。 於半導體基板(30)設置有貫通電極(66)及多層配線(MH1)，於多層配線(MH1)設置有最下層連接配線(54)、下層連接配線(57)、上層連接配線(59)及最上層連接配線(61)，將貫通電極(66)與最下層連接配線(54)接合，以避開貫通電極(66)之正上方之方式配置通孔(60)。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置及半導體裝置之製造方法。
為了謀求半導體裝置之省空間化、高性能化及大容量化，有時將半導體晶片積層。存在以下裝置，即為了獲得積層之半導體晶片之電性連接，使用被稱為TSV(Through Silicon Via，矽穿孔)之貫通電極。
本發明之一實施形態提供一種可提高具有貫通電極之半導體晶片之配線佈局自由度之半導體裝置及半導體裝置之製造方法。 根據本發明之一實施形態，具備半導體層、多層配線、閘極電極及貫通電極。多層配線與閘極電極設置於上述半導體層。貫通電極貫通上述半導體層，且與上述多層配線中之最下層配線直接相接。
[ 相關申請 ] 本申請享有以日本專利申請2015-110844號(申請日：2015年5月29日)為基礎申請之優先權。本申請係藉由參照該基礎申請而包含基礎申請之全部內容。 以下參照圖式，詳細地說明實施形態之半導體裝置及半導體裝置之製造方法。再者，本發明並不受該等實施形態限定。 (第1實施形態) 圖1係表示第1實施形態之半導體裝置之概略構成之剖視圖。再者，於以下之實施形態中，採用積層有8層半導體晶片之構成為例，但亦可為積層N(N為2以上之整數)層半導體晶片之構成。又，於以下之實施形態中，作為半導體裝置，採用NAND(Not AND，與非)快閃記憶體為例，但半導體裝置既可為DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)、FRAM(註冊商標)(Ferroelectric Random Access Memory，鐵電式隨機存取記憶體)、MRAM(Magnetoresistive Random Access Memory，磁阻式隨機存取記憶體)、PCRAM(Phase Change Random Access Memory，相變隨機存取記憶體)等，亦可為邏輯電路或處理器等。再者，圖1中表示方向之詞語即正與背係表示當將圖1中之支持板1側設為正且將安裝基板21側設為背時之方向，圖2～圖10中之正與背未必一致。 於圖1中，晶片積層體TA1具備積層後之半導體晶片P1～P8。此時，各半導體晶片P1～P8之厚度可設定為40 μm以下。為了防止於操作晶片積層體TA1時破壞晶片積層體TA1，晶片積層體TA1可經由接著層2而固定於支持板1。支持板1可使用例如引線框架等金屬板。支持板1之材料既可為Cu，亦可為42合金(Fe-Ni系合金)。接著層2既可使用絕緣性樹脂，亦可使用晶粒黏著膜。 於各半導體晶片P1～P8設置有單元區域MA1、MA2。於各單元區域MA1、MA2，可將NAND單元設置為陣列狀或設置讀出放大器或解碼器等周邊電路。此時，於各單元區域MA1、MA2中，可以維持單元圖案之配置之規則性之方式配置NAND單元。 於各半導體晶片P2～P8，設置有貫通電極5。此時，於半導體晶片P1，可不設置貫通電極5。各貫通電極5係利用側壁絕緣膜4而與半導體晶片P2～P8絕緣。貫通電極5之材料可使用Cu、Ni或Al等。於貫通電極5與側壁絕緣膜4之間亦可有TiN等障壁金屬膜。於各半導體晶片P2～P8中，貫通電極5可配置於不擾亂各單元區域MA1、MA2中之單元圖案之配置之規則性之位置。因此，貫通電極5設置於各單元區域MA1、MA2內欠佳，較佳為設置於各單元區域MA1、MA2之周圍。此處，藉由維持各單元區域MA1、MA2中之單元圖案之配置之規則性，可提高曝光時之分辨率，且可提高NAND單元之積體度。又，為了防止因各半導體晶片P1～P8之翹曲所引起之各半導體晶片P1～P8間之貫通電極5之連接不良，貫通電極5亦可設置於各單元區域MA1、MA2間。 於半導體晶片P1之背面側設置有背面電極6A。於各半導體晶片P2～P7之背面側設置有背面電極6B，於半導體晶片P8之背面側設置有背面電極6C、6D。又，於半導體晶片P8之背面側設置有背面配線9C、9D。背面配線9D可配置於通過背面配線9D之信號不與通過貫通電極5之信號干涉之位置。於各半導體晶片P2～P8之正面側設置有正面電極7B。 於各半導體晶片P2～P7中，背面電極6B連接於貫通電極5之背面側。於半導體晶片P8中，背面配線9C連接於貫通電極5之背面側，背面電極6C連接於背面配線9C。又，於半導體晶片P8中，背面電極6D連接於背面配線9D。於背面配線9D之端部設置有焊墊電極10。於各半導體晶片P2～P8中，正面電極7B連接於貫通電極5之正面側。半導體晶片P1之背面電極6A連接於半導體晶片P2之正面電極7B。於半導體晶片P2～P8間，使於積層方向相鄰之半導體晶片P2～P8之背面電極6B與正面電極7B連接。於半導體晶片P8之背面側設置有介面晶片3。再者，介面晶片3可與各半導體晶片P1～P8進行資料通信。此時，介面晶片3可經由貫通電極5而對各半導體晶片P1～P8發送寫入資料、指令或位址，或自各半導體晶片P1～P8接收讀取資料。亦可代替介面晶片3，而設置對各半導體晶片P1～P8進行讀寫控制之控制器晶片。於介面晶片3設置有正面電極7C、7D。半導體晶片P8之背面電極6C、6D分別連接於介面晶片3之正面電極7C、7D。再者，背面電極6A、6B或正面電極7B可使用焊料凸塊等突出電極，以確保半導體晶片P1～P8間之間隔SP1。此時，背面電極6A、6B及正面電極7B之兩者既可為突出電極，亦可為突出電極與平面電極之組合。背面電極6A、6B及正面電極7B之材料既可為Au、Cu、Ni、Sn、Pg、Ag等單層膜，亦可為積層膜。當將焊料材用作背面電極6A、6B及正面電極7B之材料時，可使用例如Sn-Cu合金、Sn-Ag合金等。背面配線9C、9D之材料可使用例如Cu等。焊墊電極10之材料可使用例如形成於Cu上之Ni或Ni-Pd合金等。亦可於焊墊電極10之Ni或Ni-Pd合金之表面設置Au覆膜。亦可對焊墊電極10之Ni或Ni-Pd合金之表面實施Sn鍍敷。 於半導體晶片P1～P8間，沿其等之積層方向設置有確保間隔SP1之間隔件8。間隔SP1可設定於10～20 μm左右之範圍內。間隔件8之材料可使用未達背面電極6A、6B、6C、6D與正面電極7B、7C、7D之接合溫度且具有接著性之絕緣性樹脂。例如，當將背面電極6A、6B、6C、6D與正面電極7B、7C、7D焊料接合時，可使用溫度低於焊料之回流焊溫度且具有接著性之絕緣性樹脂。例如間隔件8之材料可使用環氧樹脂、聚醯亞胺樹脂、丙烯酸系樹脂、酚樹脂或苯并環丁烯樹脂等。此處，間隔件8可利用貫通電極5來加強維持間隔SP1。此時，間隔件8可配置於單元區域MA1、MA2上。藉此，於以避開各單元區域MA1、MA2內之方式配置有貫通電極5之情形時，亦可穩定地維持半導體晶片P1～P8間之間隔SP1。 晶片積層體TA1係以被突出電極11支持之狀態覆晶安裝於安裝基板21上。此時，於晶片積層體TA1與安裝基板21之間設置有間隔SP2。該間隔SP2可設定為50 μm左右。介面晶片3可配置於間隔SP2。於安裝基板21之正面側設置有焊盤電極22A及印刷配線22B，於安裝基板21之背面側設置有焊盤電極24A及印刷配線24B。焊盤電極22A之周圍及印刷配線22B由阻焊劑23覆蓋。焊盤電極24A之周圍及印刷配線24B由阻焊劑25覆蓋。突出電極11與焊墊電極10及焊盤電極22A接合。突出電極26與焊盤電極24A接合。突出電極11、26之材料可為Au、Cu、Ni、Sn、Pg、Ag等單層膜，亦可為積層膜。當將焊料材用作突出電極11、26之材料時，可使用例如Sn-Cu合金、Sn-Ag合金等。焊盤電極22A、24A及印刷配線22B、24B之材料可使用Cu等。亦可於焊盤電極22A、24A中自阻焊劑23、25露出之部分形成Au覆膜。安裝基板21之基材可使用例如BT(Bismaleimide Triazine，雙馬來醯亞胺三嗪)樹脂等。 於半導體晶片P1～P8間之間隔SP1填充有密封樹脂(例如底部填充樹脂12A)。於晶片積層體TA1與安裝基板21之間之間隔SP2填充有密封樹脂(例如底部填充樹脂12B)。支持板1、晶片積層體TA1及介面晶片3係於安裝基板21上以密封樹脂12C密封。該密封樹脂12C可使用塑模樹脂。底部填充樹脂12A、12B及密封樹脂12C可使用例如環氧樹脂。 圖2係表示將圖1之E1部分之構成例放大表示之剖視圖。再者，圖2中之表示方向之詞語即正與背係表示與圖1中之正與背相反之方向。即，圖2中之正面電極64相當於背面電極6B，背面電極67相當於正面電極7A。 於圖2中，於半導體晶片P1設置有半導體基板(半導體層)30。於半導體基板30形成有埋式阱31B。於埋式阱31B中形成有單元阱31A，於單元阱31A，可設置記憶單元陣列。再者，半導體基板30之材料可選自例如Si、Ge、SiGe、GaAs、AlGaAs、InP、GaP、InGaAs、GaN、SiC等。又，於半導體基板30形成有元件分離層52。再者，元件分離層52可使用例如STI(Shallow Trench Isolation，淺溝槽隔離)構造。 而且，於單元區域MA1中，於單元阱31A上隔著隧道絕緣膜47而配置電荷蓄積層35。又，於單元阱31A上，於該等電荷蓄積層35之兩側，分別隔著閘極絕緣膜49、50而配置選擇閘極電極39、40。又，於電荷蓄積層35上隔著中間絕緣膜48而配置控制閘極電極36。此處，可利用1個電荷蓄積層35與電荷蓄積層35上之控制閘極電極36構成1個記憶單元。於選擇閘極電極39、40內配置有具有開口EI之中間絕緣膜48-1。換言之，可說是選擇閘極電極39、40由中間絕緣膜48-1分為上部電極與下部電極，並藉由開口EI而將上部電極與下部電極電性連接。 而且，於單元阱31A，形成有配置於電荷蓄積層35間或電荷蓄積層35與選擇閘極電極39、40之間之雜質擴散層32，並且形成有分別配置於選擇閘極電極39、40之單側之雜質擴散層33、34。雜質擴散層34係經由接觸電極37而連接於位元線BL，雜質擴散層33係經由接觸電極38而連接於源極線SCE。再者，於平面NAND記憶體中，各記憶單元之控制閘極電極36可構成字元線WL1～WLh(h為正整數)。 又，於半導體基板30上，隔著閘極絕緣膜51而形成有閘極電極46。於閘極電極46中配置有具有開口EI之中間絕緣膜48-2。換言之，可認為閘極電極46被中間絕緣膜48-2分為上部電極與下部電極，並藉由開口EI而使上部電極與下部電極電性連接。於控制閘極電極36、選擇閘極電極39、40及閘極電極46上，設置有頂蓋絕緣膜43。頂蓋絕緣膜43可用作形成控制閘極電極36、選擇閘極電極39、40及閘極電極46時之硬質掩膜。頂蓋絕緣膜43可使用例如SiN等。而且，於半導體基板30，以夾著閘極電極46下之通道區域之方式形成有雜質擴散層44、45。而且，雜質擴散層44、45分別連接於接觸電極41、42。再者，例如單元阱31A可形成為P型，埋式阱31B及雜質擴散層32、33、34、44、45可形成為N型。電荷蓄積層35之材料可使用例如多晶矽。控制閘極電極36、選擇閘極電極39、40及閘極電極46之材料可使用例如鎢。隧道絕緣膜47及閘極絕緣膜49、50、51之材料可使用例如SiO2 。 又，於半導體基板30上形成有層間絕緣膜68。於層間絕緣膜68上形成有電源線65。於電源線65上形成有無機系保護膜62，於無機系保護膜62上形成有有機系保護膜63。層間絕緣膜68及無機系保護膜62之材料可使用例如SiN、SiO2 或其等之積層膜。有機系保護膜63之材料可使用例如聚醯亞胺系樹脂膜或酚系樹脂膜。 於元件分離層52上形成有中間絕緣膜53，於中間絕緣膜53上形成有多層配線MH1。於多層配線MH1設置有最下層連接配線54、下層連接配線57、上層連接配線59及最上層連接配線61。可使最上層連接配線61之厚度厚於下層連接配線57及上層連接配線59之厚度。例如，最上層連接配線61之厚度可設定為500 nm以上，下層連接配線57及上層連接配線59之厚度可設定為100 nm以下。於最下層連接配線54上設置有頂蓋絕緣膜55。最下層連接配線54與下層連接配線57係經由通孔56而連接。下層連接配線57與上層連接配線59係經由通孔58而連接。上層連接配線59與最上層連接配線61係經由通孔60而連接。通孔60可以避開貫通電極66之正上方之方式配置(設置於除正上方以外之位置)。 中間絕緣膜48、48-1、48-2、53可利用相同之材料構成。例如，中間絕緣膜48、48-1、48-2、53可使用NONON(N為SiN，O為SiO2 )之5層構造。中間絕緣膜48、48-1、48-2、53可藉由同一成膜步驟及蝕刻步驟而形成。再者，可省略中間絕緣膜53。 最下層連接配線54可利用與閘極電極46相同之材料構成。最下層連接配線54及閘極電極46可屬於多層配線MH1中之最下層配線。閘極電極46與最下層連接配線54可藉由同一成膜步驟及蝕刻步驟形成。 下層連接配線57可利用與源極線SCE相同之材料構成。下層連接配線57及源極線SCE可屬於多層配線MH1中之下層配線。下層連接配線57及源極線SCE可藉由同一成膜步驟及CMP(Chemical Mechanical Polishing，化學機械拋光)步驟形成。下層連接配線57及通孔56可藉由雙道金屬鑲嵌步驟一次形成。下層連接配線57、通孔56及源極線SCE可使用W等高熔點金屬。作為下層連接配線57、通孔56及源極線SCE之基底層，亦可為Ti或TiN等障壁金屬膜。 上層連接配線59可利用與位元線BL相同之材料構成。上層連接配線59及位元線BL可屬於多層配線MH1中之上層配線。上層連接配線59及位元線BL可藉由同一成膜步驟及CMP步驟形成。上層連接配線59及通孔58可藉由雙道金屬鑲嵌步驟一次形成。上層連接配線59、通孔58及位元線BL可使用Cu等中熔點金屬。作為上層連接配線59、通孔58及位元線BL之基底層，亦可為Ti或TiN等障壁金屬膜。 最上層連接配線61可利用與電源線65相同之材料構成。最上層連接配線61及電源線65可屬於多層配線MH1中之最上層配線。最上層連接配線61及電源線65可藉由同一成膜步驟及蝕刻步驟形成。最上層連接配線61、通孔60及電源線65可使用Al等低熔點金屬。此時，最上層連接配線61可使用剛性較上層連接配線59及下層連接配線57低之金屬。最下層連接配線54、下層連接配線57、上層連接配線59及通孔56、58、60可埋入至層間絕緣膜68。最上層連接配線61可配置於層間絕緣膜68上。最上層連接配線61之周圍被無機系保護膜62覆蓋，並且於最上層連接配線61上，形成有正面電極64作為圖1之背面電極6B。 於半導體基板30，設置有貫通電極66作為圖1之貫通電極5。貫通電極66係利用側壁絕緣膜65而與半導體基板30絕緣。貫通電極66之正面側與最下層連接配線54接合。於貫通電極66之背面側，設置有背面電極67作為圖1之正面電極7A。 此處，藉由使貫通電極66與最下層連接配線54直接相接，可於貫通電極66之上方設置配線。因此，與將貫通電極66連接於最上層連接配線61之構成相比，可提高多層配線MH1之配線佈局之自由度。又，當最下層連接配線54使用蝕刻配線，並且下層連接配線57及上層連接配線59使用金屬鑲嵌配線時，於最下層連接配線54未產生凹陷，但於下層連接配線57及上層連接配線59產生凹陷。因此，藉由將貫通電極66與最下層連接配線54接合，和將貫通電極66與下層連接配線57或上層連接配線59接合之構成相比，可提高與貫通電極66之接合面為相反側之面之平坦性。因此，可減少貫通電極66穿透最下層連接配線54之危險性，可減少高電阻不良。 進而，藉由以避開貫通電極66之正上方之方式配置通孔60，可提高最上層連接配線61之可撓性。因此，可使最上層連接配線61具有緩衝性，而可使通過正面電極64或背面電極67對貫通電極66施加荷重時之應力分散，因此可防止最下層連接配線54、下層連接配線57或上層連接配線59破壞。 圖3(a)係表示圖2之通孔60之配置例之俯視圖，圖3(b)係表示圖2之通孔58之配置例之俯視圖，圖3(c)係表示圖2之通孔56之配置例之俯視圖。 於圖3(a)中，於最上層連接配線61下，於貫通電極66之周圍配置有通孔60，於貫通電極66之正上方未配置通孔60。藉此，可提高最上層連接配線61之可撓性，而可使對正面電極64或貫通電極66施加荷重時之應力分散。 於圖3(b)中，於上層連接配線59下能以均等之間隔配置通孔58。此時，為了減少對通孔58施加之荷重，可於貫通電極66之正上方亦配置通孔58。 於圖3(c)中，於下層連接配線57下能以均等之間隔配置通孔56。此時，為了減少對通孔56施加之荷重，可於貫通電極66之正上方亦配置通孔56。 再者，於上述實施形態中，作為與形成於半導體基板30上之貫通電極66連接之多層配線MH1，採用4層配線(最下層配線、下層配線、上層配線及最上層配線)為例，但只要為2層以上之配線，則無論幾層均可。此時，於主動區域中，最下層配線可用於控制形成於半導體基板30之通道區域之導電性之閘極電極。 圖4係表示可應用於圖1之半導體裝置之配線佈局之一例之剖視圖。再者，於圖4中，採用配置有3個貫通電極66A～66C之構成為例。 於圖4中，於半導體基板30形成有元件分離層52。於元件分離層52上形成有中間絕緣膜53A～53C，於中間絕緣膜53A～53C上形成有多層配線MH2。於多層配線MH2，設置有最下層連接配線54A～54C、下層連接配線57A、57B、上層連接配線59A及最上層連接配線61A～61C。於最下層連接配線54A～54C上分別設置有頂蓋絕緣膜55A～55C。最下層連接配線54A～54C分別配置於中間絕緣膜53A～53C上。下層連接配線57A配置於最下層連接配線54A上。下層連接配線57B配置於最下層連接配線54B、54C上。上層連接配線59A配置於下層連接配線57A、57B上。最上層連接配線61A、61B配置於上層連接配線59A上。最上層連接配線61C配置於下層連接配線57B上。 最下層連接配線54A與下層連接配線57A係經由通孔56A而連接。最下層連接配線54B與下層連接配線57B係經由通孔56B而連接，最下層連接配線54C與下層連接配線57B係經由通孔56C而連接。下層連接配線57A與上層連接配線59A係經由通孔58A而連接，下層連接配線57B與上層連接配線59A係經由通孔58B而連接。上層連接配線59A與最上層連接配線61A係經由通孔60A而連接，上層連接配線59A與最上層連接配線61B係經由通孔60B而連接。通孔60A可以避開貫通電極66A之正上方之方式配置，通孔60B可以避開貫通電極66B之正上方之方式配置。 最下層連接配線54A～54C、下層連接配線57A、57B、上層連接配線59A及最上層連接配線61A～61C及通孔56A～56C、58A、58B、60A、60B可埋入至層間絕緣膜68。最上層連接配線61A～61C可配置於層間絕緣膜68上。最上層連接配線61A～61C之周圍被無機系保護膜62覆蓋，並且於最上層連接配線61A～61C上，分別形成有正面電極64A～64C。 於半導體基板30，設置有貫通電極66A～66C。貫通電極66A～66C分別利用側壁絕緣膜65A～65C而與半導體基板30絕緣。貫通電極66A～66C之正面側與最下層連接配線54A～54C分別接合。於貫通電極66A～66C之背面側，分別設置有背面電極67A～67C。 此處，藉由將貫通電極66A～66C與最下層連接配線54A～54C分別直接相接，可將下層連接配線57A及上層連接配線59A設置於貫通電極66A之正上方，或將下層連接配線57B及上層連接配線59B設置於貫通電極66B之正上方，或將下層連接配線57B設置於貫通電極66C之正上方。因此，可經由上層連接配線59A而將貫通電極66A、66B電性連接，或經由下層連接配線57B而將貫通電極66B、66C電性連接，而可提高多層配線MH1之配線佈局之自由度。 (第2實施形態) 圖5係表示應用於第2實施形態之半導體裝置之貫通電極之連接構造之剖視圖。 於圖5之構成中，將第1導電層54-1、第2導電層54-2及第3導電層54-3之積層構造用於圖2之最下層連接配線54。第1導電層54-1可使用多晶矽，第2導電層54-2可使用WN，第3導電層54-3可使用W。第3導電層54-3之材料可自Al、Cu、W、NiSi、CoSi及Mn中選擇。於第1導電層54-1、第2導電層54-2及第3導電層54-3之側壁形成有側牆69。側牆69之材料可使用例如SiO2 。而且，貫通電極66與第3導電層54-3接合。此時，貫通電極66可與第1導電層54-1、第2導電層54-2及第3導電層54-3之電阻最低之導電層直接相接。 又，作為層間絕緣膜68，設置有層間絕緣膜68A～68D。第1導電層54-1、第2導電層54-2及第3導電層54-3埋入至層間絕緣膜68A。利用蝕刻而將第1導電層54-1、第2導電層54-2及第3導電層54-3圖案化，藉此，可使於第1導電層54-1、第2導電層54-2及第3導電層54-3不產生凹陷。 通孔56及下層連接配線57埋入至層間絕緣膜68B。此時，由於利用雙道金屬鑲嵌形成通孔56及下層連接配線57，故而於下層連接配線57產生凹陷57D。 通孔58及上層連接配線59埋入至層間絕緣膜68C。此時，由於利用雙道金屬鑲嵌形成通孔58及上層連接配線59，故而於上層連接配線59產生凹陷59D。 通孔60埋入至層間絕緣膜68D，最上層連接配線61配置於層間絕緣膜68D上。 此處，藉由將貫通電極66與第3導電層54-3直接相接，和與第1導電層54-1或第2導電層54-2接合之情形相比，可減小接觸電阻。又，藉由將貫通電極66與第3導電層54-3直接相接，相對於將貫通電極66與下層連接配線57或上層連接配線59接合之構成而言，可防止因凹陷57D、59D而引起之接合不良。 再者，於圖5之實施形態中，表示出圖2之最下層連接配線54為3層構造之情形，但最下層連接配線54並不限定於3層構造，無論幾層均可。 (第3實施形態) 圖6(a)、圖6(b)、圖7(a)及圖7(b)係表示第3實施形態之半導體裝置之製造方法之剖視圖。 於圖6(a)中，於半導體基板71形成元件分離層72。其次，利用CVD或濺鍍等方法於元件分離層72上使中間絕緣材及最下層導電材依次成膜之後，利用光微影技術及RIE(Reactive Ion Etching，反應性離子蝕刻)技術而將中間絕緣材及最下層導電材圖案化，藉此，於元件分離層72上形成中間絕緣膜73及最下層連接配線74。其次，於利用CVD等方法於最下層連接配線74上成膜層間絕緣膜82之後，利用雙道金屬鑲嵌將經由通孔76而連接於最下層連接配線74之下層連接配線77埋入至層間絕緣膜82。其次，於利用CVD等方法於下層連接配線77上成膜層間絕緣膜82之後，利用雙道金屬鑲嵌將經由通孔78而連接於下層連接配線77之上層連接配線79埋入至層間絕緣膜82。其次，於利用CVD等方法於上層連接配線79上成膜層間絕緣膜82之後，將連接於上層連接配線79之通孔80埋入至層間絕緣膜82。其次，於層間絕緣膜82上形成經由通孔80而連接於上層連接配線79之最上層連接配線81。其次，於層間絕緣膜82上形成以最上層連接配線81之表面露出之方式經圖案化之無機系保護膜83A。其次，於無機系保護膜83A上形成以最上層連接配線81之表面露出之方式經圖案化之有機系保護膜83B。其次，於最上層連接配線81上形成障壁金屬膜84A及凸塊電極84B，於凸塊電極84B上形成金屬被覆膜84C。障壁金屬膜84A之材料可使用例如積層於Ti上之包含Cu之2層構造。凸塊電極84B之材料可使用例如Ni。金屬被覆膜84C可使凸塊電極84B提高焊料潤濕性，且金屬被覆膜84C可使用例如Au。 其次，經由接著層S1而將半導體基板71之正面側接著於支持基板S2。此時，可使半導體基板71為晶片狀態。再者，支持基板S2之材料既可為Si，亦可為玻璃。接著層S1之材料可使用熱固性樹脂。其次，藉由利用CMP或BSG等方法對半導體基板71之背面側進行研磨，而使半導體基板71薄膜化。此時，半導體基板71之厚度TS可設定為50 μm以下。其次，利用CVD等方法於半導體基板71之背面依次成膜絕緣膜70A、70B。絕緣膜70A之材料可使用SiO2 ，絕緣膜70B之材料可使用SiN。 其次，如圖6(b)所示，利用光微影技術及RIE技術於半導體基板71形成貫通孔TB。此時，貫通孔TB之前端可利用中間絕緣膜73封止。貫通孔TB之直徑KS可設定為10 μm左右。 其次，如圖7(a)所示，利用CVD等方法於貫通孔TB之側壁成膜側壁絕緣膜88。繼而，通過貫通孔TB而蝕刻側壁絕緣膜88與中間絕緣膜73，藉此使最下層連接配線74露出。 其次，如圖7(b)所示，利用濺鍍等方法以將貫通孔TB之側壁覆蓋之方式依次成膜障壁金屬膜86A及籽晶層86B。障壁金屬膜86A之材料可使用Ti，籽晶層86B之材料可使用Cu。其次，利用電場鍍敷等方法將貫通電極86C埋入至貫通孔TB內。貫通電極86C之材料可使用Ni。其次，於貫通電極86C之表面形成基底金屬膜87A之後，於基底金屬膜87A上形成凸塊電極87B。基底金屬膜87A之材料可使用Cu，凸塊電極87B之材料可使用Sn。而且，於半導體基板71被支持基板S2支持之狀態下，使探針接腳與凸塊電極87B接觸，藉此進行半導體基板71之器件之測試。之後，於將切割帶等支持帶貼附於半導體基板71之背面側之後，將接著層S1及支持基板S2自半導體基板71剝離。其次，藉由切割半導體基板71而將半導體基板71單片化為半導體晶片P1～P8。繼而，當將半導體晶片P1～P8積層時，上層之半導體晶片之凸塊電極87B與下層之半導體晶片之凸塊電極84B接合。此處，當對凸塊電極84B使用Ni，對凸塊電極87B使用Sn時，於凸塊電極84B、87B接合時形成Ni-Sn合金。 (第4實施形態) 圖8(a)係表示第4實施形態之半導體裝置之正面測試焊墊之佈局例的俯視圖，圖8(b)係將第4實施形態之半導體裝置之正面電極放大表示之俯視圖，圖8(c)係將第4實施形態之半導體裝置之正面測試焊墊放大表示之俯視圖，圖8(d)係表示第4實施形態之半導體裝置之背面測試焊墊之佈局例的俯視圖。 於圖8(a)～圖8(d)中，於半導體晶片P11之正面側，設置有正面電極91及正面測試焊墊93。正面電極91可針對每一晶片於半導體晶片P11配置數萬個左右。正面測試焊墊93可針對每一晶片於半導體晶片P11配置數千個左右。於半導體晶片P11之背面側，設置有背面電極95及背面測試焊墊96。背面測試焊墊96間之間隔可以如下方式測定：即便於測試時對背面測試焊墊96施加荷重，而將背面測試焊墊96破壞之情形時，相鄰之背面測試焊墊96亦不會相互接觸。於半導體晶片P11埋入有貫通電極92、94。正面電極91與背面電極95係經由貫通電極92而電性連接。正面測試焊墊93與背面測試焊墊96係經由貫通電極94而電性連接。可使各貫通電極92、94之直徑R1、R2相互相等，且可設定為20 μm以下。 此處，1個正面電極91及1個背面電極95連接於1個貫通電極92。1個正面測試焊墊93連接於3個貫通電極94，1個背面測試焊墊96連接於1個貫通電極94。連接於1個正面測試焊墊93之3個貫通電極94可配置於假想三角形之頂點。此處，所謂假想三角形係方便表示貫通電極94之位置關係之假想圖形，不論有無呈三角形形狀之某些構成自身。正面測試焊墊93之尺寸可大於正面電極91之尺寸。正面測試焊墊93之邊之長度X2、Y2可設定為80 μm左右，正面電極91之邊之長度X1、Y1可設定為40 μm左右。正面測試焊墊93之邊之長度X2、Y2可小於探針接腳之前端之直徑R3。此時，探針接腳121之前端之直徑R3可設定為120～130 μm左右。較佳為於探針接腳121之可動範圍內，不配置除正面測試焊墊93以外之電極或間隔件8。 圖9係表示圖8(c)之正面測試焊墊與貫通電極之連接構造之一例之剖視圖。再者，於圖9中，為了容易判斷，為方便起見而將連接於1個正面測試焊墊93之3個貫通電極94於一剖面並排地表示。 於圖9中，於半導體晶片P11設置有半導體基板101。於半導體基板101形成有元件分離層102。於元件分離層102上形成有中間絕緣膜103，於中間絕緣膜103上形成有多層配線MH3。於多層配線MH3，設置有最下層連接配線104、下層連接配線107、上層連接配線109及正面測試焊墊(最上層連接配線)93。對於最下層連接配線104，可使用第1導電層104-1、第2導電層104-2及第3導電層104-3之積層構造。多層配線MH3可以與圖5之構成相同之方式構成。於最下層連接配線104上設置有頂蓋絕緣膜105。於第1導電層104-1、第2導電層104-2及第3導電層104-3之側壁形成有側牆119。最下層連接配線104與下層連接配線107係經由通孔106而連接。下層連接配線107與上層連接配線109係經由通孔108而連接。上層連接配線109與最上層連接配線93係經由通孔110而連接。通孔110可以避開貫通電極94之正上方之方式配置。 又，於半導體基板101上，形成有層間絕緣膜118。於層間絕緣膜118上形成有無機系保護膜112。最上層連接配線93之周圍被無機系保護膜112覆蓋，並且於最上層連接配線93及無機系保護膜112上形成有有機系保護膜113。 於半導體基板101，設置有貫通電極94。貫通電極94係利用側壁絕緣膜105而與半導體基板101絕緣。3個貫通電極94之正面側與1個第3導電層104-3接合。於各貫通電極94之背面側，設置有1個背面電極96。 圖10(a)係表示對第4實施形態之半導體裝置進行測試時探針卡之配置方法之俯視圖，圖10(b)係將圖10(a)之探針接腳之接觸狀態放大表示之剖視圖。 於圖10(a)中，於探針卡120設置有探針接腳121。探針接腳121可使用例如彈簧針(spring pin)。探針卡120之材料可使用例如陶瓷等。此時，探針接腳121收納於保持器122內，探針接腳121以可升降之方式被彈簧123支持。探針接腳可設置相當於正面測試焊墊93之個數之數量。可使探針接腳121之配置與正面測試焊墊93之配置對應。探針卡120可連接於測試器124。 而且，可藉由以與連接於1個正面測試焊墊93之3個背面測試焊墊96同時接觸之方式壓抵探針接腳121，而對半導體晶片P11進行測試。藉由將探針接腳121一次性壓抵至設置於半導體晶片P11之每一晶片數千個之背面測試焊墊96，可縮短半導體晶片P11之測試時間。僅將於該測試中合格之半導體晶片P1～P8用於晶片積層體TA1，藉此，可提高晶片積層體TA1之製造良率。 此處，於1個正面測試焊墊93連接3個貫通電極94，使1個探針接腳121同時與3個背面測試焊墊96接觸，藉此，與利用2個以下之背面測試焊墊96承受1個探針接腳121之荷重之情形相比，可減少對1個貫通電極94施加之負荷，從而可減少貫通電極94之損壞。進而，使1個探針接腳121同時與3個背面測試焊墊96接觸，藉此，與利用2個以下之背面測試焊墊96承受1個探針接腳121之荷重之情形相比，可使對1個貫通電極94施加之負荷相等，可提高彈簧123之彈力，而可減少因彈簧123不回彈而造成之接觸不良。 又，根據探針卡120與半導體晶片P11之熱膨脹係數之差異等，有探針卡120上之探針接腳121間之間隔與半導體晶片P11上之正面測試焊墊93間之間隔有偏差之情形。即便於該情形時，亦可藉由將連接於1個正面測試焊墊93之3個貫通電極94配置於三角形之頂點，而使1個探針接腳121始終同時與3個背面測試焊墊96接觸，與利用4個以上之背面測試焊墊96承受1個探針接腳121之荷重之情形相比，可使對1個貫通電極94施加之負荷均勻化。 雖對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種方式實施，且可於不脫離發明主旨之範圍內，進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧支持板 2‧‧‧接著層 3‧‧‧介面晶片 4‧‧‧側壁絕緣膜 5‧‧‧貫通電極 6A～6D‧‧‧背面電極 7A‧‧‧正面電極 7B‧‧‧正面電極 7C‧‧‧正面電極 7D‧‧‧正面電極 8‧‧‧間隔件 9C、9D‧‧‧背面配線 10‧‧‧焊墊電極 11、26‧‧‧突出電極 12A、12B‧‧‧底部填充樹脂 12C‧‧‧密封樹脂 21‧‧‧安裝基板 22A、24A‧‧‧焊盤電極 22B、24B‧‧‧印刷配線 23、25‧‧‧阻焊劑 30‧‧‧半導體基板(半導體層) 31A‧‧‧單元阱 31B‧‧‧埋式阱 32、33、34、44、45‧‧‧雜質擴散層 35‧‧‧電荷蓄積層 36‧‧‧控制閘極電極 37‧‧‧接觸電極 38‧‧‧接觸電極 39、40‧‧‧選擇閘極電極 41、42‧‧‧接觸電極 43‧‧‧頂蓋絕緣膜 46‧‧‧閘極電極 47‧‧‧隧道絕緣膜 48、48-1、48-2、53‧‧‧中間絕緣膜 49、50、51‧‧‧閘極絕緣膜 52‧‧‧元件分離層 53A～53C‧‧‧中間絕緣膜 54‧‧‧最下層連接配線 54-1‧‧‧第1導電層 54-2‧‧‧第2導電層 54-3‧‧‧第3導電層 54A～54C‧‧‧最下層連接配線 55‧‧‧頂蓋絕緣膜 55A～55C‧‧‧頂蓋絕緣膜 56‧‧‧通孔 56A～56C、58A、58B、60A、60B‧‧‧通孔 57‧‧‧下層連接配線 57A、57B‧‧‧下層連接配線 57D‧‧‧凹陷 58‧‧‧通孔 59‧‧‧上層連接配線 59A‧‧‧上層連接配線 59D‧‧‧凹陷 60‧‧‧通孔 61‧‧‧最上層連接配線 61A～61C‧‧‧最上層連接配線 62‧‧‧無機系保護膜 63‧‧‧有機系保護膜 64‧‧‧正面電極 64A～64C‧‧‧正面電極 65‧‧‧電源線 65A～65C‧‧‧側壁絕緣膜 66‧‧‧貫通電極 66A～66C‧‧‧貫通電極 67‧‧‧背面電極 67A～67C‧‧‧背面電極 68‧‧‧層間絕緣膜 68A～68D‧‧‧層間絕緣膜 69‧‧‧側牆 70A、70B‧‧‧絕緣膜 71‧‧‧半導體基板 72‧‧‧元件分離層 73‧‧‧中間絕緣膜 74‧‧‧最下層連接配線 76‧‧‧通孔 77‧‧‧下層連接配線 78‧‧‧通孔 79‧‧‧上層連接配線 80‧‧‧通孔 81‧‧‧最上層連接配線 82‧‧‧層間絕緣膜 83A‧‧‧無機系保護膜 83B‧‧‧有機系保護膜 84A‧‧‧障壁金屬膜 84B‧‧‧凸塊電極 84C‧‧‧金屬被覆膜 86A‧‧‧障壁金屬膜 86B‧‧‧籽晶層 86C‧‧‧貫通電極 87A‧‧‧基底金屬膜 87B‧‧‧凸塊電極 88‧‧‧側壁絕緣膜 91‧‧‧正面電極 92、94‧‧‧貫通電極 93‧‧‧正面測試焊墊 94‧‧‧貫通電極 95‧‧‧背面電極 96‧‧‧背面電極 101‧‧‧半導體基板 102‧‧‧元件分離層 103‧‧‧中間絕緣膜 104‧‧‧最下層連接配線 104-1‧‧‧第1導電層 104-2‧‧‧第2導電層 104-3‧‧‧第3導電層 105‧‧‧頂蓋絕緣膜 106‧‧‧通孔 107‧‧‧下層連接配線 108‧‧‧通孔 109‧‧‧上層連接配線 110‧‧‧通孔 112‧‧‧無機系保護膜 113‧‧‧有機系保護膜 118‧‧‧層間絕緣膜 119‧‧‧側牆 120‧‧‧探針卡 121‧‧‧探針接腳 122‧‧‧保持器 123‧‧‧彈簧 124‧‧‧測試器 BL‧‧‧位元線 EI‧‧‧開口 KS‧‧‧直徑 MA1、MA2‧‧‧單元區域 MH1‧‧‧多層配線 MH2‧‧‧多層配線 MH3‧‧‧多層配線 P1～P8‧‧‧半導體晶片 P11‧‧‧半導體晶片 R1、R2‧‧‧直徑 R3‧‧‧直徑 S1‧‧‧接著層 S2‧‧‧支持基板 SCE‧‧‧源極線 SP1‧‧‧間隔 SP2‧‧‧間隔 TA1‧‧‧晶片積層體 TB‧‧‧貫通孔 TS‧‧‧厚度 WL1～WLh‧‧‧字元線 X1、Y1‧‧‧正面電極之邊之長度 X2、Y2‧‧‧正面測試焊墊之邊之長度
圖1係表示第1實施形態之半導體裝置之概略構成之剖視圖。 圖2係將圖1之E1部分之構成例放大表示之剖視圖。 圖3(a)係表示圖2之通孔60之配置例之俯視圖，圖3(b)係表示圖2之通孔58之配置例之俯視圖，圖3(c)係表示圖2之通孔56之配置例之俯視圖。 圖4係表示可應用於圖1之半導體裝置之配線佈局之一例的剖視圖。 圖5係表示應用於第2實施形態之半導體裝置之貫通電極之連接構造的剖視圖。 圖6(a)及圖6(b)係表示第3實施形態之半導體裝置之製造方法之剖視圖。 圖7(a)及圖7(b)係表示第3實施形態之半導體裝置之製造方法之剖視圖。 圖8(a)係表示第4實施形態之半導體裝置之正面測試焊墊之佈局例的俯視圖，圖8(b)係將第4實施形態之半導體裝置之正面電極放大表示之俯視圖，圖8(c)係將第4實施形態之半導體裝置之正面測試焊墊放大表示之俯視圖，圖8(d)係表示第4實施形態之半導體裝置之背面測試焊墊之佈局例的俯視圖。 圖9係表示圖8(c)之正面測試焊墊與貫通電極之連接構造之一例之剖視圖。 圖10(a)係表示對第4實施形態之半導體裝置進行測試時探針卡之配置方法之俯視圖，圖10(b)係將圖10(a)之探針接腳之接觸狀態放大表示之剖視圖。
30‧‧‧半導體基板(半導體層)
31A‧‧‧單元阱
31B‧‧‧埋式阱
32、33、34、44、45‧‧‧雜質擴散層
35‧‧‧電荷蓄積層
36‧‧‧控制閘極電極
37‧‧‧接觸電極
38‧‧‧接觸電極
39、40‧‧‧選擇閘極電極
41、42‧‧‧接觸電極
43‧‧‧頂蓋絕緣膜
46‧‧‧閘極電極
47‧‧‧隧道絕緣膜
48、48-1、48-2、53‧‧‧中間絕緣膜
49、50、51‧‧‧閘極絕緣膜
52‧‧‧元件分離層
54‧‧‧最下層連接配線
55‧‧‧頂蓋絕緣膜
56‧‧‧通孔
57‧‧‧下層連接配線
58‧‧‧通孔
59‧‧‧上層連接配線
60‧‧‧通孔
61‧‧‧最上層連接配線
62‧‧‧無機系保護膜
63‧‧‧有機系保護膜
64‧‧‧正面電極
65‧‧‧電源線
66‧‧‧貫通電極
67‧‧‧背面電極
68‧‧‧層間絕緣膜
BL‧‧‧位元線
EI‧‧‧開口
MA1‧‧‧單元區域
MH1‧‧‧多層配線
SCE‧‧‧源極線
WL1~WLh‧‧‧字元線

Claims (4)

  1. 一種半導體裝置，其具備： 半導體層； 複數個貫通電極，其等貫通上述半導體層； 複數個正面測試焊墊(front-surface test pad)，其等係於上述半導體層之正面側連接於上述複數個貫通電極；及 複數個背面測試焊墊，其等係於上述半導體層之背面側連接於上述複數個貫通電極；且 上述複數個背面測試焊墊中之一個與上述複數個貫通電極中之一個連接，上述複數個正面測試焊墊中之一個與上述複數個貫通電極中之三個連接。
  2. 如請求項1之半導體裝置，其進而具備設於上述半導體層之多層配線；且 上述複數個貫通電極係與上述多層配線中的最下層配線直接相接； 上述複數個正面測試焊墊係以上述多層配線中的最上層配線構成； 上述最下層配線具有積層有複數之導電層的積層構造，且上述複數個貫通電極係接合於上述積層構造中電阻最低之導電層。
  3. 如請求項2之半導體裝置，其具備： 無機系保護膜，其保護上述多層配線中之最上層配線； 第1通孔(via)，其將上述最上層配線與第1下層配線直接連接；及 第2通孔，其將上述第1下層配線與上述最下層配線電性連接；且 上述第1通孔設置於除上述複數個貫通電極之正上方以外之位置。
  4. 如請求項3之半導體裝置，其中上述第2通孔係設置於上述複數個貫通電極之正上方及除正上方以外之位置。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690002B (zh) * 2018-05-24 2020-04-01 日商東芝記憶體股份有限公司 半導體裝置及其之製造方法
TWI695484B (zh) * 2018-03-20 2020-06-01 日商東芝記憶體股份有限公司 半導體裝置
US11444005B2 (en) 2017-10-19 2022-09-13 Sony Semiconductor Solutions Corporation Semiconductor device, imaging device, and manufacturing apparatus
TWI818060B (zh) * 2018-08-31 2023-10-11 日商索尼半導體解決方案公司 半導體裝置、半導體試驗裝置及半導體裝置之試驗方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535633B2 (en) 2015-07-02 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9806058B2 (en) * 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
KR102548835B1 (ko) * 2016-08-26 2023-06-30 인텔 코포레이션 집적 회로 디바이스 구조체들 및 양면 제조 기술들
JP6749408B2 (ja) * 2016-10-31 2020-09-02 京セラ株式会社 プローブカード用基板、プローブカード、および検査装置
US10043970B2 (en) * 2016-12-15 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Determining a characteristic of a monitored layer on an integrated chip
EP3364454B1 (en) 2017-02-15 2022-03-30 ams AG Semiconductor device
US11227779B2 (en) * 2017-09-12 2022-01-18 Asm Technology Singapore Pte Ltd Apparatus and method for processing a semiconductor device
JP2019054160A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置
CN107863351B (zh) 2017-11-21 2019-03-19 长江存储科技有限责任公司 一种高堆叠层数3d nand闪存的制作方法及3d nand闪存
DE112017008080T5 (de) 2017-12-26 2020-07-09 Intel Corporation Gestapelte transistoren mit zuletzt ausgebildetem kontakt
WO2019172879A1 (en) 2018-03-05 2019-09-12 Intel Corporation Metallization structures for stacked device connectivity and their methods of fabrication
CN108565255B (zh) * 2018-04-09 2020-10-30 复汉海志(江苏)科技有限公司 一种半导体互连结构
CN108428665B (zh) * 2018-04-09 2020-10-30 山东汉芯科技有限公司 一种叠层芯片集成封装工艺
EP3564994A1 (en) * 2018-05-03 2019-11-06 ams AG Semiconductor device with through-substrate via
US11688780B2 (en) 2019-03-22 2023-06-27 Intel Corporation Deep source and drain for transistor structures with back-side contact metallization
US11037846B2 (en) * 2019-09-20 2021-06-15 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
JP7341927B2 (ja) 2020-03-12 2023-09-11 キオクシア株式会社 半導体記憶装置
KR20240061935A (ko) * 2022-11-01 2024-05-08 삼성전자주식회사 테스트 패드를 갖는 반도체 패키지
CN117976660A (zh) * 2024-03-27 2024-05-03 湖北江城实验室 一种半导体结构及其热测试方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267105B1 (ko) * 1997-12-09 2000-11-01 윤종용 다층패드를구비한반도체소자및그제조방법
JP2005276877A (ja) * 2004-03-23 2005-10-06 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2007087975A (ja) * 2005-09-16 2007-04-05 Ricoh Co Ltd 半導体装置
JP2007251022A (ja) 2006-03-17 2007-09-27 Fujitsu Ltd 半導体装置及びその試験方法
JP2008053624A (ja) 2006-08-28 2008-03-06 Matsushita Electric Ind Co Ltd アライメント装置
JP2008171924A (ja) 2007-01-10 2008-07-24 Sharp Corp 半導体ウェハ、テスト装置、半導体ウェハのテスト方法
JP2008294367A (ja) * 2007-05-28 2008-12-04 Nec Electronics Corp 半導体装置およびその製造方法
JP4799542B2 (ja) 2007-12-27 2011-10-26 株式会社東芝 半導体パッケージ
JP2011171567A (ja) * 2010-02-19 2011-09-01 Elpida Memory Inc 基板構造物の製造方法及び半導体装置の製造方法
US20120032339A1 (en) * 2010-08-04 2012-02-09 Nanya Technology Corporation Integrated circuit structure with through via for heat evacuating
US8410580B2 (en) * 2011-01-12 2013-04-02 Freescale Semiconductor Inc. Device having conductive substrate via with catch-pad etch-stop
JP5802515B2 (ja) * 2011-10-19 2015-10-28 株式会社東芝 半導体装置及びその製造方法
JP5955706B2 (ja) * 2012-08-29 2016-07-20 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2014107308A (ja) 2012-11-22 2014-06-09 Toshiba Corp 半導体装置及びその製造方法
JP5986499B2 (ja) * 2012-12-21 2016-09-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5982312B2 (ja) * 2013-03-22 2016-08-31 株式会社東芝 半導体装置
US9147642B2 (en) * 2013-10-31 2015-09-29 Nanya Technology Corporation Integrated circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11444005B2 (en) 2017-10-19 2022-09-13 Sony Semiconductor Solutions Corporation Semiconductor device, imaging device, and manufacturing apparatus
TWI695484B (zh) * 2018-03-20 2020-06-01 日商東芝記憶體股份有限公司 半導體裝置
TWI690002B (zh) * 2018-05-24 2020-04-01 日商東芝記憶體股份有限公司 半導體裝置及其之製造方法
US10943852B2 (en) 2018-05-24 2021-03-09 Toshiba Memory Corporation Semiconductor device and method for manufacturing the same
TWI818060B (zh) * 2018-08-31 2023-10-11 日商索尼半導體解決方案公司 半導體裝置、半導體試驗裝置及半導體裝置之試驗方法
US11927622B2 (en) 2018-08-31 2024-03-12 Sony Semiconductor Solutions Corporation Semiconductor device, semiconductor testing device, and semiconductor device testing method

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