TW201730917A - 半導體結構 - Google Patents

半導體結構 Download PDF

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TW201730917A
TW201730917A TW105121364A TW105121364A TW201730917A TW 201730917 A TW201730917 A TW 201730917A TW 105121364 A TW105121364 A TW 105121364A TW 105121364 A TW105121364 A TW 105121364A TW 201730917 A TW201730917 A TW 201730917A
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band gap
layer
region
gap layer
semiconductor structure
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TW105121364A
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TWI690976B (zh
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文豪 關
姚福偉
蘇如意
蔡俊琳
亞歷山大 克爾尼斯基
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台灣積體電路製造股份有限公司
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Abstract

在一些實施例中，一種半導體結構包括一第一裝置及一第二裝置。該第一裝置具有一第一表面。該第一裝置包括由一第一材料系統定義之一第一主動區。該第二裝置具有一第二表面。該第二表面與該第一表面共面。該第二裝置包括由一第二材料系統定義之一第二主動區。該第二材料系統不同於該第一材料系統。

Description

半導體結構
本揭露係關於一種半導體結構。
近來，諸如交換器或整流器之功率電子裝置之開發強調功率裝置之製造。通常，功率裝置由III-V族材料製成。借助於半導體製造，功率裝置能夠整合至積體電路或晶片中。以此方式，功率裝置具有更緊湊之大小及變通性。
一些實施例具有以下特徵及/或優點中之一者或組合。在一些實施例中，半導體結構包括具有第一表面之第一裝置及具有第二表面之第二裝置。第二表面與第一表面共面。第一裝置包括由一第一材料系統定義之一第一主動區。第二裝置包括由一第二材料系統定義之一第二主動區。第二材料系統不同於第一材料系統。
在一些實施例中，半導體結構包括矽基板及III-V族層。矽基板在其中具有主動區。III-V族層係在基板上且在矽基板之主動區上方。
在一些實施例中，一種用於製造半導體結構之方法包括至少以下操作。提供第一材料系統之基板。基板具有第一裝置區及第二裝置區。定義第一裝置區中之主動區。第二材料系統之層形成於基板上。第二材料系統不同於第一材料系統。隔離區定義於層的在第一裝置區上方之一部分中。
10‧‧‧半導體結構
11‧‧‧第一裝置
12‧‧‧第二裝置
13‧‧‧層
13A‧‧‧第一區
13B‧‧‧第二區
14‧‧‧基板
14A‧‧‧第一裝置區
14B‧‧‧第二裝置區
20‧‧‧半導體結構
21‧‧‧第一裝置
27‧‧‧隔離區
30‧‧‧半導體結構
31‧‧‧第一裝置
32‧‧‧第二裝置
35‧‧‧經圖案化導電層
36‧‧‧第一能帶間隙層
36A‧‧‧第一部分
36B‧‧‧第二部分
37‧‧‧互連件
38‧‧‧第二能帶間隙層
38A‧‧‧第一部分
38B‧‧‧第二部分
40‧‧‧半導體結構
41‧‧‧第一裝置
110‧‧‧第一表面
112‧‧‧第一主動區
113‧‧‧第一側
114‧‧‧第二側
120‧‧‧第二表面
122‧‧‧第二主動區
123‧‧‧側
124‧‧‧側
132‧‧‧點線
271‧‧‧第一側
272‧‧‧第二側
312‧‧‧第一主動區
314‧‧‧摻雜區
316‧‧‧摻雜區
322‧‧‧第二主動區
412‧‧‧第一主動區
414‧‧‧摻雜區
502‧‧‧基板
502A‧‧‧第一裝置區
502B‧‧‧第二裝置區
504‧‧‧第一主動區
506‧‧‧摻雜區
508‧‧‧第一能帶間隙層
510‧‧‧第二能帶間隙層
512‧‧‧隔離區
514‧‧‧互連件
516‧‧‧經圖案化導電層
W1‧‧‧第一距離
W2‧‧‧第二距離
當結合附圖研讀時，自以下實施方式最好地理解本揭露之態樣。應注意，根據業界中之標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵之尺寸。
圖1為根據本揭露之一些實施例之半導體結構的圖式。
圖2為根據本揭露之一些實施例之半導體結構的圖式。
圖3為根據本揭露之一些實施例之半導體結構的截面。
圖4為根據本揭露之一些實施例之半導體結構的圖式。
圖5A至圖5G為根據本揭露之一些實施例的展示製造半導體裝置之方法的圖式。
圖6為說明根據本揭露之一些實施例的形成半導體結構之方法的流程圖。
以下揭示內容提供用於實施本揭露之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上之形成可包括第一特徵及第二特徵直接接觸地形成之實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成使得第一特徵及第二特徵可不直接接觸之實施例。另外，本揭露可在各種實例中重複參考數字及/或字母。此重複係出於簡化及清楚之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
圖1為根據本揭露之一些實施例之半導體結構10的圖式。參看圖1，半導體結構10包括第一裝置11及第二裝置12。第一裝置11及第二裝置12分別具有第一表面110及第二表面120。第一表面110與第二表面120共面。
在一些實施例中，第一裝置11為Si主動裝置，諸如電晶體、二極體、光電二極體、熔斷器、電阻器、電容器等。舉例而言，電晶體包括金屬氧化物半導體(MOS)電晶體、雙極接面電晶體(BJT)、互補式MOS(CMOS)電晶體等。此外，第一裝置11可包括邏輯裝置、記憶體裝置(例如，靜態隨機存取記憶體(SRAM))、射頻(RF)裝置、輸入/輸出(I/O)裝置、系統單晶片(SoC)裝置、其他合適類型之裝置，或其組合。
在一些實施例中，第二裝置12為高電壓裝置或功率裝置，其通常用作功率電子電路中或積體電路中之切換器或整流器。舉例而言，一些常見功率裝置為功率二極體、閘流體、功率金屬氧化物半導體場效電晶體(MOSFET)、雙極接面電晶體(BJT)及絕緣閘極雙極電晶體(IGBT)。功率二極體或MOSFET按類似於其低功率對應體之原理操作，但能夠攜載大量電流且通常能夠支援關斷狀態下的較大反向偏壓電壓。
第一裝置11包括第一主動區112。第一主動區112位於基板14之第一裝置區14A中。第一裝置區14A為基板14的與第一裝置11相關聯之一部分。基板14及第一主動區112由第一材料系統製成。在一些實施例中，基板14及第一主動區112由矽製成。此外，第一裝置11包括第一裝置區14A上方之層13的第一區13A。層13由不同於第一材料系統之第二材料系統製成。舉例而言，層13由III-V族材料製成，該III-V族材料可為砷化鎵、砷化銦、砷化銦鎵、磷化銦、氮化鎵、銻化銦、銻化鎵、磷化鎵及/或其任何三元或四元化合物，或其混合物或合金。
在一些實施例中，基板14包括矽鍺、砷化鎵、碳化矽或其他合適半導體材料。在一些實施例中，基板14進一步包括摻雜區，諸如P型井及/或N型井(未圖示)。在一些其他實施例中，基板14進一步包括 其他特徵，諸如嵌埋層及/或磊晶層。此外，在一些實施例中，基板14為(諸如)絕緣體上矽(SOI)之絕緣體上半導體。在其他實施例中，半導體基板14包括摻雜磊晶層、梯度半導體層，及/或進一步包括上覆不同類型之另一半導體層的半導體層(諸如，矽鍺層上之矽層)。在一些其他實例中，合成半導體基板包括多層矽結構，或矽基板可包括多層合成半導體結構。在一些實施例中，基板14可包括(諸如)鍺及金剛石之其他元素半導體。在一些實施例中，基板14包括合成半導體，諸如碳化矽、砷化鎵、砷化銦或磷化銦。
類似地，第二裝置12包括層13之第二區13B中的第二主動區122。第二主動區122由第二材料系統構成。在一些實施例中，第二主動區122並不與第一裝置區14A中之第一主動區112重疊。第二主動區122具有由點線132指出之側123。第二主動區122之側123充當第一裝置11與第二裝置12之間的邊界。此外，第二裝置12進一步包括基板14之第二裝置區14B。基板14之第二裝置區14B係與第二裝置12相關聯。第二裝置區14B係在第二主動區122下方。
在一些實施例中，第一表面110及第二表面120形成為層13之表面的共面表面。即，在第一表面110與第二表面120之間實質上不存在台階差。在本實施例中，第一裝置11及第二裝置12緊鄰於彼此。半導體結構10變得更緊湊，且因此半導體結構10具有相對低之區域成本。此外，第一裝置11及第二裝置12在不進行任何接合操作之情況下經整合。此外，在第一表面110與第二表面120之間無台階差進一步促進後續金屬化操作，在金屬化操作中光學微影之品質高度取決於投影表面之高度均一性。
在整合III-V族材料系統與Si材料系統之一些現有半導體結構中，兩個材料系統由接合操作連接，例如，Si材料系統堆疊於III-V族材料系統上。接合操作導致相對高成本。此外，歸因於接合操作，在III-V 族材料系統之表面與Si材料系統之表面之間通常存在台階差異。靠近台階差的區域不能被實施任何的主動裝置，因此會浪費掉預定裝置區。據此，整合裝置之間具有台階差之此半導體結構會消耗更多區域，因此具有相對高之區域成本。
圖2為根據本揭露之一些實施例之半導體結構20的圖式。參看圖2，半導體結構20類似於參看圖1所描述並說明之半導體結構10，差別在於半導體結構20包括第一裝置21中之隔離區27。
隔離區27係在第二材料系統之層13之第一區13A中且在第一主動區112上方。隔離區27經組態以抵抗第二主動區122之載子進入第一裝置21之層13的第一區13A中。隔離區27具有第一側271及與第一側271相對之第二側272。第一側271與第二主動區122之側123重疊，且用以決定第一裝置11與第二裝置12之間的邊界。若隔離區27之第一側271朝向第二主動區122之側124延伸，則第二裝置12之尺寸減小，且第一裝置11之尺寸增加，反之亦然。
此外，第一主動區112具有第一側113及與第一側113相對之第二側114。在本實施例中，隔離區27之第一側271與第二側272之間的第一距離W1大於第一主動區112之第一側113與第二側114之間的第二距離W2。在一些實施例中，第一距離W1與第二距離W2之間的差小於10μm。
由於類似原因，如圖1之實施例中所提供，由於第一裝置21之第一表面110與第二裝置12之第二表面120共面，因此半導體結構20之相對低的區域成本及製造歸因於無接合操作要求而變得更簡單。
圖3為根據本揭露之一些實施例之半導體結構30的截面。參看圖3，半導體結構30類似於參看圖2所描述並說明之半導體結構20，差別在於半導體結構30包括第一裝置31及第二裝置32之更多細節。
第一裝置31及第二裝置32分別類似於參看圖2所描述並說明之第 一裝置21及第二裝置12，差別在於第一裝置31包括第一主動區312及該第一主動區中之兩個摻雜區314及316、第二裝置32包括第二主動區322且第一裝置31及第二裝置32包括第二材料系統層。第二材料系統具有第一能帶間隙層36及第二能帶間隙層38。
第一主動區312以及兩個摻雜區314及316定義主動裝置，諸如電晶體。舉例而言，主動區312摻雜有p型雜質，且摻雜區314及316摻雜有n型雜質。以此方式，第一主動區312及摻雜區314、316定義n型半導體裝置，諸如n通道金屬氧化物半導體場效電晶體(MOSFET)。替代地，例如，第一主動區312摻雜有n型雜質，且摻雜區314及316摻雜有p型雜質。以此方式，第一主動區312以及摻雜區314及316定義p型半導體裝置，諸如p通道金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor，MOSFET)。主動裝置經由互連件37及第二材料系統之第二能帶間隙層38上之經圖案化導電層35以通信方式耦接至另一裝置。舉例而言，互連件37為貫穿GaN通路(thorough-GaN-Via，TGV)，且經圖案化導電層35為前端操作之後的第一金屬層。互連件37穿過包括第一能帶間隙層36及第二能帶間隙層38之層，且經組態以連接一個末端處之經圖案化導電層35與另一末端處之第一主動區312。
第一能帶間隙層36及第二能帶間隙層38由第二材料系統製成。在一些實施例中，第二能帶間隙大於第一能帶間隙。在本實施例中，第一能帶間隙層36為GaN且第二能帶間隙層38為AlGaN，而本揭露不限於此。第一能帶間隙層36及第二能帶間隙層38可為砷化鎵、砷化銦、砷化銦鎵、磷化銦、氮化鎵、銻化銦、銻化鎵、磷化鎵及/或其任何三元或四元化合物或其混合物或合金。
此外，第一裝置31包括第一能帶間隙層36之第一部分36A及第二能帶間隙層38之第一部分38A。第一部分36A及第一部分38A與第一裝 置31相關聯。第一能帶間隙層36之第一部分36A係在基板14之第一裝置區14A上。第二能帶間隙層38之第一部分38A係在第一能帶間隙層36之第一部分36A上。
隔離區27係在第一裝置區14A上方且跨越第一能帶間隙層36之第一部分36A與第二能帶間隙層38之第二部分38A之間的界面。以此方式，由於類似原因，如在圖2之實施例中所提供，由於帶負電離子排斥來自第二裝置32之第二主動區322的電子，因此產生於第二裝置32中之二維電子氣體(two-dimensional electron gas，2-DEG)不流動至第一裝置31的任一部分。
另一方面，第二裝置32包括第一能帶間隙層36之第二部分36B及第二能帶間隙層38之第二部分38B。第二部分36B及第二部分38B與第二裝置32相關聯。第一能帶間隙層36之第二部分36B係在基板14之第二裝置區14B上。第二能帶間隙層38之第二部分38B係在第一能帶間隙層36之第二部分36B上。
第二主動區322由第一能帶間隙層36及第二能帶間隙層38定義出。由於第二能帶間隙層38之能帶間隙大於第一能帶間隙層36之能帶間隙，因此能帶間隙不連續性存在於第一能帶間隙層36與第二能帶間隙層38之間。第二能帶間隙層38中來自壓電效應之電子落入第一能帶間隙層36中，從而導致第一能帶間隙層36中高度可遷移導電電子的極薄層(亦即，第二主動區322)。2-DEG之薄層位於第一能帶間隙層36與第二能帶間隙層38之間的界面處。因此，載子通道具有高電子遷移率，此係因為第一能帶間隙層36不經摻雜或經無意地摻雜，且電子可自由地移動而無與雜質之衝突或實質上減小之衝突。請注意，為了說明清楚，誇示第二主動區322之尺寸。
對於與諸如第一裝置31之主動裝置之另一裝置的通信，若第二能帶間隙層36之第二部分36B及第二能帶間隙層38之第二部分38B定 義電晶體，則亦存在第二能帶間隙層38之第二部分38B上的導電圖案化層35，且導電圖案化層35耦接至第二主動區322且進一步耦接至電晶體之汲極、閘極及源極。
在本實施例中，第一表面110及第二表面120係第二能帶間隙層38之表面。因此，第一表面110與第二表面120共面。由於類似原因，如圖1之實施例中所提供，由於第一裝置31之第一表面110與第二裝置32之第二表面120共面，因此每區域之成本為相對低的，且半導體結構30之製造歸因於無接合操作要求而變得更簡單。
圖4為根據本揭露之一些實施例之半導體結構40的截面。參看圖4，半導體結構40類似於參看圖3所描述並說明之半導體結構30，差別在於半導體結構40包括不同之第一裝置41。
第一裝置41類似於參看圖3描述並說明之第一裝置31，差別在於第一裝置41包括第一主動區412與基板14之第一裝置區14A中之摻雜區414。第一主動區412及摻雜區414定義齊納二極體(或整流器)。摻雜區414充當曾納二極體之陽極，且第一主動區充當曾納二極體之陰極。互連件37穿過第一能帶間隙層36及第二能帶間隙層38，且經組態以連接一個末端處之摻雜區414及第一主動區412及另一末端處的經圖案化導電層35。
如圖1之實施例中所提供的類似原因，由於第一裝置41之第一表面110與第二裝置32之第二表面120共面，因此每區域之成本為相對低的，且半導體結構40之製造歸因於無接合操作要求而變得更簡單。
圖5A至圖5G為根據一些實施例之展示製造半導體結構之方法的圖式。參看圖5A，提供基板502。基板502包括第一裝置區502A及第二裝置區502B。第一裝置區502A及第二裝置區502B分別與半導體結構之第一裝置及第二裝置相關聯。在一些實施例中，基板502包括p型基板。
參看圖5B，由(例如)離子植入操作形成第一主動區504於基板502中。在一些實施例中，第一主動區504摻雜有n型雜質。在其他實施例中，第一主動區504摻雜有p型雜質。
參看圖5C，由(例如)離子植入操作繼之以退火操作而形成摻雜區506於第一主動區504中。在一些實施例中，摻雜區506摻雜有n型雜質。在其他實施例中，摻雜區506摻雜有p型雜質。藉由具有n型雜質之第一主動區504及具有p型雜質之摻雜區506，PMOS電晶體形成於基板502中。相反地，藉由具有p型雜質之第一主動區504及具有n型雜質之摻雜區506，NMOS電晶體形成於基板502中。摻雜區506充當NMOS電晶體或PMOS電晶體之汲極或源極。
參看圖5D，由(例如)沈積操作形成第一能帶間隙層508於基板502上。此外，由(例如)沈積操作形成第二能帶間隙層510於第一能帶間隙層508上。第二能帶間隙層510之能帶間隙大於第一能帶間隙層508之能帶間隙。舉例而言，第一能帶間隙層508由GaN之材料製成，且第二能帶間隙層510由AlGaN材料製成。
參看圖5E，藉由，例如一植入操作，在與第一裝置區502A相關聯的暴露第二能帶間隙層510中植入負電離子，在第一能帶間隙層508及第二能帶間隙層510中形成隔離區512。具體言之，隔離區512橫越與第一裝置區相關聯之第一能帶間隙層508與第二能帶間隙層510之間的界面。
參看圖5F，互連件514由(例如)以下操作形成於第一能帶間隙層508及第二能帶間隙層510中：形成暴露摻雜區506及第一主動區504之一部分的通路溝槽之蝕刻操作，及繼之以將導電材料沈積於通路溝槽中以形成互連件514之沈積操作。舉例而言，互連件514為貫穿GaN通路(TGV)。第一主動區504及摻雜區506定義之電晶體經由互連件514以通信方式耦接至另一裝置。
參看圖5G，藉由(例如)沈積操作繼之以蝕刻操作，經圖案化導電層516形成於第二能帶間隙層510上。請注意，經圖案化導電層516可定位於第一裝置區502A及第二裝置區502B兩者上。在一些實施例中，經圖案化導電層516為前端操作之後的第一金屬層。
在本實施例中，半導體結構之表面為第二能帶間隙層510之表面。因此，第一裝置(參看點線之右側處且其主動區藉由第一材料系統定義之裝置)之表面與第二裝置(參看點線之左側處且其主動區藉由第二材料系統定義之裝置)之表面共面。由於類似原因，如圖1之實施例中所提供，半導體結構之每區域之成本為相對低的，且半導體結構之製造歸因於無對接合操作之要求而變得更簡單。
圖6為說明根據本揭露之一些實施例的形成半導體結構之方法的流程圖。參看圖6，在操作600中，提供第一材料系統之基板。基板包括第一裝置區及第二裝置區。第一裝置區及第二裝置區分別與第一裝置及第二裝置相關聯。該基板類似於分別參看圖4及圖5A所描述並說明之基板14或基板502。此外，第一裝置區及第二裝置區類似於參看圖3所說明並描述之第一裝置區14A及第二裝置區14B。在一實施例中，基板為p型基板。
在操作602中，在第一裝置區中定義第一主動區，且接著在第一主動區中定義摻雜區。在一實施例中，第一主動區為n型井，且摻雜區包括p型雜質，從而產生PMOS電晶體。在另一實施例中，第一主動區域為p型井，且摻雜區包括n型雜質。
在操作604中，使第二材料系統之第一能帶間隙層形成於基板上。第一能帶間隙層類似於參看圖3所描述並說明之第一能帶間隙層36。第二材料系統不同於第一材料系統。舉例而言，第一材料系統包括矽，而第二材料系統包括III-V族材料，該III-V族材料可為砷化鎵、砷化銦、砷化銦鎵、磷化銦、氮化鎵、銻化銦、銻化鎵、磷化鎵 及/或其任何三元或四元化合物，或其混合物或合金。在本實施例中，第一能帶間隙層為GaN層。
在操作606中，使第二材料系統之第二能帶間隙層形成於第一能帶間隙層上。第二能帶間隙層類似於參看圖3描述並說明之第二能帶間隙層38。第二能帶間隙層之能帶間隙大於第一能帶間隙層之能帶間隙。以此方式，第二主動區由第一能帶間隙層與第二能帶間隙層之界面而定義。在本實施例中，第二能帶間隙層為AlGaN層。
在操作606之後，在操作608中，在第一能帶間隙層與第二能帶間隙層之間的界面處定義隔離區。隔離區類似於參看圖3描述並說明之隔離區27。由於如圖2之實施例中所提供的類似原因，隔離區經組態以排斥來自第二裝置區502B之第二主動區的電子。
在操作610中，形成互連件。互連件穿過第一裝置區502A處之第一能帶間隙層及第二能帶間隙層，且連接一個末端處之第一主動區、另一末端處稍後論述的導電層。
在操作612中，經圖案化導電層形成於第二能帶間隙層上且與互連件相結合。經圖案化導電層經由互連件電耦接至第一主動區。
一些實施例具有以下特徵及/或優點中之一者或組合。在一些實施例中，半導體結構包括具有第一表面之第一裝置及具有第二表面之第二裝置。第二表面與第一表面共面。第一裝置包括由一第一材料系統定義之一第一主動區。第二裝置包括由一第二材料系統定義之一第二主動區。第二材料系統不同於第一材料系統。
在一些實施例中，半導體結構包括矽基板及III-V族層。矽基板在其中具有主動區。III-V族層係在基板上且在矽基板之主動區上方。
在一些實施例中，一種用於製造半導體結構之方法包括至少以下操作。提供第一材料系統之基板。基板具有第一裝置區及第二裝置區。定義第一裝置區中之主動區。第二材料系統之層形成於基板上。 第二材料系統不同於第一材料系統。隔離區定義於層的在第一裝置區上方之一部分中。
前文概述若干實施例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，其可易於使用本揭露作為用於設計或修改用於實現本文中所介紹之實施例的相同目的及/或達成相同優點的其他操作及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替代及更改。
10‧‧‧半導體結構
11‧‧‧第一裝置
12‧‧‧第二裝置
13‧‧‧層
13A‧‧‧第一區
13B‧‧‧第二區
14‧‧‧基板
14A‧‧‧第一裝置區
14B‧‧‧第二裝置區
110‧‧‧第一表面
112‧‧‧第一主動區
120‧‧‧第二表面
122‧‧‧第二主動區
123‧‧‧側
132‧‧‧點線

Claims (10)

  1. 一種半導體結構，其包含：具有一第一表面之一第一裝置，該第一裝置包括：由一第一材料系統定義之一第一主動區；及具有一第二表面之一第二裝置，該第二表面與該第一表面共面，該第二裝置包括：藉由一第二材料系統定義之一第二主動區，其中該第二材料系統不同於該第一材料系統。
  2. 如請求項1之半導體結構，其中該第一裝置及該第二裝置進一步包括一基板，該基板包含與該第一裝置相關聯之一第一裝置區及與該第二裝置相關聯之一第二裝置區；該第一主動區放置於該第一裝置區中。
  3. 如請求項1之半導體結構，其中該第一裝置及該第二裝置進一步包括該第二材料系統之一層，且該第一表面及該第二表面為該第二材料系統之該層的一頂表面。
  4. 如請求項3之半導體結構，其中該第二主動區係在該層中。
  5. 如請求項3之半導體結構，其中該第一裝置包含在該第二材料系統之該層中且在該第一主動區上方之一隔離區。
  6. 如請求項3之半導體結構，其中該層包含一第一能帶間隙層及在該第一能帶間隙層上之一第二能帶間隙層，該第二能帶間隙層之能帶間隙大於該第一能帶間隙層之能帶間隙。
  7. 一種半導體結構，其包含：一矽基板，其中具有一主動區；及在該基板上且在該矽基板之該主動區上方的一III-V族層。
  8. 如請求項7之半導體結構，其中該III-V族層包括： 該基板上之一第一能帶間隙層；及該第一能帶間隙層上之一第二能帶間隙層，其中該第二能帶間隙層之能帶間隙大於該第一能帶間隙層之能帶間隙。
  9. 如請求項8之半導體結構，其進一步包含：跨越該第一能帶間隙層與該第二能帶間隙層之間的一界面之一隔離區。
  10. 一種用於製造一半導體結構之方法，其包含：提供一第一材料系統之一基板，該基板具有一第一裝置區及一第二裝置區；在該第一裝置區中定義一主動區；及在該基板上形成一第二材料系統之一層，該第二材料系統不同於該第一材料系統；及在該層之在該第一裝置區上方之一部分中定義一隔離區。
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