TW201729425A - 功率金屬氧化物半導體場效電晶體及用於製造其之方法 - Google Patents
功率金屬氧化物半導體場效電晶體及用於製造其之方法 Download PDFInfo
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- TW201729425A TW201729425A TW105140723A TW105140723A TW201729425A TW 201729425 A TW201729425 A TW 201729425A TW 105140723 A TW105140723 A TW 105140723A TW 105140723 A TW105140723 A TW 105140723A TW 201729425 A TW201729425 A TW 201729425A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
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- 229910052732 germanium Inorganic materials 0.000 claims description 5
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
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- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 2
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Abstract
係提供一種半導體裝置及製造其之方法。該半導體裝置係包含一井區、一第一摻雜區、一汲極區、一源極區、以及一閘電極。該第一摻雜區係具一第一傳導性類型且位在該井區內的一第一側。該汲極區係具該第一傳導性類型且在該第一摻雜區內。該源極區係具該第一傳導性類型且在該井區內的一第二側,其中該第二側係與該第一側相對。該閘電極係在該井區上方且在該源極區與該汲極區之間。該汲極區的一表面以及該源極區的一表面定義出一通道,以及該源極區的該表面直接接觸該井區。
Description
本揭露係關於一種半導體結構及製造其之方法以及一種金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor,MOSFET)。
半導體積體電路(integrated circuit,IC)產業經歷了快速的成長。於IC材料和設計的技術進步已產生其中各代具有比上一代更小且更複雜之電路的數代IC。然而,這些進步增加了加工及製造IC的複雜性,且為了實現這些進步,需要在IC加工及製造上有相似的發展。在積體電路進化的過程中,已普遍增加功能密度(即,每晶片面積被互連裝置的數目),同時已減少幾何大小(即,使用成形加工製程可創建的最小組件(或線))。 IC可含有具有摻雜區之電晶體裝置。隨著電晶體尺寸的不斷縮小,更難以防止摻雜區的非所欲向外擴散。此向外擴散可干擾電晶體裝置操作及/或降低電晶體性能。此外,縮小電晶體尺寸可能會導致諸如電流擁擠、高源極/汲極電阻、以及非最佳摻雜概況的問題。
根據一實施例,一種半導體裝置係包含一井區、一第一摻雜區、一汲極區、一源極區、以及一閘電極。該第一摻雜區係具一第一傳導性類型且位在該井區內的一第一側。該汲極區係具該第一傳導性類型且在該第一摻雜區內。該源極區係具該第一傳導性類型且在該井區內的一第二側,其中該第二側係與該第一側相對。該閘電極係在該井區上方且在該源極區與該汲極區之間。該汲極區的一表面以及該源極區的一表面定義出一通道,以及該源極區的該表面直接接觸該井區。 根據另一實施例,一種半導體裝置係包含一井區、一輕摻雜區、一汲極區、一源極區、一閘電極以及間隔件。該輕摻雜區係具一第一傳導性類型且位在該井區內的一第一側。該汲極區係具該第一傳導性類型且在該輕摻雜區內。該源極區係具該第一傳導性類型且在該井區內的一第二側,其中該第二側係與該第一側相對。該閘電極係在該井區上方且在該源極區與該汲極區之間。該等間隔件係位在該閘電極的二側。各間隔件的寬度與該閘電極的寬度的一比係在自約1:4至約1:7的一範圍中。 根據另一實施例,一種製造一半導體裝置之方法係包含形成一井區,植入一輕摻雜區在該井區的一第一側中,以一第一深度植入一第一汲極區在該輕摻雜區中,以一第二深度植入一第二汲極區在該輕摻雜區中,植入一源極區在該井區內的一第二側中,該第二側係與該第一側相對,以及形成一閘電極在該井區上方。該第二深度係大於該第一深度。
本揭露實施例之製作以及使用係詳細討論如下。然而,應了解該等實施例提供許多可在廣泛種類的特定背景下體現之可應用發明性概念。所討論的特定實施例僅為說明性,且不限定本揭露之範疇於此。 將理解,當一元件或層被稱作"在...上"、“連接至”、或“耦合至”另一元件或層時,其可以是直接在其他元件或層上、或直接連接或耦合至其他元件或層、或者可出現中介元件或層。相反地,當一元件被稱作"直接在...上"、“直接連接至”、或“直接耦合至”另一元件或層時,沒有出現中介元件或層。 將理解,雖然可於本文中使用辭彚第一、第二、第三、等來描述各種元件、組件、區、層、及/或區段,但這些元件、組件、區、層、及/或區段不應受這些辭彚所限。這些辭彚僅用於將一個元件、組件、區、層、或區段與另一個區、層、或區段區別。因此,下面所描述的第一元件、組件、區、層、或區段可被稱為第二元件、組件、區、層、或區段而不會悖離本發明性概念的教示。 空間相關詞彙,諸如“之下”、“下面”、“下”、“上面”、“上”和類似詞彙,可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個(或多個)元件或特徵的關係而使用於本文中。將理解到,除了圖式中所畫的方位外,這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。例如,若將圖示中之裝置翻面,被描述成在其他元件或特徵“下面”或“之下”之元件則將定位成在其他元件或特徵“上面”。因此,例示性詞彙“上面”或“下面”可涵蓋上面方位及下面方位二者。該裝置可以其他方式定向(旋轉90度或於其它方位),據此解釋在本文中所使用的這些空間相關說明符。 本文中所使用的名詞只是為了描述具體例示實施例目的而不是意圖限制本發明性概念。除非內文中有明確另行指明,於本文中使用時,單數形式“一(a)”、“一(an)”、以及“該(the)”係意圖也包括複數形式。將進一步理解到,辭彚“包含(comprises)”及/或“包含(comprising)”—當於說明書中使用時,指明所稱特徵、整數、步驟、操作、元件、及/或組件之存在,但並不排除一或多個其它特徵、整數、步驟、操作、元件、組件、及/或其群組之存在或增加。 本說明書全文中提及"一個實施例(one embodiment)”或“一實施例(an embodiment)”係意指相關於該實施例描述的一具體之特徵、結構、或特性係包括在至少一個實施例中。因此,在本說明書全文的各種位置中出現短語“在一個實施例中(in one embodiment)”或“在一實施例中(in an embodiment)”不必然都指相同實施例。再者,具體之特徵、結構、或特性可以以任何合適的方式組合於一或多個實施例中。應了解,以下圖示不是依比例繪製,反而這些圖示僅意圖用於例示說明。 圖1係根據本揭露的一個實施例的金屬氧化物半導體場效電晶體(MOSFET)1。MOSFET包括基板10、輕摻雜區11、汲極區12、源極區13、閘電極14、以及介電層15。 基板10可以是p型摻雜基板、或n型摻雜基板,其意指半導體基板10可經n型或p型雜質摻雜。該基板10係自矽、砷化鎵、矽鍺、矽碳、或在半導體裝置加工中使用的其它已知半導體材料形成。雖然在本文中所呈現之經繪示實例中使用半導體基板,在其他替代性實施例中,可使用磊晶生長半導體材料或絕緣體上矽(silicon on insulator,SOI)層作為基板10。在其它實施例中,基板10可以是井區。 本技術領域中已知,摻雜物雜質可植入到半導體材料中以形成p型或n型材料。取決於摻雜物的濃度,p型材料可進一步分類成p++型材料、p+型材料、p型材料、p−型材料、p−−型材料。若稱材料為p型材料,其係經p型雜質摻雜且其可以是p++型材料、p+型材料、p型材料、p−型材料、p−−型材料的任一者。相似地,n型材料可進一步分類成n++型材料、n+型材料、n型材料、n−型材料、n−−型材料。若稱材料為n型材料,其係經n型雜質摻雜且其可以是n++型材料、n+型材料、n型材料、n−型材料、n−−型材料的任一者。p型材料的摻雜物原子包括例如硼。在n型材料中,摻雜物原子包括例如磷、砷、及銻。可透過離子植入製程完成摻雜。當與光微影製程耦合時,藉由將原子植入暴露的區域中並遮蓋其他區域的方式可在選定的區域中實施摻雜。也可使用熱驅動或退火循環以利用熱擴散來擴大或延伸先前摻雜區。作為替代者,半導體材料的一些磊晶沉積允許磊晶製程期間之原位摻雜。可透過某些材料,諸如薄氧化物層完成植入係通常知識。 所述之井區的摻雜濃度量以及擴散可隨所使用製程以及具體設計而變化。在p型材料或n型材料的摻雜濃度可在自1014
個原子/cm3
至1022
個原子/cm3
之範圍,例如具有高於約1018
/cm3
濃度的p+/n+材料。可使用一些其它濃度範圍,諸如具有小於1014
個原子/cm3
摻雜濃度的n−−/p−−材料、具有自1014
個原子/cm3
至1016
個原子/cm3
範圍之摻雜濃度的n−/p−材料、具有自1016
個原子/cm3
至1018
個原子/cm3
範圍之摻雜濃度的n/p材料、具有自1018
個原子/cm3
至1020
個原子/cm3
範圍之摻雜濃度的n+/p+材料、以及具有大於1020
個原子/cm3
範圍之摻雜濃度的n++/p++材料。可使用進一步替代濃度範圍,諸如具有約1015
至1018
個原子/cm3
範圍之摻雜濃度的n−−/p−−材料、以及n−/p−材料,其具有之摻雜濃度係n−−/p−−材料的濃度的5至100倍濃。 輕摻雜區11係具第一傳導性類型且形成在基板10內的一側。輕摻雜區11可藉由實施本技術領域中已知的離子植入製程形成。在一些實施例中,在圖1中所顯示之MOSFET係n型金屬氧化物半導體(n-type metal-oxide-semiconductor,NMOS)裝置,因此具有範圍在自約80KeV至約90KeV能量之N型摻雜物諸如磷可用來形成輕摻雜區11。在其它實施例中,對於p型金屬氧化物半導體(p-type metal-oxide-semiconductor,PMOS)裝置(未繪示),P型摻雜物諸如硼可用來形成輕摻雜區11。 汲極區12係具第一傳導性類型且在輕摻雜區11內。汲極區12可具有汲極接點(圖中未顯示)。汲極區12包含第一汲極區12a以及第二汲極區12b。第一汲極區12a以及第二汲極區12b二者都在輕摻雜區11內。第一汲極區具有從基板10的頂部表面測量的接面深度d1。第二汲極區12b具有從基板10的頂部表面測量的接面深度d2。接面深度d2係大於接面深度d1。在一些實施例中,接面深度d1係在自約0.01 μm至約0.022 μm之範圍中,以及接面深度d2係在自約0.02 μm至約0.054 μm之範圍中。在一些實施例中,第一汲極區12a以及第二汲極區12b係由不同材料所形成。例如,第一汲極區12a可由具有在自約10KeV至約30KeV範圍中之能量的砷所形成,以及第二汲極區12b可由具有在自約20KeV至約40KeV範圍中之能量的磷所形成。 源極區13係具第一傳導性類型且在基板10內的另一側。源極區13可具有汲極接點(圖中未顯示)。源極區13包含第一源極區13a以及第二源極區13b。第一源極區13a具有從基板10的頂部表面測量的接面深度d3。第二源極區13b具有從基板10的頂部表面測量的接面深度d4。接面深度d4係大於接面深度d3。在一些實施例中,接面深度d3係在自約0.01 μm至約0.022 μm之範圍中,以及接面深度d4係在自約0.02 μm至約0.054 μm之範圍中。在一些實施例中,第一源極區13a以及第二源極區13b係由不同材料所形成。例如,第一源極區13a可由具有在自約10KeV至約30KeV範圍中之能量的砷所形成,以及第二源極區13b可由具有在自約20KeV至約40KeV範圍中之能量的磷所形成。 汲極區12的表面121以及源極區13的表面131係在其等之間定義出通道。源極區13的表面131直接接觸井區10。在一些實施例中,源極區13的所有表面直接接觸井區10。因此,源極區13不被輕摻雜區環繞。 介電層15係在基板10的頂部表面上且在汲極區12與源極區之間。介電層15覆蓋輕摻雜區11的一部分、汲極區12的一部分、以及源極區13的一部分。因此,介電層15與汲極區12的一部分或源極區的一部分重疊。介電層15與汲極區12或源極區13的重疊係約0.3 μm。介電層15可包括氧化矽、氮化矽、氧氮化矽、高k介電材料、其組合、或其之多層。高k介電材料可包含TiO2
、HfZrO、Ta2
O3
、HfSiO4
、ZrO2
、ZrSiO2
、其組合、或其它合適的材料。介電層15可具有厚度係在約100埃(Å)與約2,500 Å之間,雖然也可用不同厚度。 閘電極14係在介電層15上。閘電極14完全覆蓋介電層15,且因此閘電極14與汲極區12的一部分或源極區13的一部分重疊。閘電極14可包括導電材料,諸如摻雜多晶矽、金屬、金屬合物、或類似物。矽化物層(圖中未顯示)可藉由自對準矽化物製程形成在閘電極上。 間隔件16a、16b係在基板10上。間隔件16a係在閘電極14的一側且與由閘電極14的側表面與介電層15的側表面所定義的共平面表面接觸。間隔件16b係在閘電極14的相對側且與由閘電極14的側表面與介電層15的側表面所定義的共平面表面接觸。間隔件16a、16b係由介電材料所製,諸如氧化矽、氧氮化矽(SiON)、或氮化矽(SiN)。在一些實施例中,閘電極14的寬度W1與間隔件16a或16b的寬度W2的比係在自約4:1至約7:1的範圍中。 在一些實施例中,輕摻雜區會在基板的二側(即,汲極側或源極側)被植入以防止MOSFET有偏移閘極議題。然而,若閘電極的寬度不夠,則源極側的輕摻雜區以及汲極側的輕摻雜區可能彼此實體接觸,而在MOSFET的通道中形成非所欲短路。為了防止該等輕摻雜區彼此接觸,應使用具有較寬寬度之閘電極。本揭露的一個益處在於提供不對稱之輕摻雜概況,而使得較小的閘電極寬度可被實現,且因此縮小電晶體的尺寸。 根據在本揭露之圖1中所顯示之實施例,閘電極14與汲極區12或源極區13部分地重疊以防止MOSFET 1有偏移閘極議題。因此,沒有必要在汲極側以及源極側二者都植入輕摻雜區。如圖1所顯示,係僅在汲極側植入輕摻雜區11。因此,與在汲極側以及源極側二者都具有輕摻雜區之MOSFET相比,在圖1中所顯示之MOSFET 1具有較窄之閘電極14的寬度。MOSFET的通道長度係由閘電極14的寬度所定義,且因此減少閘電極14的寬度會減少MOSFET的通道長度。在一些實施例中,MOSFET 1的通道係習用MOSFET所具者的約58%至66%小(對於NMOS),以及MOSFET 1的通道係習用MOSFET所具者的約60%至70%小(對於PMOS)。減少MOSFET的通道長度會減少導通電阻(Ron)以及閘極電荷,其反而會增加MOSFET的性能。 圖2A至2E係根據一些實施例以剖面圖繪示製造MOSFET的方法。所得MOSFET可以是圖1中所顯示之MOSFET 1。可使用替代方法製作圖1中所顯示之MOSFET 1或該MOSFET的替代性實施例。 如圖2A中所繪示者,係提供基板20。視需要n+埋層(n+ Buried Layer,NBL)可形成在基板20的一部份中(圖中未顯示)。在其它實施例中,主題20可以是井區。基板20可以是p型摻雜基板、或n型摻雜基板,其意指半導體基板20可經n型或p型雜質摻雜。該基板20係自矽、砷化鎵、矽鍺、矽碳、或在半導體裝置加工中使用的其它已知半導體材料形成。雖然在本文中所呈現之經繪示實例中使用半導體基板,在其他替代性實施例中,可使用磊晶生長半導體材料或絕緣體上矽(SOI)層作為基板20。 本技術領域中已知,摻雜物雜質可植入到半導體材料中以形成p型或n型材料。取決於摻雜物的濃度,p型材料可進一步分類成p++型材料、p+型材料、p型材料、p−型材料、p−−型材料。若稱材料為p型材料,其係經p型雜質摻雜且其可以是p++型材料、p+型材料、p型材料、p−型材料、p−−型材料的任一者。類似地,n型材料可進一步分類成n++型材料、n+型材料、n型材料、n−型材料、n−−型材料。若稱材料為n型材料,其係經n型雜質摻雜且其可以是n++型材料、n+型材料、n型材料、n−型材料、n−−型材料的任一者。p型材料的摻雜物原子包括例如硼。在n型材料中,摻雜物原子包括例如磷、砷、及銻。可透過離子植入製程完成摻雜。當與光微影製程耦合時,藉由將原子植入暴露的區域中並遮蓋其他區域的方式可在選定的區域中實施摻雜。也可使用熱驅動或退火循環以利用熱擴散來擴大或延伸先前摻雜區。作為替代者,半導體材料的一些磊晶沉積允許磊晶製程期間之原位摻雜。可透過某些材料,諸如薄氧化物層完成植入係通常知識。 所述之井區的摻雜濃度量以及擴散可隨所使用製程以及具體設計而變化。在p型材料或n型材料的摻雜濃度可在自1014
個原子/cm3
至1022
個原子/cm3
之範圍,例如具有高於約1018
/cm3
濃度的p+/n+材料。可使用一些其它濃度範圍,諸如具有小於1014
個原子/cm3
摻雜濃度的n−−/p−−材料、具有自1014
個原子/cm3
至1016
個原子/cm3
範圍之摻雜濃度的n−/p−材料、具有自1016
個原子/cm3
至1018
個原子/cm3
範圍之摻雜濃度的n/p材料、具有自1018
個原子/cm3
至1020
個原子/cm3
範圍之摻雜濃度的n+/p+材料、以及具有大於1020
個原子/cm3
範圍之摻雜濃度的n++/p++材料。可使用進一步替代濃度範圍,諸如具有約1015
至1018
個原子/cm3
範圍之摻雜濃度的n−−/p−−材料、以及n−/p−材料,其具有之摻雜濃度係n−−/p−−材料的濃度的5至100倍濃。 介電層25係形成在基板20的頂部表面上。介電層25可包括氧化矽、氮化矽、氧氮化矽、高k介電材料、其組合、或其之多層。高k介電材料可包含TiO2
、HfZrO、Ta2
O3
、HfSiO4
、ZrO2
、ZrSiO2
、其組合、或其它合適的材料。介電層25可藉由原子層沉積(atomic layer deposition,ALD)及/或其它合適的方法形成。介電層25可具有厚度係在約100 Å與約2,500 Å之間,雖然也可用不同厚度。 閘電極24係形成在介電層25上並完全覆蓋介電層25。閘電極24可包括導電材料,諸如摻雜多晶矽、金屬、金屬合物、或類似物。矽化物層(圖中未顯示)可藉由自對準矽化物製程形成在閘電極上。根據一些實施例,對於NMOS,閘電極的寬度W1係在自約0.35 μm至約0.4 μm之範圍中,以及對於PMOS,閘電極的寬度W1係在自約0.3 μm至約0.35 μm之範圍中。然而,閘電極的寬度會基於製造製程變化。 參考圖2B,輕摻雜區21係形成在基板20內的一側。在一些實施例中,輕摻雜區21係形成在基板20的井區內的一側。輕摻雜區21可藉由以約30至約45度的傾斜角實施本技術領域中已知的離子植入製程形成。在一些實施例中,在圖2B中所顯示之MOSFET係NMOS裝置,因此具有範圍在自約80KeV至約90KeV能量之N型摻雜物諸如磷可用來形成輕摻雜區21。在其它實施例中,對於PMOS裝置(未繪示),P型摻雜物諸如硼可用來形成輕摻雜區21。 參考圖2C,間隔件26a、26b係形成在基板20上。間隔件26a係形成在閘電極24的一側且與由閘電極24的側表面與介電層25的側表面所定義的共平面表面接觸。間隔件26b係在閘電極24的相對側且與由閘電極24的側表面與介電層25的側表面所定義的共平面表面接觸。間隔件26a、26b係由介電材料所製,諸如氧化矽、氧氮化矽(SiON)、或氮化矽(SiN)。在一些實施例中,間隔件26a、26b係藉由沉積製程諸如電漿增強化學氣相沈積(plasma-enhanced chemical vapor deposition,PECVD)製程形成。也可使用其它可應用沉積製程。在一些實施例中,閘電極24的寬度W1與間隔件26a或26b的寬度W2的比係在自約4:1至約7:1的範圍中。 參考圖2D,第一汲極區22a係藉由離子植入操作而形成在輕摻雜區21內。在一些實施例中,第一汲極區22a的離子植入係以沒有傾斜角實施。第一汲極區的傳導性類型係與輕摻雜區21所具者相同。第一汲極區22a具有從基板20的頂部表面測量的接面深度d1。在一些實施例中,接面深度d1係在自約0.01 μm至約0.022 μm的範圍中。在一些實施例中,第一汲極區22a可包括具有在自約10KeV至約30KeV範圍中之能量的砷。在植入第一汲極區22a期間,第一汲極區22a的摻雜物側向擴散至在間隔件26a以及介電層25下面的基板20的區中。因此,介電層25與第一汲極區22a的一部份重疊。介電層25與第一汲極區22a的重疊係約0.3 μm。 第一源極區23a係藉由植入離子而形成在基板20內。第一源極區23a的傳導性類型係與第一汲極區22a所具者相同。第一源極區23a具有從基板20的頂部表面測量的接面深度d3。在一些實施例中,接面深度d3係在自約0.01 μm至約0.022 μm的範圍中。在一些實施例中,第一源極區23a可包括具有在自約10KeV至約30KeV範圍中之能量的砷。在植入第一源極區23a期間,第一源極區23a的摻雜物側向擴散至在間隔件26b以及介電層25下面的基板20的區中。因此,介電層25與第一源極區23a的一部份重疊。介電層25與第一源極區23a的重疊係約0.3 μm。 參考圖2E,第二汲極區22b係藉由另一離子植入操作而形成在輕摻雜區21內。第二汲極區22b的傳導性類型係與第一汲極區22a所具者相同。第二汲極區22b具有從基板20的頂部表面測量的接面深度d2。接面深度d2係大於接面深度d1。在一些實施例中,接面深度d2係在自約0.02 μm至約0.054 μm的範圍中。在一些實施例中,在第二汲極區22b中的摻雜物係與在第一汲極區22a中所具者不同。第二汲極區22b可包括植入具有在自約20KeV至約40KeV範圍中之能量的磷。在植入第二汲極區22b期間,第二汲極區22b的摻雜物側向擴散至在間隔件26a以及介電層25下面的基板20的區中。因此,介電層25與第二汲極區22b的一部份重疊。介電層25與第二汲極區22b的重疊係約0.3 μm。 第二源極區23b係藉由植入離子而形成在基板20內。第二源極區23b的傳導性類型係與第一源極區23a所具者相同。第二源極區23b具有從基板20的頂部表面測量的接面深度d4。接面深度d4係大於接面深度d3。在一些實施例中,接面深度d4係在自約0.02 μm至約0.054 μm的範圍中。在一些實施例中,在第二源極區23b中的摻雜物係與在第一源極區23a中所具者不同。第二源極區23b可包括植入具有在自約20KeV至約40KeV範圍中之能量的磷。在植入第二源極區23b期間,第二源極區23b的摻雜物側向擴散至在間隔件26b以及介電層25下面的基板20的區中。因此,介電層25與第二源極區23b的一部份重疊。介電層25與第二源極區23b的重疊係約0.3 μm。可實施快速熱退火(rapid thermal annealing,RTA)操作以促進側向擴散。在一些實施例中,係實施RTA以退火第一汲極區22a、第二汲極區22b、第一源極區23a以及第二源極區23b。在一些實施例中,RTA製程係實施於約1010~1020攝氏度以及10秒以促進摻雜物的側向擴散,尤其是在第一源極區23a以及第二源極區23b中。 如上面所述,在一些實施例中,為了避免偏移閘極議題,會在基板的二側(即,汲極側或源極側)都植入輕摻雜區,造成增加之閘電極寬度。為了解決此問題,一些實施例會將在源極側的輕摻雜區以芯輕摻雜區(即,輕摻雜區加上在芯區之口袋植入物,而非I/O區)置換。然而,此額外的口袋植入物係設計用以減輕裝置穿通,但會產生由於重摻雜本性所致之較高閾值電壓。根據一些實施例,本揭露提供不對稱之輕摻雜結構,具有僅井區的一側具備輕摻雜區。偏移閘極議題可藉由下列規避:採用合適的RTA以及合適的閘極間隔件寬度,而使得在源極或汲極(無論哪個沒有輕摻雜區)中的摻雜物可以適當地朝在閘電極下面且處在閘極氧化物之下的區擴散。 根據本揭露之圖2A至2E所顯示之實施例,由於間隔件26a、26b的寬度以及用以植入第一汲極區22a、第二汲極區22b、第一源極區23a、第二源極區23b之條件(即,能量、濃度、物種以及摻雜深度)被最佳化,係確保來自源極區以及汲極區二者的摻雜物會在閘電極下面擴散,以防止MOSFET有偏移閘極議題。因此,沒有必要在汲極側以及源極側二者都形成輕摻雜區。因此,與在汲極側以及源極側二者都具有輕摻雜區之MOSFET相比,在圖2E中所顯示之MOSFET具有較窄之閘電極24的寬度。MOSFET的通道長度係由閘電極24的寬度所定義,且因此減少閘電極24的寬度會減少MOSFET的通道長度。在一些實施例中,MOSFET的通道係習用MOSFET所具者的約58%至66%小(對於NMOS),以及MOSFET的通道係習用MOSFET所具者的約60%至70%小(對於PMOS)。減少MOSFET的通道長度會減少導通電阻(Ron)以及閘極電荷,其反而會增加MOSFET的性能。 圖2A至2E所顯示之製程僅為說明性且而不是限制性。可以有製程步驟的其它變化,且可以不同順序實施製程步驟。其他製程步驟可接續在圖2A至2E所顯示之製程之後。 鑒於上述,在一些實施例中,係藉由減少MOSFET的通道長度而提供一種具有較低導通電阻之MOSFET,減少MOSFET的通道長度反而會增加MOSFET的性能。 根據一實施例,一種半導體裝置係包含一井區、一第一摻雜區、一汲極區、一源極區、以及一閘電極。該第一摻雜區係具一第一傳導性類型且位在該井區內的一第一側。該汲極區係具該第一傳導性類型且在該第一摻雜區內。該源極區係具該第一傳導性類型且在該井區內的一第二側,其中該第二側係與該第一側相對。該閘電極係在該井區上方且在該源極區與該汲極區之間。該汲極區的一表面以及該源極區的一表面定義出一通道,以及該源極區的該表面直接接觸該井區。 根據另一實施例,一種半導體裝置係包含一井區、一輕摻雜區、一汲極區、一源極區、一閘電極以及間隔件。該輕摻雜區係具一第一傳導性類型且位在該井區內的一第一側。該汲極區係具該第一傳導性類型且在該輕摻雜區內。該源極區係具該第一傳導性類型且在該井區內的一第二側,其中該第二側係與該第一側相對。該閘電極係在該井區上方且在該源極區與該汲極區之間。該等間隔件係位在該閘電極的二側。各間隔件的寬度與該閘電極的寬度的一比係在自約1:4至約1:7的一範圍中。 根據另一實施例,一種製造一半導體裝置之方法係包含形成一井區,植入一輕摻雜區在該井區的一第一側中,以一第一深度植入一第一汲極區在該輕摻雜區中,以一第二深度植入一第二汲極區在該輕摻雜區中,植入一源極區在該井區內的一第二側中,該第二側係與該第一側相對,以及形成一閘電極在該井區上方。該第二深度係大於該第一深度。 前面列述了數個實施例的特徵以便本技術領域具有通常知識者可更佳地理解本揭露之態樣。本技術領域具有通常知識者應了解他們可輕易地使用本揭露作為用以設計或修改其他裝置或電路之基礎以實現本文中所介紹實施例的相同目的或達成本文中所介紹實施例的相同優點。本技術領域具有通常知識者也應體認到此等均等結構不會背離本揭露之精神及範疇,以及他們可在不背離本揭露之精神及範疇下做出各種改變或變更。
1‧‧‧MOSFET
10‧‧‧基板
11、21‧‧‧輕摻雜區
12‧‧‧汲極區
12a、22a‧‧‧第一汲極區
12b、22b‧‧‧第二汲極區
13‧‧‧源極區
13a、23a ‧‧‧第一源極區
13b、23b‧‧‧第二源極區
14、24‧‧‧閘電極
15、25‧‧‧介電層
16a、16b、26a、26b‧‧‧間隔件
20‧‧‧基板/主題
121、131‧‧‧表面
d1、d2、d3、d4‧‧‧接面深度
W1、W2‧‧‧寬度
10‧‧‧基板
11、21‧‧‧輕摻雜區
12‧‧‧汲極區
12a、22a‧‧‧第一汲極區
12b、22b‧‧‧第二汲極區
13‧‧‧源極區
13a、23a ‧‧‧第一源極區
13b、23b‧‧‧第二源極區
14、24‧‧‧閘電極
15、25‧‧‧介電層
16a、16b、26a、26b‧‧‧間隔件
20‧‧‧基板/主題
121、131‧‧‧表面
d1、d2、d3、d4‧‧‧接面深度
W1、W2‧‧‧寬度
本揭露的一或多個實施例的詳情係陳述於下面說明及隨附圖式中。本揭露的其他特徵與優點將從說明書、圖式及申請專利範圍明顯得知。 圖1係根據一些實施例之MOSFET的示意圖。 圖2A至2E係根據一些實施例繪示製造MOSFET之製程。 在各式圖式中之類似參考符號係指類似元件。
1‧‧‧MOSFET
10‧‧‧基板
11‧‧‧輕摻雜區
12‧‧‧汲極區
12a‧‧‧第一汲極區
12b‧‧‧第二汲極區
13‧‧‧源極區
13a‧‧‧第一源極區
13b‧‧‧第二源極區
14‧‧‧閘電極
15‧‧‧介電層
16a、16b‧‧‧間隔件
121、131‧‧‧表面
d1、d2、d3、d4‧‧‧接面深度
W1、W2‧‧‧寬度
Claims (10)
- 一種半導體結構,其包含: 一井區; 一第一摻雜區,具一第一傳導性類型且位在該井區內的一第一側; 一汲極區,具該第一傳導性類型且在該第一摻雜區內; 一源極區,具該第一傳導性類型且在該井區內的一第二側,該第二側係與該第一側相對;以及 一閘電極,在該井區上方且在該源極區與該汲極區之間; 其中該汲極區的一表面以及該源極區的一表面定義出一通道,以及該源極區的該表面直接接觸該井區。
- 如請求項1之半導體結構,其中該汲極區具有一第一汲極區以及一第二汲極區,以及該第一汲極區的深度係與該第二汲極區所具者不同,或其中該源極區具有一第一源極區以及一第二源極區,以及該第一源極區的深度係與該第二源極區所具者不同,或其中該第一汲極區以及該第二汲極區係由不同材料所形成,以及該第一源極區以及該第二源極區係由不同材料所形成。
- 如請求項2之半導體結構,其中該第一汲極區的該深度或該第一源極區的該深度係在自約0.01 μm至約0.022 μm的一範圍中,或該第二汲極區的該深度或該第二源極區的該深度係在自約0.02 μm至約0.054 μm的一範圍中。
- 如請求項1之半導體結構,其進一步包含間隔件,位在該閘電極的二側,其中各間隔件的寬度與該閘電極的寬度的一比係在約1:4至約1:7的一範圍中。
- 如請求項1之半導體結構,其中該汲極區或該源極區以0.3μm的一距離在該閘電極之下延伸。
- 一種高壓金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor,MOSFET),其包含: 一井區; 一輕摻雜區,具一第一傳導性類型且位在該井區內的一第一側; 一汲極區,具該第一傳導性類型且在該輕摻雜區內; 一源極區,具該第一傳導性類型且在該井區內的一第二側,該第二側係與該第一側相對; 一閘電極,在該井區上方且在該源極區與該汲極區之間;以及 間隔件,位在該閘電極的二側,其中各間隔件的寬度與該閘電極的寬度的一比係在自約1:4至約1:7的一範圍中。
- 如請求項6之高壓MOSFET,其中該汲極區具有由不同材料所形成的一第一汲極區以及一第二汲極區,以及該源極區具有由不同材料所形成的一第一汲極區以及一第二汲極區。
- 一種製造一半導體結構之方法,其包含: 形成一井區; 植入一輕摻雜區在該井區的一第一側中; 以一第一深度植入一第一汲極區在該輕摻雜區中; 以一第二深度植入一第二汲極區在該輕摻雜區中,其中該第二深度大於該第一深度; 植入一源極區在該井區內的一第二側中,該第二側係與該第一側相對;以及 形成一閘電極在該井區上方。
- 如請求項8之製造一半導體結構之方法,其中植入該源極區進一步包含: 以該第一深度植入一第一源極區在該井區中;以及 以該第二深度植入一第二源極區在該輕摻雜區中, 其中該第一深度係在自約0.01 μm至約0.022 μm的一範圍中;以及 該第二深度係在自約0.02 μm至約0.054 μm的一範圍中。
- 如請求項9之製造一半導體結構之方法,其中該第一源極區以及該第一汲極區係使用在自10KeV至約30KeV的一範圍中的一能量植入,或其中該第二源極區以及該第二汲極區係使用在自約20KeV至約40KeV的一範圍中的一能量植入,或其中該製造該半導體結構之方法進一步包含在植入該第一源極區、該第一汲極區、該第二源極區以及該第二汲極區之後,施加約10秒的一退火操作至該半導體結構,或其中該製造該半導體結構之方法更包括在該植入該第一汲極區之前,形成間隔件在該閘電極的二側,其中各間隔件的寬度與該閘電極的寬度的一比係在自約1:4至約1:7的一範圍中。
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