TW201701425A - 兩種材料的高介電熱封裝物系統 - Google Patents

兩種材料的高介電熱封裝物系統 Download PDF

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TW201701425A
TW201701425A TW105112019A TW105112019A TW201701425A TW 201701425 A TW201701425 A TW 201701425A TW 105112019 A TW105112019 A TW 105112019A TW 105112019 A TW105112019 A TW 105112019A TW 201701425 A TW201701425 A TW 201701425A
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die
package
electronic
electronic package
primer
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TW105112019A
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TWI694560B (zh
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范瑪席 麥克馬漢
西瓦庫瑪 納加拉珍
格拉耶里 伊拉 波洛格
安里塔 麥可
朱光翰
王力未
尼夏 阿南塔克里希南
科瑞格Ｊ 溫曼
安蘭 艾登
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英特爾公司
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Abstract

一些實施例係關於一種電子封裝。該電子封裝包括一第一晶粒及堆疊至該第一晶粒上之一第二晶粒。一第一封裝物定位於該第一晶粒與該第二晶粒之間。該第一封裝物包括覆蓋該第一晶粒與該第二晶粒之間的一第一體積之一第一材料。一第二封裝物定位於該第一晶粒與該第二晶粒之間。該第二封裝物包括覆蓋該第一晶粒與該第二晶粒之間的一第二體積之一第二材料。該第一材料具有比該第二材料高之一熱導率，且與該第一材料相比，該第二材料更有效地促進該第一晶粒與該第二晶粒之間的電氣連接。

Description

兩種材料的高介電熱封裝物系統 發明領域
本文中描述的實施例大體上係關於電子封裝及使用兩種材料的高熱導率封裝物系統將一第一晶粒連接至一第二晶粒之方法。
發明背景
使電晶體大小最小化以便符合莫耳定律(Moore's law)持續需要減小一級互連(FLI)間距及凸塊大小。此外，使用高級介電質通常導致在矽中利用低k及極低熱導率材料。
此等因素之組合導致對裝配期間之應力及熱機械應力的更高敏感性。因此，隨著每一項新技術改進，用於減小熱機械應力的解決方案變得顯著地更加重要。
將晶片(CPU、記憶體、圖形等)堆疊在彼此之上導致較短互連線以實現改良的電氣效能(例如，用於不同產品區隔中的較高頻帶及/或較低潛時)。然而，晶片堆疊導致熱阻增大，使得相對於非堆疊晶片，其使得更難自CPU移 除熱。
對習知堆疊電子裝置之分析指示，封裝物層之熱阻為自堆疊封裝傳遞熱的關鍵限制因素。當前封裝架構使用通常包括矽石填充劑之晶片間封裝物材料。
此等典型封裝劑範圍之複合熱導率範圍通常限制包括封裝物調配物之電子裝置自堆疊電子裝置傳遞熱之能力。
依據本發明之一實施例，係特地提出一種電子封裝，其包含：一第一晶粒；一第二晶粒，其堆疊至該第一晶粒上；以及一第一封裝物，其定位於該第一晶粒與該第二晶粒之間，該第一封裝物包括覆蓋於該第一晶粒與該第二晶粒之間的一第一體積之一第一材料；以及一第二封裝物，其定位於該第一晶粒與該第二晶粒之間，該第二封裝物包括覆蓋於該第一晶粒與該第二晶粒之間的一第二體積之一第二材料，其中該第一材料具有比該第二材料高之一熱導率，且與該第一材料相比，該第二材料更有效地促進於該第一晶粒與該第二晶粒之間的電氣連接。
10‧‧‧導熱填充劑
20‧‧‧曲線圖
21‧‧‧窗
30、60、70、1010‧‧‧電子封裝
31、61、71‧‧‧第一晶粒
32、72‧‧‧第二晶粒
33、73‧‧‧第一封裝物
34、74‧‧‧第二封裝物
35‧‧‧下表面
36A、36B、66‧‧‧互連件
37‧‧‧周邊
65‧‧‧上表面
75‧‧‧第三封裝物
800、900‧‧‧方法
1000‧‧‧電子裝置
1002‧‧‧系統匯流排
1012‧‧‧處理器
1014‧‧‧通訊電路
1016‧‧‧顯示裝置
1018‧‧‧揚聲器
1020‧‧‧外部記憶體
1022‧‧‧主記憶體
1024‧‧‧硬碟機
1026‧‧‧抽取式媒體
1030‧‧‧鍵盤及/或控制器
圖1展示一些典型導熱填充劑相對於熔融矽石之熱性質。
圖2展示對於實例堆疊電子封裝可適合於達成足夠熱耗散的窗。
圖3說明實例電子封裝之俯視圖。
圖4說明第一晶粒與第二晶粒即將被壓縮在一起之前的實例電子封裝之側視圖。
圖5展示實例電子封裝之仰視圖，其中第一晶粒被移除以曝露第二晶粒之下表面。
圖6展示另一實例電子封裝之俯視圖，其中第二晶粒被移除以曝露第二晶粒之上表面。
圖7說明另一實例電子封裝之俯視圖。
圖8為說明製造實例電子封裝之實例方法的流程圖。
圖9為說明製造實例電子封裝之另一實例方法的流程圖。
圖10為併有本文中描述的至少一個電子封裝及/或方法的電子裝置之方塊圖。
較佳實施例之詳細說明
以下描述及圖式充分說明特定實施例，以以下描述及圖式充分說明特定實施例，以使得熟習此項技術者能夠實踐該等實施例。其他實施例可併入有結構性、邏輯上、與電氣有關之、程序及其他改變。一些實施例之部分及特徵可包括於其他實施例之部分及特徵中，或由其他實施例之部分及特徵取代。請求項中闡述之實施例涵蓋彼等請求項之所有可用等效者。
如本申請案中所使用的諸如「水平」之定向術語係關相對於平行於晶圓或基體之習知平面或表面的平面來 而定義界定，而不管考慮晶圓或基體之定向如何。術語「垂直」指代垂直於如上文所界定之水平的方向。諸如「在......上」、「側」(如在「側壁」中)、「較高」、「下部」、「在......上方」及「在......下方」之介詞係相對於在晶圓或基體之頂部表面上的習知平面或表面而界定，而不管晶圓或基體之定向如何。
本文中所描述的電子封裝及方法可部分地利用包括大粒徑及高體積分率之填充劑來調配具有較高主體熱(bulk thermal)的複合物。儘管設計專門用於高熱導率的材料在技術上可能係可行的，但較高熱導率將伴隨不利取捨：使用的材料將使得晶粒附接處理困難得多。作為一實例，使填充劑體積分率最大化且使平均粒徑最大化有利於較高熱導率，但此舉增大填充劑滯留風險且可能完全干擾接點形成。
本文中描述的電子封裝及方法可使用兩種封裝物材料以(i)將邏輯晶粒接合至記憶體晶粒(及/或將記憶體接合至記憶體晶粒及/或將邏輯晶粒接合至邏輯晶粒)，且(ii)將來自底部邏輯晶粒之熱耗散至頂部記憶體以在較高功率堆疊封裝中實現較高熱耗散。使用兩種封裝物材料以改良堆疊晶片中之熱耗散可適用於多種不同的電子封裝架構。
本文中描述的電子封裝及方法之基本原理為使用兩種材料(而非一種)來製得晶片間接點且在多種電子封裝架構中實現較大熱耗散。作為一實例，材料1可形成接點 且囊封該等接點，且材料2可將來自底部晶粒之熱耗散至頂部晶粒。
本文中描述的電子封裝及方法中的兩種材料的填充劑系統使接合要求與熱傳導要求分開，以使得可藉由兩種材料的填充劑系統達成每一功能而不犧牲效能。接點形成可能受到任何導熱晶片間封裝物之填充劑裝載的限制。本文中描述的電子封裝及方法可藉由在非接點區域中使用高填充劑裝載(亦即，以促進熱導率)且在接點區域中使用低填充劑裝載(亦即，以促進堆堆疊晶片之間的電氣連接之形成)來擴展較低成本及較低熱導率的填充劑之使用。
高填充劑裝載及較大填充劑大小有利於較高熱導率，但可能引起填充劑滯留且可能會干擾晶片間隙驟降。因此，單一封裝物材料通常不能平衡對高熱導率的需要與接合處理所需的性質。本文中描述的實例電子封裝及方法可滿足對晶片附接及高熱導率的雙重要求。
在一些形式中，本文中描述的電子封裝及方法可擴展至周邊陣列，其中一種材料囊封周邊陣列，而另一較高導熱性材料填充封裝之內部。作為一實例，可在附接處理之前與之後施配兩種不同材料，包括(i)含有導熱填充劑之NCP、CUF、MUF；(ii)至少兩個晶粒，其中該等晶粒中之一者包括穿矽通孔(TSV)；以及(iii)具有局部凸塊區域(例如，小於突起區域之30%)的堆疊之1或多個層，其可不或可不基於第一晶粒(例如，邏輯晶粒)與第二晶粒(例如，記憶體、圖形等)之間的重疊區域而佈線。
因此，填充劑之材料1的材料覆蓋面積可高達重疊區域的45%。此外，填充劑之材料2可為高導熱率封裝物，其包括導熱填充劑以達成所需之熱耗散。
在一些形式中，導熱填充劑擁有的熱導率大於熔融矽石之熱導率。圖1展示一些典型導熱填充劑10相對於熔融矽石的熱性質。
應注意，用於材料1及材料2之導熱填充劑之類型可根據堆疊電子封裝之熱要求進行定製。圖2展示布魯格曼方程式(Bruggeman's equation)之曲線圖20，且提供具有熱導率0.23W/m*K之環氧樹脂的各別填充劑導電性及樹脂導電性的估計複合熱導率。
圖2中的加框區域展示將適合於達成用於實例堆疊電子封裝之15W熱耗散之窗21。由於材料2之調配物不受接點形成約束之束縛，因此高填充劑裝載可用以擴展較低成本及較低導熱率填充劑之使用。
在一些形式中，互連件陣列可由材料1囊封。互連件將耗散熱，且由此不需要較高導熱性材料。應該說，材料1可定義為與如所指出的材料2在以下特性中的一或多個特性上不同的任何晶片間材料：填充劑類型、填充劑粒徑、填充劑粒徑分佈，及填充劑裝載。此外，材料1與材料2可包括類似或相異樹脂結構以便促進每一材料之處理。
圖3說明實例電子封裝30之俯視圖。電子封裝30包括第一晶粒31及堆疊至第一晶粒31上之第二晶粒32。
第一封裝物33定位於第一晶粒31與第二晶粒32 之間。第一封裝物33包括覆蓋第一晶粒31與第二晶粒32之間的第一體積的第一材料。
第二封裝物34定位於第一晶粒31與第二晶粒32之間。第二封裝物34包括覆蓋第一晶粒31與第二晶粒32之間的第二體積之第二材料。第一材料具有比第二材料高之熱導率，且與第一材料相比，第二材料更有效地促進第一晶粒31與第二晶粒31之間的電氣連接。
在圖3中所說明的實例形式中，第二封裝物34圍繞第一封裝物33。涵蓋第二封裝物34不圍繞第一封裝物33或僅部分地圍繞第一封裝物33之其它形式。
儘管圖3中未說明，但第一封裝物33可覆蓋至少一個額外體積(圖3中僅展示一個體積)。第一封裝物33之額外體積之數目將部分地取決於電子封裝30之總體組態(以及其他因素)。此外，第二封裝物34可圍繞(i)第一封裝物33之每一額外體積；部分地圍繞第一封裝物33之每一額外體積的一些(或全部)；及/或不圍繞第一封裝物33之每一額外體積之一些(或全部)。
電子封裝30中的第一填充劑33及第二填充劑34之類型將部分地取決於：(i)將使用電子封裝30的應用；(ii)電子封裝30之總體結構；及/或(iii)在電子封裝30中使用的第一填充劑33與第二填充劑34之相對量。在一些形式中，形成第一填充劑33之第一材料比形成第二填充劑34之第二材料更密集地填充。
形成第一填充劑33之第一材料與形成第二填充 劑34之第二材料可包括相同樹脂。涵蓋第一材料與第二材料包括不同樹脂或第一材料及第二材料中的至少一個(或兩者)包括多種樹脂的其他形式。包括於第一材料及第二材料中之樹脂之類型將部分地取決於：(i)將使用電子封裝30的應用；電子封裝30之總體結構；(iii)第一填充劑33與第二填充劑34之相對量；及/或(iv)形成第一晶粒31及第二晶粒32之材料的類型。
在圖3中所說明的電子封裝之實例形式中，第一晶粒31之大小與第二晶粒32不同。涵蓋第一晶粒31的大小與第二晶粒32相同之其他形式。
包括於電子封裝30中之晶粒之類型將部分地取決於將使用電子封裝30的應用。作為實例，第一晶粒31及/或第二晶粒32可為晶片、邏輯晶粒、記憶體晶粒、基體、積體電路、處理器控制集線器及/或嵌入式裝置，以及其他類型之電子裝置。
圖4說明第一晶粒31與第二晶粒32即將被壓在一起之前的實例電子封裝30之側視圖。圖4展示施加至第一晶粒31及/或第二晶粒32的第一封裝物33及第二封裝物34之量可視第一封裝物33及第二封裝物34之體積的配置方式(一旦第一晶粒31與第二晶粒32堆疊在一起)而不同。待施加至第一晶粒31及/或第二晶粒32的第一封裝物33及第二封裝物34之量將部分地取決於第一封裝物33及第二封裝物34之各別體積中所需要的熱導率及電連接之位置及量。
圖5展示實例電子封裝30之實例仰視圖，其中第 一晶粒31被移除以曝露第二晶粒32之下表面35。第一晶粒31與第二晶粒32經由互連件36A、36B(在移除第一晶粒31的情況下可見)電氣連接。
在本文中描述的電子封裝及方法之一些形式中，第二封裝物34圍繞互連件36A、36B。應注意，涵蓋其中第二封裝物34圍繞互連件36A、36B中的一些(或全不圍繞)的電子封裝30之其他實例形式。
在本文中描述的電子封裝30及方法之實例形式中，互連件36A、36B可以任何方式配置在第一晶粒31及/或第二晶粒32上。互連件36A、36B配置於第一晶粒31及/或第二晶粒32上之方式將部分地取決於：(i)電子封裝30之應用；(ii)包括於電子封裝30中之晶片之類型；及/或(iii)第一晶粒31及第二晶粒32之總體組態(以及其他因素)。
作為一實例，互連件36A可繞第一晶粒31及第二晶粒32中之一者(在圖5中展示第二晶粒32)的周邊37而延伸。在其他實例形式中，互連件36A可繞第一晶粒31及第二晶粒32中之一者的周邊37的至少一部分而延伸。
互連件36B並非繞第一晶粒31及第二晶粒32中之一者的周邊延伸。應注意，電子封裝30可包括不同類型之互連件。作為一實例，互連件36A大於互連件36B。此外，互連件36A或36B可以交錯組態配置以便節省第一晶粒31及/或第二晶粒32上之寶貴空間。
圖6展示另一實例電子封裝60之俯視圖，其中第二晶粒被移除以曝露第一晶粒61之上表面65。第一晶粒61 及第二晶粒經由互連件66(在移除第二晶粒的情況下可見)電氣連接。
在電子封裝60之一些形式中，第二封裝物34圍繞互連件66(圖6中展示四個互連件66)。應注意，涵蓋其中第二封裝物34圍繞互連件66中之一些(或全不圍繞)的電子封裝60之其他實例形式。在圖6中展示之實例電子封裝60中，第一封裝物33之四個區域在第二封裝物34之兩側上。
圖7說明另一實例電子封裝70之俯視圖。電子封裝70包括第一晶粒71及堆疊至第一晶粒71上之第二晶粒72。在圖7中所說明的實例形式中，第一晶粒71的大小與第二晶粒72相同，但第一晶粒71與第二晶粒72可具有不同大小。
第一封裝物73定位於第一晶粒71與第二晶粒72之間。第一封裝物73包括覆蓋第一晶粒71與第二晶粒72之間的多個第一體積的第一材料。
第二封裝物74定位於第一晶粒71與第二晶粒72之間。第二封裝物74包括覆蓋第一晶粒71與第二晶粒72之間的第二體積之第二材料。第一材料具有比第二材料高之熱導率，且與第一材料相比，第二材料更有效地促進第一晶粒71與第二晶粒72之間的電氣連接。
儘管圖7中未說明，但第二封裝物74可覆蓋至少一個額外體積(圖7中僅展示一個體積)。第一封裝物73之體積的數目將部分地取決於電子封裝70之總體組態(以及其他因素)。
如圖7中所示，電子封裝可進一步包括定位於第一晶粒71與第二晶粒72之間的第三封裝物75。第三封裝物75可包括覆蓋第一晶粒71與第二晶粒72之間的至少一個第三體積(圖7中展示第三封裝物75之兩個體積)的第三材料。 第三材料具有的熱導率可與第一材料及第二材料不同，及/或第三材料可以與第一材料及第二材料不同之方式促進第一晶粒與第二晶粒之間的電氣連接。
形成第一填充劑73之第一材料、形成第二填充劑74之第二材料及形成第三填充劑75之第三材料可全部包括相同樹脂。涵蓋其中第一材料、第二材料及第三材料包括不同樹脂或第一、第二及第三材料中的至少一種(一些或全部)包括多種樹脂的其他形式。
圖8為說明製造電子封裝30(見圖3)之實例方法[800]的流程圖。方法[800]包括[810]將由第一材料製成之第一封裝物33安置在第一晶粒31上及[820]將由第二材料製成之第二封裝物34安置在第一晶粒31上。在一些形式中，[820]將第二封裝物34安置在第一晶粒31上包括用第二封裝物34圍繞(有時僅部分地)第一封裝物33。
第一材料具有比該第二材料高之一熱導率。此外，與第一材料相比，第二材料更有效地促進第一晶粒31與第二晶粒32之間的電氣連接。
方法[800]進一步包含[830]將第二晶粒32堆疊至第一晶粒31上，使得第一封裝物33及第二封裝物34處於第一晶粒31與第二晶粒32之間。可使用現在已知或未來發現 的任何技術將第二晶粒32堆疊至第一晶粒31上。
在方法[800]之一些形式中，[820]將第二封裝物34安置在第一晶粒31上包括用第二封裝物34圍繞將第一晶粒31電氣連接至第二晶粒32之互連件36A、36B。藉由第二封裝物34圍繞互連件36A、36B之方式將部分地取決於與製造電子封裝30相關聯之成本、製造考慮因素及功能性(以及其他因素)。
此外，[820]將第二封裝物34安置在第一晶粒31上可包括繞第一晶粒31及第二晶粒32中之一者的周邊37的至少一部分安置第二封裝物34。
圖9為說明製造電子封裝30之另一實例方法[900]的流程圖。方法[900]包括[910]將由第二材料製成之第二封裝物34安置在第一晶粒31上及[920]將第二晶粒32堆疊至第一晶粒31上，使得第二封裝物34處於第一晶粒31與第二晶粒32之間。可使用現在已知或未來發現的任何技術將第二晶粒32堆疊至第一晶粒31上。
方法[900]進一步包含[930]將由第一材料製成之第一底膠33插入於第一晶粒與第二晶粒之間。該第一材料具有比該第二材料高之熱導率，且較之於該第一材料，該第二材料更有效地促進第一晶粒31與第二晶粒32之間的電氣連接。
在方法[900]之一些形式中，[930]將第一底膠插入於第一晶粒31與第二晶粒32之間可包括：(i)用第一底膠33圍繞(有時僅部分地)第二底膠34；(ii)用第一底膠33圍繞 將第一晶粒31電氣連接至第二晶粒32之互連件36A、36B；及/或(iii)繞第一晶粒31及第二晶粒32中之一者的周邊37的至少一部分安置第一底膠34。
第一底膠33圍繞第二底膠34以及藉由第二底膠34圍繞互連件36A、36B之方式將部分地取決於與製造電子封裝30相關聯的成本、製造考慮因素及功能性(以及其他因素)。包括於方法[800]、[900]中之第一晶粒31及第二晶粒32之類型、大小及組態將部分地取決於電子封裝30之總體所需組態及功能。
本文中描述的電子封裝及方法可使得能夠與較高導熱性材料組合地使用較低熱導率填充劑。兩種不同填充劑之使用可解決與堆疊晶粒之附接過程相關的需要以及本文中描述的電子封裝之熱管理要求。
為了更好地說明本文中揭示之方法及電子封裝，本文中提供實施例之非限制性清單。
實例1包括一種電子封裝。該電子封裝：一基體；附接至該基體之一晶粒；以及一封裝物，其歸因於毛細作用而定位於該晶粒與該基體之間；以及圍繞該晶粒之一支撐件。
實例2包括實例1之電子封裝，其中該晶粒覆晶接合至該基體。
實例3包括實例1至2中的任一者之電子封裝，其中該封裝物將該支撐件緊固至該基體。
實例4包括實例1至3中的任一者之電子封裝，其 中該封裝物將該支撐件緊固至該晶粒。
實例5包括實例1至4中任一者之電子封裝，其中該支撐件具有大體上均一的橫截面。
實例6包括實例1至5中的任一者之電子封裝，其中該支撐件具有一內部底部邊緣及一外部底部邊緣，該內部底部邊緣經斜切以在繞該晶粒安裝該支撐件時收納封裝物。
實例7包括實例6之電子封裝，其中該支撐件具有一內部上邊緣及一內部外部上邊緣，該內部上邊緣包括一通道以在繞該晶粒安裝該支撐件時收納在該晶粒與該支撐件之間向上流動的過剩封裝物。
實例8包括實例1至7中的任一者的電子封裝，其中該支撐件之該橫截面改變，使得該橫截面在該晶粒上應力相對較高之區域中較大且在該晶粒上應力相對較低之區域中較小。
實例9包括實例8之電子封裝，其中該支撐件具有一內部下邊緣及一外部下邊緣，該支撐件包括一通路及一外表面，該通道自該支撐件之該內部下邊緣延伸至該支撐件之該外表面，使得在繞該晶粒安裝該支撐件時，該封裝物經由該通路自該外表面流動至該內部下邊緣。
實例10包括實例9之電子封裝，其中該通路在該支撐件之一側上自該支撐件之該外表面延伸。
實例11包括一種方法，其包括：將一晶粒附接至一基體；使用毛細作用將一封裝物插入於該晶粒與該基體 之間；以及繞該晶粒安置一支撐件，使得該支撐件圍繞該晶粒。
實例12包括實例11中的任一者之方法，其中將該晶粒附接至該基體包括使用覆晶接合將該晶粒附接至該基體。
實例13包括實例11至12中的任一者之方法，其中繞該晶粒安置一支撐件使得該支撐件圍繞該晶粒包括使用該封裝物將該支撐件附接至該晶粒。
實例14包括實例11至13中的任一者之方法，其中繞該晶粒安置一支撐件使得該支撐件圍繞該晶粒包括使用該封裝物將該支撐件附接至該基體。
實例15包括實例11至14中的任一者之方法，且進一步包括固化該封裝物。
實例16包括實例11至15中的任一者之方法，且進一步包括經由該支撐件中之開放區域移除封裝物。
實例17包括實例11至16中的任一者之方法，其中使用毛細作用將一底膠插入於該晶粒與該基體之間包括將該底膠經由該支撐件中之一通路自該支撐件之一外表面插入至該支撐件之一下部內邊緣。
實例18包括一種電子封裝。該電子封裝包括：一晶粒；模製至該晶粒之一支撐件，其中該支撐件圍繞該晶粒；一基體；以及一底膠，其歸因於該支撐件及該晶粒與該基體之間的該底膠之毛細作用而將該晶粒及該支撐件附接至該基體。
實例19包括實例18之電子封裝，其中該晶粒覆晶接合至該基體。
實例20包括實例18至19中的任一者之電子封裝，其中該基體包括多個重佈層，且該底膠將該晶粒及該支撐件附接至形成該基體的該等重佈層中的至少一個。
在【實施方式】中將部分地闡述本發明之電子裝置、焊料組合物以及相關方法之此等以及其他實例及特徵。此概述意欲提供本發明標的物之非限制性實例，其並不意欲提供排他性或窮盡性解釋。包括【實施方式】以提供關於系統以及方法之其他資訊。
包括使用在本發明中描述的電子封裝方法的電子裝置之實例以展示本發明的較高階裝置應用之實例。圖10為併有本文中描述的至少一個電子封裝及/或方法的電子裝置1000之方塊圖。電子裝置1000僅為可使用本發明之實施例的電子系統之一個實例。
電子裝置1000之實例包括(但不限於)個人電腦、平板電腦、行動電話、遊戲裝置、MP3或其他數位音樂播放器等。在此實例中，電子裝置1000包含包括系統匯流排1002以耦接該系統之各組件的資料處理系統。系統匯流排1002提供電子裝置800之各組件之間的通訊鏈路，且可實施為單一匯流排、實施為匯流排之組合或以任一其他合適方式來實施。
電子封裝1010耦接至系統匯流排1002。電子封裝1010可包括任何電路或電路之組合。在一個實施例中，電 子封裝1010包括可屬於任一類型之處理器1012。如本文中所使用，「處理器」意謂任一類型之計算電路，諸如(但不限於)，微處理器、微控制器、複雜指令集計算(CISC)微處理器、精簡指令集計算(RISC)微處理器、超長指令字(VLIW)微處理器、圖形處理器、數位信號處理器(DSP)、多核處理器或任一其他類型之處理器或處理電路。
可包括於電子封裝1010中的其他類型之電路為自訂電路、特殊應用積體電路(ASIC)或類似者，諸如供用於如行動電話、平板電腦、膝上型電腦、雙向無線電及類似電子系統之無線裝置中的一或多個電路(例如通訊電路1014)。IC可執行任一其他類型之功能。
電子裝置1000亦可包括一外部記憶體820，該外部記憶體又可包括適合於特定應用之一或多個記憶體元件，諸如，呈隨機存取記憶體(RAM)之形式的主記憶體1022、一或多個硬碟機1024及/或處置抽取式媒體1026之一或多個碟機(諸如，光碟(CD)、快閃記憶體卡、數位視訊碟(DVD)及類似者)。
電子裝置1000亦可包括一顯示裝置1016、一或多個揚聲器1018及一鍵盤及/或控制器1030，鍵盤及/或控制器可包括滑鼠、軌跡球、觸控式螢幕、語音辨識裝置或准許系統使用者將資訊輸入至電子裝置1000中及自電子裝置1000接收資訊的任何其他裝置。
此概述意欲提供本發明標的物之非限制性實例，其並不意欲提供排他性或窮盡性解釋。包括【實施方 式】以提供關於方法之另外資訊。
以上【實施方式】包括對附圖之參考，該等附圖形成該【實施方式】之一部分。圖式藉由說明展示本發明可實踐之特定實施例。此等實施例在本文中亦稱作「實例」。此等實例可包括除所展示或描述之彼等元件之外的元件。然而，本發明者亦涵蓋僅提供所展示或描述之彼等元件的實例。此外，本發明者人亦預期使用所展示或描述之彼等元件之任何組合或排列的實例(或其一或多個態樣)，其係關於特定實例(或其一或多個態樣)，抑或關於本文中所展示或描述之其他實例(或其一或多個態樣)而展示或描述之彼等元件的任何組合或排列的實例(或其一或多個態樣)。
在此文件中，如專利文件中常見之術語「一(a/an)」用於包括一個或一個以上，與「至少一個(at least one)」或「一或多個(one or more)」之任何其他例項或用法無關。在此文件中，術語「或」用以指代非排他性或，使得「A或B」包括「A而非B」、「B而非A」及「A及B」，除非另有指示。在此文件中，術語「包括」及「其中(in which)」用作各別術語「包含」及「其中(wherein)」之通俗易懂的等效者。又，在以下申請專利範圍中，術語「包括」及「包含」為開放式，亦即，包括除了在請求項中列舉於此術語之後的元素以外之元素的系統、裝置、物品、組合物、調配物或製程仍被認為在彼請求項之範疇內。此外，在以下申請專利範圍中，術語「第一」、「第二」及「第三」等僅用作標記，且並不意欲對其對象施加數值要求。
以上描述意欲為說明性的而非限制性的。舉例而言，上述實例(或其一或多個態樣)可與彼此組合使用。諸如，一般熟習此項技術者在審閱以上描述後可使用其他實施例。
提供發明摘要以符合37 C.F.R.§1.72(b)，從而允許讀者快速地確定技術揭示內容之本質。遵從以下理解：其不用於限制或解釋申請專利範圍之範疇或意義。
又，在以上【實施方式】中，可將各種特徵分組在一起以簡化本發明。此不應解釋為期望未主張之揭示特徵對任何請求項而言均為必需的。相反地，本發明之標的物可在於比特定所揭示實例的所有特徵少的特徵。因此，特此將以下申請專利範圍併入【實施方式】中，其中每一請求項作為獨立實施例而獨立存在，且預期此等實施例可以各種組合或排列彼此組合。應參考所附申請專利範圍連同此申請專利範圍所具有的等效物之全部範疇來判定本發明之範疇。
30‧‧‧電子封裝
31‧‧‧第一晶粒
32‧‧‧第二晶粒
33‧‧‧第一封裝物
34‧‧‧第二封裝物

Claims (20)

  1. 一種電子封裝，其包含：一第一晶粒；一第二晶粒，其堆疊至該第一晶粒上；以及一第一封裝物，其定位於該第一晶粒與該第二晶粒之間，該第一封裝物包括覆蓋於該第一晶粒與該第二晶粒之間的一第一體積之一第一材料；以及一第二封裝物，其定位於該第一晶粒與該第二晶粒之間，該第二封裝物包括覆蓋於該第一晶粒與該第二晶粒之間的一第二體積之一第二材料，其中該第一材料具有比該第二材料高之一熱導率，且與該第一材料相比，該第二材料更有效地促進於該第一晶粒與該第二晶粒之間的電氣連接。
  2. 如請求項1之電子封裝，其中該第二封裝物圍繞該第一封裝物。
  3. 如請求項1之電子封裝，其中該第一晶粒及該第二晶粒經由互連件而被電氣連接。
  4. 如請求項3之電子封裝，其中該第二封裝物圍繞該等互連件。
  5. 如請求項3之電子封裝，其中該等互連件繞該第一晶粒及該第二晶粒中之一者的周邊的至少一部分延伸。
  6. 如請求項1之電子封裝，其中該第一材料中之第一填充劑比該第二材料中之第二填充劑更密集地填充。
  7. 如請求項6之電子封裝，其中該第一材料及該第二材料包括相同的樹脂。
  8. 如請求項1之電子封裝，其中該第一封裝物覆蓋至少一個額外體積。
  9. 如請求項8之電子封裝，其中該第二封裝物圍繞該第一封裝物之每一體積。
  10. 如請求項1之電子封裝，其中該第一晶粒之大小與該第二晶粒不同。
  11. 如請求項1之電子封裝，其進一步包含定位於該第一晶粒與該第二晶粒之間的第三封裝物，該第三封裝物包括覆蓋於該第一晶粒與該第二晶粒之間的一第三體積之一第三材料，其中該第三材料具有之熱導率與該第一材料及該第二材料不同，且該第三材料以與該第一材料及該第二材料不同之方式促進於該第一晶粒與該第二晶粒之間的電氣連接。
  12. 如請求項11之電子封裝，其中該第三材料包括與該第一材料及該第二材料中的至少一者相同的樹脂。
  13. 一種方法，其包含：將由第一材料所製成之一第一封裝物安置在一第一晶粒上；將由第二材料所製成之一第二封裝物安置在該第一晶粒上，其中該第一材料具有比該第二材料高之熱導率，且該第二材料比該第一材料更有效地促進於該第一晶粒與該第二晶粒之間的電氣連接；以及 將一第二晶粒堆疊至該第一晶粒上，使得該第一封裝物及該第二封裝物是在該第一晶粒與該第二晶粒之間。
  14. 如請求項13之方法，其中將一第二封裝物安置在該第一晶粒上包括以該第二封裝物圍繞該第一封裝物。
  15. 如請求項13之方法，其中將一第二封裝物安置在該第一晶粒上包括以該第二封裝物圍繞將該第一晶粒電氣連接至該第二晶粒之互連件。
  16. 如請求項13之方法，其中將一第二封裝物安置在該第一晶粒上包括繞該第一晶粒及該第二晶粒中之一者的周邊的至少一部分安置該第二封裝物。
  17. 一種方法，其包含：將由一第二材料所製成之一第二底膠安置在一第一晶粒上；將一第二晶粒堆疊至該第一晶粒上，使得該第二底膠是在該第一晶粒與該第二晶粒之間；以及將由第一材料所製成之一第一底膠插入於該第一晶粒與該第二晶粒之間，其中該第一材料具有比該第二材料高之一熱導率，且該第二材料比該第一材料更有效地促進於該第一晶粒與該第二晶粒之間的電氣連接。
  18. 如請求項17之方法，其中將一第一底膠插入於該第一晶粒與該第二晶粒之間包括以該第一底膠圍繞該第二底膠。
  19. 如請求項17之方法，其中將一第一底膠插入於該第一晶 粒與該第二晶粒之間包括以該第一底膠圍繞將該第一晶粒電氣連接至該第二晶粒之互連件。
  20. 如請求項17之方法，其中將一第一底膠插入於該第一晶粒與該第二晶粒之間包括繞該第一晶粒及該第二晶粒中之一者的周邊的至少一部分安置該第一底膠。
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KR20180016989A (ko) 2018-02-20
EP3311408B1 (en) 2021-05-19
EP3311408A1 (en) 2018-04-25
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TWI694560B (zh) 2020-05-21
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JP2018518824A (ja) 2018-07-12
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