TW201643969A - 封裝模組及其製作方法 - Google Patents

封裝模組及其製作方法 Download PDF

Info

Publication number
TW201643969A
TW201643969A TW104126650A TW104126650A TW201643969A TW 201643969 A TW201643969 A TW 201643969A TW 104126650 A TW104126650 A TW 104126650A TW 104126650 A TW104126650 A TW 104126650A TW 201643969 A TW201643969 A TW 201643969A
Authority
TW
Taiwan
Prior art keywords
package module
circuit substrate
pins
bent portion
manufacturing
Prior art date
Application number
TW104126650A
Other languages
English (en)
Inventor
Kai Lu
zhen-qing Zhao
Tao Wang
Original Assignee
Delta Electronics Shanghai Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Electronics Shanghai Co filed Critical Delta Electronics Shanghai Co
Publication of TW201643969A publication Critical patent/TW201643969A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一種封裝模組的製作方法，包含放置具有複數個引腳之一引腳架於一電路基板上，接合引腳與電路基板上所對應的接合區，使引腳連接於接合區，切除引腳架之一連接部，以及彎折引腳，使引腳垂直於電路基板。透過引腳架將引腳設置在電路基板對應之接合區上，而後再切除連接部並折彎引腳，可以大幅提升封裝模組的組裝效率。

Description

封裝模組及其製作方法
本發明是關於一種封裝模組及其製作方法，且特別是關於一種外殼封裝的封裝模組及其製作方法。
高效率、高密度以及高可靠性一直是現今電子裝置的發展趨勢，以達到節能、降低成本、以及良好的使用壽命的目的。舉例而言，集成功率模組（ In t eg r a t ed Powe r Mod ul e ,IPM），將多個半導體器件集成在一個器件封裝裏，爲提升封裝內的空間利用率提供了可能。
功率模塊的封裝形式種類繁多，如金屬封裝(Metal Packaging)、陶瓷封裝(Ceramic Packaging)、塑膠封裝(Plastic Packaging)等，其中塑膠封裝具有較高的性價比，因此在民用以及工業應用的領域被大規模使用。
塑膠封裝亦可再細分為塑封料（molding compound）封裝與外殼（housing）封裝兩大類。塑封料封裝是將塑封料包覆於元件以及基板以起到絕緣保護、環境保護、機械保護的功能。由於塑封料和其餘材料之間熱膨脹係數（CTE）不一致，故引起的熱應力也會相應增加。所以，通常此類封裝形式不易將尺寸做的非常大，從而在大功率領域應用被限制。
外殼封裝則是採用獨立的外殼實現元件的機械保護、電氣絕緣等，然而，此種類型的封裝組裝較為費時費力，亦不利於大規模生產。
因此， 本發明便提出了一種封裝模組的製造方法， 可以用以提升外殼封裝類型之封裝模組的組裝效率。
本發明之一實施方式提供了一種封裝模組的製作方法，包含放置具有複數個引腳之一引腳架於一電路基板上；接合引腳與電路基板上所對應的接合區，使引腳連接於接合區；切除引腳架之一連接部；以及彎折引腳，使引腳垂直於電路基板。
於一或多個實施例中，封裝模組的製作方法更包含組裝一外殼於電路基板，其中外殼具有複數個穿孔，以供彎折的引腳穿過而外露於外殼。
於一或多個實施例中，封裝模組的製作方法更包含填充一保護膠於外殼內，使保護膠覆蓋電路基板。
於一或多個實施例中，封裝模組的製作方法更包含設置一焊料於電路基板之接合區上；以及加熱焊料。
於一或多個實施例中，封裝模組的製作方法更包含設置複數個電子元件於電路基板；以及打線接合部分的電子元件之接點至部分的接合區。
於一或多個實施例中，封裝模組的製作方法更包含將引腳之彎折部進行變截面處理。變截面積處理包含將引腳之彎折部於厚度方向或寬度方向進行開槽、通孔或縮減。
本發明之另一實施方式提供了由上述方法所製作的封裝模組。
本發明之又一實施方式提供了一種封裝模組，包含一電路基板、一外殼以及複數個引腳。電路基板具有複數個接合區。外殼組裝於電路基板，外殼具有複數個穿孔。引腳連接於接合區，其中每一引腳包含焊接部、引腳本體、以及彎折部。焊接部連接於接合區之一。引腳本體垂直於電路基板，且穿過穿孔之一。彎折部連接焊接部與引腳本體，其中至少部份的彎折部具有變化的截面積。
於一或多個實施例中，彎折部在沿厚度方向相較於焊接部具有縮減的厚度。
於一或多個實施例中，彎折部在沿寬度方向相較於焊接部具有縮減的寬度。
於一或多個實施例中，彎折部具有至少一凹陷部，凹陷部位於彎折部的內側或是外側，且凹陷部為三角形、矩形、弧形、鋸齒狀或不規則形狀凹槽。
本發明之外殼封裝類型的封裝模組與其製作方法，透過引腳架將引腳設置在電路基板對應之接合區上，而後再切除連接部與折彎引腳的設計，可以大幅縮短設置引腳所需要的時間以及人力，有效提升了封裝模組的組裝效率。
以下將以圖式及詳細說明清楚說明本發明之精神，任何所屬技術領域中具有通常知識者在瞭解本發明之較佳實施例後， 當可由本發明所教示之技術， 加以改變及修飾， 其並不脫離本發明之精神與範圍。
參照第1A圖至第1F圖，其分別為本發明之封裝模組的製作方法一實施例不同階段的示意圖。第1A圖為提供電路基板110，電路基板110具有多個接合區112。接合區112可以包含絕緣部分和電性連接部分，每個接合區112可具有多個不同的電性連接部分，彼此之間可以連接或不連接，本發明並不以此為限。電路基板110可以為單層或多層的印刷電路板、敷銅陶瓷基板或是導線架等，本發明並不以此為限。本實施例中是以印刷電路板進行說明。
第1A圖中更包含將焊料114，如錫膏，設置在電路基板110之接合區112上，例如電性連接部分。焊料114可以透過如印刷的方式塗布在電路基板110上之接合區112，但本發明並不以此為限。
接著，於第1B圖中，將引腳架120放置在電路基板110上。引腳架120包含有多個引腳130、外框架140以及連接引腳130與外框架140之連接部150。引腳130的位置為對應於至少部份的接合區112。換言之，引腳130之一端與電路基板110之接合區112接觸，並且焊料114可以位於接合區112與引腳130之間，但本發明並不以此為限。引腳130之另一端則是透過連接部150與外框架140連接。
如此一來，當要將引腳130放置在電路基板110上時，由於引腳130已經透過連接部150一體固定於外框架140上，因此，只需要一次作業即可將所有的引腳130放置到對應的接合區112上。相較於傳統需要一個一個放置引腳130的工序，本發明之一實施例可以一次將所有的引腳130放置到電路基板110上的預定位置，大幅縮短了組裝引腳130所需要的時間。
第1B圖中更包含將電子元件160，例如半導體晶片，放置在電路基板110上，其中電子元件160的位置可與部份的接合區112重疊，以讓焊料114連接接合區112與電子元件160，但本發明並不以此為限。引腳130可以圍繞設置在電路基板110的邊緣。
電路基板110與其上之電子元件160及引腳架120可以送入加熱裝置，例如回焊爐中，以加熱焊料114，讓焊料114接合引腳130與對應之接合區112，以及接合電子元件160與對應之接合區112等。如此一來，電子元件160以及引腳130便透過焊料114固定於電路基板110上。
接著參照第1C圖，電子元件160上具有多個接點162，部份之電子元件160之接點162可以透過焊線116連接至電路基板110之接合區112，或是連接至另一電子元件160的接點162等。如此一來，便可以讓電子元件160透過電路基板110以及引腳130與外部溝通，但本發明並不以此為限。
接著，切除引腳架120之連接部150，讓引腳架120之外框架140以及連接部150與引腳130分離，讓引腳130繼續保留在電路基板110上，如第1D圖所示。
接著，如第1E圖所示，將引腳130彎折，使得引腳130的一端垂直於電路基板110。為了便於彎折引腳130，可將引腳130的結構進行變截面處理，此部份將於後續的實施例中進行說明。
而後，第1F圖為將外殼170組裝於電路基板110上，其中外殼170可以為塑膠外殼，但本發明並不以此為限。外殼170可以透過如射出成型的方式製作而成。外殼170上具有多個穿孔172，穿孔172的位置為對應於引腳130，以供引腳130穿過而外露於外殼170。
第1F圖中更包含填充保護膠180於外殼170之中，使得保護膠180覆蓋於電路基板110、電子元件160、以及部份的引腳130。保護膠180可由外殼170上之灌注口174填入外殼170內，但本發明並不以此為限。保護膠180除了用以保護電子元件160與其上之焊線116，亦可以用以電性隔離相鄰的引腳130。保護膠180材料舉例而言，可以為具有流動性的膠體，如矽膠。
將外殼170組裝於電路基板110上之步驟更包含有在外殼170與電路基板110之間的縫隙處塗上密封膠182，以藉由密封膠182連接外殼170與電路基板110，並且隔離外界的水氣。
綜上所述，本發明之封裝模組的製作方法之一實施例可以利用引腳架將所有的引腳設置在電路基板之對應的接合區上，待引腳透過焊料固定於接合區上之後，再將引腳架的連接部切除，並彎折引腳。相較於傳統需要一個一個組裝引腳的方式，本方法則可以大幅提升封裝模組的組裝效率。
參照第2A圖與第2B圖，其分別為應用於本發明之封裝模組的引腳一實施例的正視圖與側視圖。引腳130包含有焊接部132、引腳本體134以及彎折部136。焊接部132可以 為平行於電路基板110，且透過焊料114焊接於電路基板110上之接合區。引腳本體134則是垂直於電路基板110，用以穿過如第1F圖中之外殼170的穿孔172，彎折部136則是連接引腳本體134以及焊接部132。
如前所述，為了讓引腳130更容易被折彎，引腳130的彎折部136可進行變截面處理，以讓部份的彎折部136便於彎折。舉例而言，此變截面處理包含，但不限於，將引腳130的彎折部136於其厚度方向D1或是寬度方向D2進行開槽、通孔或是縮減等，以減少局部之彎折部136的寬度或是厚度(例如相較於焊接部132)等，讓引腳130可以較為輕易地被彎折。
接著參照第2A圖至第2C圖，其中第2C圖為第2B圖中之引腳130的局部放大圖。更具體地說，引腳本體134可以垂直於電路基板110，焊接部132可以平行於電路基板110。彎折部136可以為平面A-A與平面B-B之間彎折的部分，但本發明並不以此為限。
前述之將彎折部136進行變截面處理的設計，包含讓至少部份的彎折部136具有變化的截面積，例如，彎折部136內存在有截面積小於例如在平面A-A或是平面B-B位置處之截面積的區域。彎折部136之變截面的設計可在製作引腳架110(見第1圖)時一併完成，舉例而言，可以利用蝕刻或是機械加工等方式，將彎折部136沿其厚度方向D1或是寬度方向D2進行開槽、通孔或是縮減等，以減少局部之彎折部136的截面積，但本發明並不以此為限，彎折部136包含變化的截面積即可。
接著，請參照第3A圖至第5B圖，其分別繪示本發明之封裝模組中引腳的彎折部於折彎前後之多個實施例的局部側視圖。第3A圖、第4A圖與第5A圖為彎折部136被折彎前的側視圖，而第3B圖、第4B圖與第5B圖則是彎折部136被折彎之後的側視圖。具體而言，第3A圖至第5B圖中之彎折部136的截面積為沿著厚度方向D1變化，彎折部136上可以具有至少一個凹陷部138，凹陷部138可以位於彎折部136的內側或是外側，凹陷部138的深度較佳為不超過彎折部136之厚度的一半，以維持足夠的機械強度，但本發明並不以此為限。
凹陷部138的形狀可以為如第3A圖所示之三角形，如第4A圖所示之矩形，如第5A圖所示之鋸齒狀，或者在其他的實施例變化中，凹陷部138的形狀可以為弧形或是其他的規則或不規則形狀之凹槽。藉由凹陷部138的設置，可以減少彎折部136於折彎時的應力，讓彎折部136更容易被彎折。
請參照第6A圖至第7B圖，其分別繪示本發明之封裝模組中引腳的彎折部於折彎前後之多個實施例的局部正視圖。第6A圖與第7A圖為彎折部136被折彎前的正視圖，而第6B圖與第7B圖則是彎折部136被折彎之後的正視圖。具體而言，第6A圖至第7B圖中之彎折部136的截面積為沿著寬度方向D2變化，彎折部136上可以具有至少一個凹陷部138，凹陷部138可以位於彎折部136的左右兩側，凹陷部138的寬度總和較佳為不超過彎折部136之寬度的一半，以維持足夠的機械強度，但本發明並不以此為限。
凹陷部138的形狀可以為如第6A圖所示之矩形，如第7A圖所示之弧狀，或者在其他的實施例變化中，凹陷部138的形狀可以為三角形、鋸齒狀或是其他的規則或不規則形狀。
在部份的實施例中，彎折部136的截面積變化可不限於沿厚度方向D1或是沿寬度方向D2作變化，而是可以同時沿厚度方向D1與寬度方向D2變化等，本技術領域人員更可以按照不同的設計需求變更彎折部136中之凹陷部138的位置、數量與形狀，不應以前述實施例為限，變截面設計亦可以通過設置通孔、縮減等方式實現，本發明並不以此為限。
雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110‧‧‧電路基板 112‧‧‧接合區 114‧‧‧焊料 116‧‧‧焊線 120‧‧‧引腳架 130‧‧‧引腳 132‧‧‧焊接部 134‧‧‧引腳本體 136‧‧‧彎折部 138‧‧‧凹陷部 140‧‧‧外框架 150‧‧‧連接部 160‧‧‧電子元件 162‧‧‧接點 170‧‧‧外殼 172‧‧‧穿孔 174‧‧‧灌注口 180‧‧‧保護膠 182‧‧‧密封膠 D1、D2‧‧‧方向 A-A、B-B‧‧‧平面
為讓本發明之目的、特徵、優點與實施例能更 明顯易懂， 所附圖式之詳細說明如下： 第1A 圖至第1 F 圖分別為本發明之封裝模組的製作方法 一實施例不同階段的示意圖。 第2A 圖與第2B 圖分別為應用於本發明之封裝模組的引 腳一實施例的正視圖與側視圖。 第2C圖為第2B圖中之引腳的局部放大圖。 第3A圖至第5B圖， 其分別繪示本發明之封裝模組中引腳 的彎折部於折彎前後之多個實施例的局部側視圖。 第6A圖至第7B圖， 其分別繪示本發明之封裝模組中引腳 的彎折部於折彎前後之多個實施例的局部正視圖。
110‧‧‧電路基板
112‧‧‧接合區
116‧‧‧導線
120‧‧‧引腳架
130‧‧‧引腳
140‧‧‧外框架
150‧‧‧連接部
160‧‧‧電子元件
162‧‧‧接點

Claims (13)

  1. 一種封裝模組的製作方法，包含： 放置具有複數個引腳之一引腳架於一電路基板上； 接合該些引腳與該電路基板上所對應的複數個接合區，使該些引腳連接於該些接合區； 切除該引腳架之一連接部；以及 彎折該些引腳，使該些引腳垂直於該電路基板。
  2. 如請求項1所述之封裝模組的製作方法，更包含： 組裝一外殼於該電路基板，其中該外殼具有複數個穿孔，以供該些彎折的引腳穿過而外露於該外殼。
  3. 如請求項2所述之封裝模組的製作方法，更包含： 填充一保護膠於該外殼內，使該保護膠覆蓋該電路基板。
  4. 如請求項1所述之封裝模組的製作方法，更包含： 設置一焊料於該電路基板之該些接合區上；以及 加熱該焊料。
  5. 如請求項1所述之封裝模組的製作方法，更包含： 設置複數個電子元件於該電路基板；以及 打線接合至少部分的該些電子元件之接點至至少部分的該些接合區。
  6. 如請求項1所述之封裝模組的製作方法，更包含： 將該些引腳之一彎折部進行變截面處理。
  7. 如請求項6所述之封裝模組的製作方法，該變截面積處理包含： 將該些引腳之該彎折部於其厚度方向或寬度方向進行開槽、通孔或縮減。
  8. 一種使用如請求項1-7項任一項之製作方法所製造的封裝模組。
  9. 一種封裝模組，包含： 一電路基板，具有複數個接合區； 一外殼，組裝於該電路基板，該外殼具有複數個穿孔；以及 複數個引腳，連接於該些接合區，其中每一該些引腳包含： 一焊接部，連接該些接合區之一； 一引腳本體，垂直於該電路基板，且穿過該些穿孔之一；以及 一彎折部，連接該焊接部與該引腳本體，其中至少部份的該彎折部具有變化的截面積。
  10. 如請求項9所述之封裝模組，其中該彎折部在沿厚度方向相較於該焊接部具有縮減的厚度。
  11. 如請求項9或10所述之封裝模組，其中該彎折部在沿寬度方向相較於該焊接部具有縮減的寬度。
  12. 如請求項9所述之封裝模組，其中該彎折部具有至少一凹陷部。
  13. 如請求項12所述之封裝模組，其中至少一該凹陷部位於該彎折部的內側或是外側，且至少一該凹陷部為三角形、矩形、弧形、鋸齒狀或不規則形狀凹槽。
TW104126650A 2015-06-11 2015-08-17 封裝模組及其製作方法 TW201643969A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510319405.6A CN106298553A (zh) 2015-06-11 2015-06-11 封装模组及其制作方法

Publications (1)

Publication Number Publication Date
TW201643969A true TW201643969A (zh) 2016-12-16

Family

ID=57517248

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104126650A TW201643969A (zh) 2015-06-11 2015-08-17 封裝模組及其製作方法

Country Status (3)

Country Link
US (1) US9806010B2 (zh)
CN (1) CN106298553A (zh)
TW (1) TW201643969A (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017209097A1 (de) * 2017-05-31 2018-12-06 Robert Bosch Gmbh Verbindungsanordnung und korrespondierendes Verfahren zur Montage eines elektronischen Bauteils auf einer Leiterplatte
JP6780635B2 (ja) * 2017-12-22 2020-11-04 三菱電機株式会社 半導体モジュール
CN108109977B (zh) * 2018-02-12 2020-04-21 王艺蒲 一种用超声波铜线制造的集成电路芯片封装装置
CN110176451A (zh) * 2019-05-13 2019-08-27 珠海格力电器股份有限公司 功率模块及其封装方法
CN110752197B (zh) 2019-09-30 2022-09-16 华为技术有限公司 引线框架、封装集成电路板、电源芯片及电路板的封装方法
US11342275B2 (en) 2020-10-22 2022-05-24 Nxp Usa, Inc. Leadless power amplifier packages including topside terminations and methods for the fabrication thereof
US11984429B2 (en) 2021-09-30 2024-05-14 Nxp Usa, Inc. Leadless power amplifier packages including topside termination interposer arrangements and methods for the fabrication thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394530A (en) * 1977-09-19 1983-07-19 Kaufman Lance R Power switching device having improved heat dissipation means
JP2002043496A (ja) * 2000-07-21 2002-02-08 Hitachi Ltd 半導体装置
JP4002231B2 (ja) * 2003-11-12 2007-10-31 浜松ホトニクス株式会社 高周波信号伝送用光モジュール及びその製造方法
US7226219B2 (en) * 2003-11-12 2007-06-05 Hamamatsu Photonics K.K. High-frequency signal transmitting optical module and method of fabricating the same
TWI405349B (zh) 2004-10-07 2013-08-11 Seoul Semiconductor Co Ltd 側照明透鏡以及使用此透鏡的發光元件
DE102007005630B4 (de) 2007-02-05 2019-08-08 Infineon Technologies Ag Sensorchip-Modul und Verfahren zur Herstellung eines Sensorchip-Moduls
CN201194383Y (zh) 2008-05-09 2009-02-11 东莞市同和实业有限公司 一种网络滤波器
WO2012137685A1 (ja) * 2011-04-01 2012-10-11 富士電機株式会社 半導体装置およびその製造方法
JP5984526B2 (ja) 2012-06-20 2016-09-06 日本電波工業株式会社 表面実装型デバイス

Also Published As

Publication number Publication date
US9806010B2 (en) 2017-10-31
CN106298553A (zh) 2017-01-04
US20160365306A1 (en) 2016-12-15

Similar Documents

Publication Publication Date Title
TW201643969A (zh) 封裝模組及其製作方法
KR100324333B1 (ko) 적층형 패키지 및 그 제조 방법
KR101388328B1 (ko) 통합 ｔｈｔ 히트 스프레더 핀을 구비한 리드 프레임 기반 오버-몰딩 반도체 패키지와 그 제조 방법
TWI486105B (zh) 封裝結構及其製造方法
KR20090005599A (ko) 리드 프레임 및 이를 구비한 반도체 패키지
JP5041996B2 (ja) 固体電解コンデンサ
JP2007207802A (ja) 電子回路モジュールとその製造方法
US20120112333A1 (en) Semiconductor device with nested rows of contacts
JP6165025B2 (ja) 半導体モジュール
JP5169964B2 (ja) モールドパッケージの実装構造および実装方法
JP2002064224A (ja) 発光ダイオード及びその製造方法
JP2006108306A (ja) リードフレームおよびそれを用いた半導体パッケージ
JP2010192847A (ja) リードフレーム及びこれを用いた半導体パッケージの製造方法
KR100274854B1 (ko) 반도체장치 및 반도체장치용 리이드프레임
CN101419957B (zh) 半导体器件及其制造方法
JP5498604B1 (ja) 固体撮像素子用中空パッケージ
JP2002009217A (ja) 樹脂封止型半導体装置
JP4413054B2 (ja) 混成集積回路装置の製造方法
JP2009164240A (ja) 半導体装置
US9252090B2 (en) Resin package
JP2018117473A (ja) 回路構成体の製造方法、回路構成体及び電気接続箱
JP6569610B2 (ja) 電子装置
JP4810898B2 (ja) 半導体装置
JP6923687B2 (ja) 発光装置
JP3089384B2 (ja) 集積回路素子搭載用基板