TW201628129A - 鰭式場效電晶體裝置結構與其形成方法 - Google Patents

鰭式場效電晶體裝置結構與其形成方法 Download PDF

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TW201628129A
TW201628129A TW104139878A TW104139878A TW201628129A TW 201628129 A TW201628129 A TW 201628129A TW 104139878 A TW104139878 A TW 104139878A TW 104139878 A TW104139878 A TW 104139878A TW 201628129 A TW201628129 A TW 201628129A
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fin
barrier layer
layer
field effect
effect transistor
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TW104139878A
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TWI585900B (zh
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溫宗堯
王聖禎
世海 楊
宋學昌
鄭雅云
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種鰭式場效電晶體裝置結構，包括：一基板；一鰭式結構從該基板延伸；一抗貫穿佈植區形成於該鰭式結構之中；一阻障層形成於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及一磊晶結構，形成於該阻障層之上。

Description

鰭式場效電晶體裝置結構與其形成方法
本揭露係有關於一種半導體結構，且特別有關於一種鰭式場效電晶體裝置結構與其形成方法。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，藉以在此半導體基板之上形成電路零件及組件。通常在單一個半導體晶圓上製造許多積體電路，並且藉由沿著切割線在積體電路之間進行切割，以切割位在晶圓上的各個晶粒。舉例而言，接著將個別的晶粒分別封裝在多晶片模組中或其它類型的封裝結構中。
隨著半導體工業進展到奈米技術製程節點，以追求高裝置密度、高性能與低成本。因為製造與設計方面的問題所帶來的挑戰，因此三維設計開始發展，例如鰭式場效電晶體(FinFET)。鰭式場效電晶體(FinFET)具有從基板延伸出來的薄的垂直”鰭”。鰭式場效電晶體的通道形成於垂直鰭之中。閘極位於鰭之上。鰭式場效電晶體之優點可包括降低短通道效應與 高電流流通。
雖然現有的鰭式場效電晶體元件及其製造方法已普遍足以達成預期的目標，然而卻無法完全滿足所有需求。
本揭露提供一種鰭式場效電晶體裝置結構(FinFET device structure)包括：一基板；一鰭式結構從該基板延伸；一抗貫穿佈植區形成於該鰭式結構之中；一阻障層，形成於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及一磊晶結構，形成於該阻障層之上。
本揭露亦提供一種鰭式場效電晶體裝置結構，包括：一基板；一第一鰭式結構與一第二鰭式結構形成於該基板之上；一第一抗貫穿佈植區形成於該第一鰭式結構之中；一阻障層形成於該第一抗貫穿佈植區之上，其中該阻障層具有一凸形結構；一磊晶層，形成於該阻障層之上；以及一第二抗貫穿佈植區，形成於該第二鰭式結構之中。
本揭露又提供一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板；形成一鰭式結構於該基板之上；形成一抗貫穿佈植區於該鰭式結構之中；形成一阻障層於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及形成一磊晶層於該阻障層之上。
10‧‧‧第一區
15‧‧‧第一離子佈值製程
17‧‧‧第二離子佈值製程
20‧‧‧第二區
100‧‧‧鰭式場效電晶體裝置結構
102‧‧‧基板
104‧‧‧氧化層
106‧‧‧硬罩幕層
108‧‧‧光阻
110‧‧‧鰭式結構
110a‧‧‧第一鰭式結構
110b‧‧‧第二鰭式結構
112‧‧‧襯層
113‧‧‧介電層
114‧‧‧隔離結構
115‧‧‧凹槽
120‧‧‧抗貫穿佈植區
122‧‧‧阻障層
122m‧‧‧中間部份
122p‧‧‧週邊部份
124‧‧‧磊晶層
208‧‧‧閘極介電層
210‧‧‧閘極電極
212‧‧‧通道區
214‧‧‧源極區
216‧‧‧汲極區
220‧‧‧第二抗貫穿佈植區
402‧‧‧第一光阻(PR)層
404‧‧‧硬罩幕層
406‧‧‧第二光阻層
A‧‧‧區域
P、Q、R‧‧‧點
D1‧‧‧第一深度
D2‧‧‧第二深度
H1‧‧‧突起高度
H2‧‧‧鰭高度
H3‧‧‧鰭高度
根據以下的詳細說明並配合所附圖式做完整揭 露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖顯示依據本揭露之一些實施例之鰭式場效電晶體結構之示意圖。
第2A-2H圖顯示依據本揭露之一些實施例之形成鰭式場效電晶體結構(FinFET device structure)之剖面圖。
第3圖顯示根據本發明的一些實施例之第2F圖之區域A的放大的剖面圖。
第4A-4L圖顯示依據本揭露之一些實施例之形成鰭式場效電晶體結構(FinFET device structure)之剖面圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
下文描述實施例的各種變化。藉由各種視圖與所 繪示之實施例，類似的元件標號用於標示類似的元件。應可理解的是，額外的操作步驟可實施於所述方法之前、之間或之後，且在所述方法的其他實施例中，可以取代或省略部分的操作步驟。
本揭露提供形成鰭式場效電晶體(FinFET)裝置結構之各種實施例。第1圖顯示依據本揭露之一些實施例之鰭式場效電晶體結構100之示意圖。
鰭式場效電晶體結構100包括基板102。基板102可以由矽或其他半導體材料所組成。另外且額外的，基板102可包括其他元素半導體，例如，鍺。在一些實施例中，基板102由化合物半導體所組成，例如，碳化矽(silicon carbide,SiC)、砷化鎵(gallium arsenic,GaAs)、砷化銦(indium arsenide,InAs)或磷化銦(indium phosphide,InP)。在一些實施例中，基板102由合金半導體所組成，例如矽鍺(Silicon germanium,SiGe)、矽碳化鍺(silicon germanium carbide,SiGeC)、砷磷化鎵(gallium arsenic phosphide,GaAsP)或磷化鎵銦(gallium indium phosphide,GaInP)。在一些實施例中，基板102包括磊晶層。舉例而言，基板102是磊晶層位於塊狀半導體之上。
鰭式場效電晶體結構100也包括從基板102延伸之鰭式結構110(例如矽鰭)。在一些其他實施例中，超過一個鰭式結構110從基板102延伸。鰭式結構110可選擇性地包括鍺(Ge)。可藉由合適的製程，例如微影製程與蝕刻製程形成鰭式結構110。在一些實施例中，使用乾式蝕刻或電漿製程蝕刻基板102而得鰭式結構110。
形成隔離結構114，例如淺溝隔離(STI)結構，以圍繞鰭式結構110。在一些實施例中，鰭式結構110之底部份被隔離結構114所圍繞，且鰭式結構110之頂部份突出於隔離結構114，如第1圖所示。另言之，鰭式結構110之一部份埋設於隔離結構114之中。隔離結構114避免電子干擾或串音(crosstalk)。
鰭式場效電晶體結構100尚包括閘極堆疊結構，閘極堆疊結構包括閘極介電層208和閘極電極210。閘極堆疊結構形成在鰭式結構110的中心部分上方。在一些實施例中，在鰭式結構110上方形成多個閘極堆疊結構。在閘極結構中也可以存在多個其他層，例如，覆蓋層、介面層、間隔元件、和/或其他合適的特徵。
閘極介電層208可包括介電材料，例如氧化矽、氮化矽、氮氧化矽、具有高介電常數(high-k)之介電材料，或上述之組合。高介電常數(high-k)材料的實例包括氧化鉿、氧化鋯、氧化鋁、二氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、類似之材料或上述組合。
閘極電極210可以包括多晶矽或金屬。金屬包括氮化鉭(TaN)、矽化鎳(NiSi)、矽化鈷(CoSi)、鉬(Mo)、銅(Cu)、鎢(W)、鋁(Al)、鈷(Co)、鋯(Zr)、鉑(Pt)或其他適用的材料。可以藉由後閘極製程(或閘極替代製程)形成閘極電極210。在一些實施例中，閘極堆疊結構包括額外的層，諸如介面層、覆蓋層、擴散/阻擋層或其他合適的層。
鰭式結構110包括由閘極電極210和閘極介電層208圍繞或包裹的通道區212。可以摻雜鰭式結構110以提供用 於n型FinFET(NMOS元件)或p型FinFET(PMOS元件)的合適的通道。可以使用例如離子佈植製程、擴散製程、退火製程、其他適用的製程或上述之組合的合適的製程摻雜鰭式結構110。鰭式結構110包括源極區214和汲極區216，通道區212位於源極區214和汲極區216之間。鰭式場效電晶體結構(FinFET)100可以是包括在微處理器、記憶體單元(例如，靜態隨機存取記憶體(SRAM))，和/或其他積體電路中的元件。
襯層112順應性地形成在鰭式結構110的側壁上。抗貫穿佈植(anti-punch through(APT)implant)區120形成在鰭式結構110中並且低於隔離結構114的頂表面。抗貫穿佈植區120用於減少亞閾值源極至汲極漏電(sub-threshold source-to-drain leakage)和汲極偏壓導致通道能障降低效應(Drain-Induced Barrier Lowering,DIBL)。阻障層122形成在抗貫穿佈植區120上以防止抗貫穿佈植區120擴散到通道區212內。在後文中描述抗貫穿佈植區120和阻障層122的詳細的形成方法。
第2A-2H圖顯示依據本揭露之一些實施例之形成鰭式場效電晶體結構(FinFET device structure)100之剖面圖。第2A-2H圖是沿著第1圖之線I-I’所獲得之剖面圖。
請參見第2A圖，提供基板102。在一些實施例中，提供矽(Si)基板。之後，形成氧化層104與硬罩幕層106於基板102之上，以及形成光阻層108於硬罩幕層106之上。藉由圖案化製程圖案化光阻層108。圖案化製程包括微影製程與蝕刻製程。微影製程包括光阻塗佈(photoresist coating)(例如旋轉塗 佈)、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤(post-exposure)、光阻顯影(developing photoresist)、潤洗(rising)、乾燥(例如硬烘烤(hard baking))。蝕刻製程包括乾式蝕刻製程、濕式蝕刻製程或上述之組合。
氧化層104是位於基板102和硬罩幕層106之間的緩衝層。此外，當去除硬罩幕層106時，氧化物層104做為停止層。氧化層104可以由氧化矽製成。硬罩幕層106可以由氧化矽、氮化矽、氮氧化矽、或其他適用的材料製成。在一些其他的實施例中，在氧化層104上形成多於一個的硬罩幕層106。
藉由沉積製程形成氧化層104和硬罩幕層106，沉積製程例如化學氣相沉積(CVD)製程、高密度電漿化學氣相沉積(HDPCVD)製程、旋塗製程、濺鍍製程或其他合適的製程。
依據本揭露之一些實施例，如第2B圖所示，在圖案化光阻層108之後，使用圖案化後之光阻層108作為光罩，以圖案化氧化層104和硬罩幕層106。如此一來，獲得圖案化後之氧化層104與圖案化後之硬罩幕層106。之後，藉由將圖案化後的氧化物層104和圖案化後的硬罩幕層106用作光罩，對基板102進行蝕刻製程以形成鰭式結構110。
需注意的是，可以根據實際應用調整鰭式結構110的數目，並且鰭式結構110的數目不限於一個鰭式結構110。鰭式結構110具有從頂部至底部逐漸增加的寬度。
蝕刻製程可以是乾式蝕刻製程或濕式蝕刻製程。在一些實施例中，通過乾式蝕刻製程蝕刻基板102，並且使用包括六氟化硫(SF6)、碳氟化物(CxFy)、三氟化氮(NF3)或上述的 組合之氟基蝕刻劑氣體(fluorine-based etchant gas)。蝕刻製程可以是時間控制的製程，並且繼續進行直到鰭式結構110達到預定的高度。
依據本揭露之一些實施例，如第2C圖所示，在形成鰭式結構110之後，在鰭式結構110的側壁上順應性地形成襯層112。
襯層112用於保護鰭式結構110不受隨後的製程(諸如退火製程或蝕刻製程)的損壞。因此，通過襯層112的保護來維持鰭式結構110的輪廓。襯層112包括氮化矽、氮氧化矽、碳化矽、碳氮氧化矽或上述之組合。襯層112可以是單層或多層。
之後，介電材料形成於鰭式結構110與襯層112之上，且接著薄化或平坦化介電材料，以形成隔離結構114。因此，隔離結構114的頂表面與鰭式結構110的頂表面等高。隔離結構114是由氧化矽、氮化矽、或其他合適的材料所製成的。可以通過化學氣相沉積(CVD)製程、旋塗玻璃製程或其他合適的製程沉積隔離結構114。
依據本揭露之一些實施例，如第2D圖所示，之後，移除一部份之鰭式結構110與一部份之襯層112。如此一來，在隔離結構114中形成凹槽115。在一些實施例中，通過例如乾式蝕刻製程或濕式蝕刻製程的蝕刻製程，以去除部份之鰭式結構110與部份之襯層112。凹槽115具有第一深度D1。在一些實施例中，第一深度D1之範圍為約40nm到70nm。
依據本揭露之一些實施例，如第2E圖所示，在蝕刻製程之後，形成抗貫穿佈植區120於鰭式結構110之中。抗貫 穿佈植區120可以是n型抗貫穿佈植區或是p型抗貫穿佈植區。在一些實施例中，藉由摻雜n型摻雜質，例如砷(As)、磷(P)、或銻(Sb)以獲得n型抗貫穿佈植區。在一些實施例中，藉由摻雜p型摻雜質，例如硼(B)或氟化硼(BF2)，以獲得p型抗貫穿佈植區。在一些實施例中，進行離子佈植(ion implantation,IMP)製程以形成抗貫穿佈植區120。在一些實施例中，在從約3keV到約7keV的範圍內的功率下，對表面區域進行離子佈植製程。
在形成抗貫穿佈植區120之後，進行熱處理製程，以活化抗貫穿佈植區120之中的摻雜質。在一些實施例中，藉由快速熱退火製程(rapid thermal annealing process)進行熱處理製程。
依據本揭露之一些實施例，如第2F圖所示，在形成抗貫穿佈植區120之後，形成阻障層122於抗貫穿佈植區120之上。阻障層122用於阻擋抗貫穿佈植區120之擴散。阻障層122包括碳化矽(SiC)、碳化矽鍺(SiGeC)或上述之組合。
在一些實施例中，阻障層122是由碳化矽(SiC)所組成，碳濃度之範圍為約0.5%至約1.0%。如果碳濃度太低，則阻障層122的阻擋效果不夠好。如果碳濃度太高，則阻障層122的晶格常數會與基板102的晶格常數失配。
在一些實施例中，阻障層122是由碳化矽鍺(SiGeC)製成的，碳濃度之範圍為約0.5%至約1.0%，並且鍺濃度之範圍為約5%至約20%。如果碳濃度太低，則阻障層122的阻擋效果不夠好。如果碳濃度太高，則阻障層122的晶格常數會與基板102的晶格常數失配。
在一些實施例中，藉由磊晶(epi)製程形成阻障層122。磊晶製程可包括選擇性磊晶生長(SEG)製程、化學氣相沉積(CVD)沉積技術(例如，氣相磊晶(VPE)和/或超高真空CVD(UHV-CVD))、分子束磊晶或其他合適的磊晶製程。在一些實施例中，在約450度到約650度的範圍內的溫度下操作磊晶製程，以形成阻障層122。在一些實施例中，藉由在約1托(torr)到約50托(torr)的範圍內的壓力下操作磊晶製程，以形成阻障層122。
第3圖顯示根據本發明的一些實施例之第2F圖之區域A的放大的剖面圖。阻障層122具有凸形輪廓(convex profile)並且阻障層122沿著(111)面磊晶生長。在一些實施例中，阻障層122具有凸形彎月面結構(convex meniscus structure)。
阻障層122具有中間部份122m和週邊部份122p。中間部分122m高於週邊部分122p。點P和點R位於週邊部分122p的最低位置。點P和點R與抗貫穿佈植區120之頂表面大致上等高。最高點Q位於中間部分122m處。中間部分122m在抗貫穿佈植區120的頂表面上方具有突起高度H1。從中間部分122m的底表面至點Q測量突起高度H1。在一些實施例中，突起高度H1之範圍為約5nm到約10nm。如果突起高度H1太低，則控制抗貫穿佈植回擴散的能力可能降低。如果突起高度H1太高，將損失通道應力並且可能會降低遷移率。
依據本揭露之一些實施例，如第2G圖所示，在形成阻障層122之後，磊晶層124形成於阻障層122之上。磊晶層 124作為應力層。位於閘極電極層之下的一部份的磊晶層124稱為通道區域。舉例而言，如第1圖所示，通道區域212位於閘極電極210之下。當形成p型鰭式場效電晶體結構(FinFET device structure)時，藉由形成磊晶層124使半導體元件100的通道區212應變。因此，改進了通道區212的遷移率。
磊晶層124包括矽鍺(SiGe)、鍺(Ge)或上述之組合。在一些實施例中，當磊晶層124由矽鍺(SiGe)形成時，鍺濃度之範圍為約50%至約70%。
在一些實施例中，藉由磊晶(epi)製程形成磊晶層124。磊晶製程可以包括選擇性磊晶生長(SEG)製程、化學氣相沉積(CVD)技術(例如，汽相磊晶(VPE)和/或超高真空CVD(UHV-CVD))、分子束磊晶、或其他合適的磊晶製程。
在一些實施例中，磊晶層124是藉由為約450度至約650度的範圍內的溫度下操作的磊晶製程而形成。然而，磊晶製程是熱製程。需注意的是，在形成抗貫穿(APT)佈植區120之後，實施熱製程。如果在抗貫穿佈植區120上方沒有形成阻障層，則摻雜劑可能擴散到位於抗貫穿佈植區120之上的通道區(諸如磊晶層124)內。結果，由於摻雜劑的擴散，可能會降低通道區的遷移率。為了減緩或阻擋抗貫穿佈植區120的摻雜劑的擴散，阻障層122形成在抗貫穿佈植區120之上。換句話說，阻障層122形成在抗貫穿佈植區120和磊晶層124(或通道區)之間。
需注意的是，阻障層122和磊晶層124均由磊晶(epi)製程形成。因此，為了方便和有效，在腔室中原位(in-situ)實 施形成阻障層122和形成磊晶層124而不被運到另一個工作臺。此外，降低了製造成本。
依據本揭露之一些實施例，如第2H圖所示，在形成磊晶層124之後，去除隔離結構114的一部分，以暴露磊晶層124的頂面。
如果阻障層122具有矩形形狀，則由於阻障層122佔據空間而可以減小鰭高度。相反，由於阻障層122具有凸形彎月面結構，鰭高度H2不減小。從點P或點R測量鰭高度H2，並且點P或點R處於阻障層122的最低位置。從點P至磊晶層124的頂面測量鰭高度H2。因此，由於凸形輪廓的阻障層122的形成，沒有減小鰭高度。在一些實施例中，鰭高度H2之範圍為約20奈米(nm)到約60奈米(nm)。
第4A圖至第4L圖顯示根據本發明的一些實施例的形成鰭式場效應電晶體(FinFET)元件結構200的剖面圖。
請參見第4A圖，基板102被劃分為第一區10和第二區20。第一鰭式結構110a形成在第一區10中並且第二鰭式結構110b形成在第二區20中。p型鰭式場效應電晶體(FinFET元)件結構將在第一區10中形成，並且n型鰭式場效應電晶體(FinFET)元件結構將在第二區20中形成。
根據本發明的一些實施例，如第4B圖所示，在形成第一鰭式結構110a和第二鰭式結構110b之後，襯層112順應地形成在第一鰭式結構110a和第二鰭式結構110b的側壁上。
根據本發明的一些實施例，如第4C圖所示，在形成襯層112後，沉積介電層113於襯層112上。
之後，對介電層113實施平坦化製程以暴露第一鰭式結構110a和第二鰭式結構110b的頂表面。結果，獲得隔離結構114。在一些實施例中，平坦化製程是化學機械拋光(CMP)製程。
根據本發明的一些實施例，如第4D圖所示，第一光阻(PR)層402形成於第一區10上的第一鰭式結構110a上。第一光阻層402沉積於第一區10和第二區20之上，並且圖案化第一光阻層402以在第一區10中形成圖案化的第一光阻層402。圖案化的第一光阻層402用於保護下面的層。
之後，對第二鰭式結構110b實施第一離子佈值製程15，以在第二鰭式結構110b的頂部份中形成第二抗貫穿(APT)佈植區220。在一些實施例中，在第二區20中形成n型鰭式場效應電晶體(FinFET)元件結構，將例如硼(B)或氟化硼(BF2)的p型摻雜劑摻雜至第二鰭式結構110b內。
根據本發明的一些實施例，如第4E圖所示，在形成第二抗貫穿佈植區220之後，硬罩幕層404形成於第一鰭式結構110a和第二抗貫穿佈植區220之上。之後，在硬罩幕層404上形成並且圖案化第二光阻層406，以形成圖案化的第二光阻層406。
根據本發明的一些實施例，如第4F圖所示，在形成圖案化的第二光阻層406之後，藉由將圖案化的第二光阻層406用作光罩，以圖案化硬罩幕層404。
之後，去除第一鰭式結構110a的頂部份，以在隔離結構114中形成凹槽115。此外，去除襯層112的頂部份。因此， 在凹槽115中暴露隔離結構114。凹槽115具有第二深度D2。在一些實施例中，第二深度D2之範圍為約40奈米(nm)至約70奈米(nm)。
根據本發明的一些實施例，如第4G圖所示，在蝕刻製程之後，對第一區10實施第二離子佈植製程17，以在第一鰭式結構110a中形成第一抗貫穿佈植區120。在一些實施例中，在第一區10中形成p型鰭式場效應電晶體(FinFET)元件結構，將例如砷(As)、磷(P)或銻(Sb)的n型摻雜劑摻雜到第一鰭式結構110a內。
根據本發明的一些實施例，如第4H圖所示，在形成第一抗貫穿佈植區120之後，在第一抗貫穿佈植區120上形成阻障層122。阻障層122用於阻擋抗貫穿佈植區120擴散到通道區(之後形成)內。阻障層122具有凸形結構，凸形結構具有高於週邊部分122p的中間部分122m。阻障層122包括碳化矽(SiC)、碳化矽鍺(SiGeC)或上述之組合。
根據本發明的一些實施例，如第4I圖所示，在形成阻障層122之後，磊晶層124形成於阻障層122上。當在第一區10中形成p型鰭式場效應電晶體(FinFET)元件結構時，磊晶層124用作應變層。磊晶層124包括矽鍺(SiGe)、鍺(Ge)或上述之組合。藉由磊晶製程形成磊晶層124。
在一些實施例中，在相同腔室中原位(in-situ)形成阻障層122和磊晶層124而不被運到另一個腔室。此外，減少了製造操作和成本。
根據本發明的一些實施例，如第4J圖所示，在形成 磊晶層124之後，對磊晶層124實施平坦化製程，以使磊晶層124的頂表面與隔離結構114的頂表面等高。在一些實施例中，平坦化製程是化學機械研磨(CMP)製程。
根據本發明的一些實施例，如第4K圖所示，在平坦化製程之後，去除一部分的隔離結構114，以暴露磊晶層124和阻障層122。通過例如乾蝕刻製程或濕蝕刻製程的蝕刻製程去除一部分的隔離結構114。
根據本發明的一些實施例，如第4L圖所示，在去除隔離結構114的部分之後，閘極介電層208形成於第一鰭式結構110a和第二鰭式結構110b之上。之後，在閘極介電層208上形成閘極電極210。
需注意的是，磊晶層124的一部分用作通道區。阻障層122被配置為阻擋抗貫穿佈植區120的擴散。藉由在抗貫穿佈植區120和磊晶層124之間形成阻障層120，因而阻擋了抗貫穿佈植區120的擴散，因此改善通道區的遷移率。因此，提高了鰭式場效應電晶體(FinFET)元件結構200的性能。此外，阻障層120具有特定的凸形形狀，因此鰭高度H3不減小。
本揭露提供形成鰭式場效電晶體結構之實施例。鰭式結構形成於基板之上。在鰭式結構中形成抗貫穿佈植區，並且在抗貫穿佈植區之上形成阻障層。在阻障層之上形成磊晶層，一部份的磊晶層作為通道區。阻障層介於抗貫穿佈植區和通道區之間，以減緩或阻擋抗貫穿佈植區的摻雜劑的擴散。因此，改善通道區的遷移率，並且進一步改進了鰭式場效電晶體(FinFET)元件結構的性能。
在一些實施例中，本揭露提供一種鰭式場效電晶體裝置結構(FinFET device structure)包括：一基板；一鰭式結構，從該基板延伸；一抗貫穿佈植區形成於該鰭式結構之中；一阻障層，形成於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及一磊晶結構，形成於該阻障層之上。
在一些實施例中，本揭露提供一種鰭式場效電晶體裝置結構，包括：一基板；一第一鰭式結構與一第二鰭式結構形成於該基板之上；一第一抗貫穿佈植區形成於該第一鰭式結構之中；一阻障層形成於該第一抗貫穿佈植區之上，其中該阻障層具有一凸形結構；一磊晶層，形成於該阻障層之上；以及一第二抗貫穿佈植區，形成於該第二鰭式結構之中。
在一些實施例中，本揭露有關於一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板；形成一鰭式結構於該基板之上；形成一抗貫穿佈植區於該鰭式結構之中；形成一阻障層於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及形成一磊晶層於該阻障層之上。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明 精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧鰭式場效電晶體裝置結構
102‧‧‧基板
112‧‧‧襯層
114‧‧‧隔離結構
120‧‧‧抗貫穿佈植區
122‧‧‧阻障層
124‧‧‧磊晶層
P、R‧‧‧點
H2‧‧‧鰭高度

Claims (10)

  1. 一種鰭式場效電晶體裝置結構(FinFET device structure)，包括：一基板；一鰭式結構，從該基板延伸；一抗貫穿佈植區，形成於該鰭式結構之中；一阻障層，形成於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及一磊晶結構，形成於該阻障層之上。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該阻障層具有凸形結構。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該阻障層是沿著(111)面磊晶生長的。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，尚包括：一隔離結構，形成於該基板之上，其中該鰭式結構埋設於該隔離結構之中，且該抗貫穿佈植區位於該隔離結構之一頂表面之下。
  5. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，其中該中間部分具有位於該抗貫穿佈植區之一頂表面上方的一突起高度，並且該突起高度之範圍為約5nm至約10nm。
  6. 一種鰭式場效電晶體裝置結構，包括： 一基板；一第一鰭式結構與一第二鰭式結構，形成於該基板之上；一第一抗貫穿佈植區，形成於該第一鰭式結構之中；一阻障層，形成於該第一抗貫穿佈植區之上，其中該阻障層具有一凸形結構；一磊晶層，形成於該阻障層之上；以及一第二抗貫穿佈植區，形成於該第二鰭式結構之中。
  7. 如申請專利範圍第6項所述之鰭式場效電晶體裝置結構，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份。
  8. 如申請專利範圍第6項所述之鰭式場效電晶體裝置結構，尚包括：一隔離結構，形成於該基板之上，其中該第一鰭式結構埋設於該隔離結構之中，且該第一抗貫穿佈植區位於該隔離結構之一頂表面之下。
  9. 一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板；形成一鰭式結構於該基板之上；形成一抗貫穿佈植區於該鰭式結構之中；形成一阻障層於該抗貫穿佈植區之上，其中該阻障層具有一中間部份與一週邊部份，且該中間部份高於該週邊部份；以及形成一磊晶層於該阻障層之上。
  10. 如申請專利範圍第9項所述之鰭式場效電晶體裝置結構之 形成方法，其中於一腔室中原位(in-situ)形成該阻障層與形成該磊晶層。
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