CN106206729B - 鳍式场效应晶体管(finfet)器件结构及其形成方法 - Google Patents

鳍式场效应晶体管(finfet)器件结构及其形成方法 Download PDF

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CN106206729B
CN106206729B CN201510262860.7A CN201510262860A CN106206729B CN 106206729 B CN106206729 B CN 106206729B CN 201510262860 A CN201510262860 A CN 201510262860A CN 106206729 B CN106206729 B CN 106206729B
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finfet
fin
field effect
effect transistor
barrier layer
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CN106206729A (zh
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温宗尧
王圣祯
杨世海
宋学昌
郑雅云
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明提供了鳍式场效应晶体管(FinFET)器件结构及其形成方法。FinFET器件结构包括衬底和从衬底延伸的鳍结构。FinFET器件结构也包括形成在鳍结构中的抗穿通注入(APT)区和形成在APT区上的阻挡层。阻挡层具有中间部分和外围部分，并且中间部分高于外围部分。FinFET器件结构还包括形成在阻挡层上的外延层。

Description

鳍式场效应晶体管(FINFET)器件结构及其形成方法
相关申请的交叉引用
本申请涉及于2015年1月28日提交的标题为“Method of forming semiconductorstructure with anti-punch through structure”的共同代决的共同转让的美国专利申请第14/607,780号(申请人代理卷号P20141119US00)，其全部内容结合于此作为参考。
技术领域
本发明涉及鳍式场效应晶体管(FINFET)器件结构及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层、和半导体材料层并且使用光刻以图案化各个材料层以在其上形成电路部件和元件来制造半导体器件。通常在单个半导体晶圆上制造许多集成电路，和通过在集成电路之间沿着划线锯切来在晶圆上分割晶圆上的单个的管芯。例如，通常以多芯片模式或以其他类型的封装模式来单独地封装单个管芯。
随着半导体产业已经步入纳米技术工艺节点以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战已导致诸如鳍式场效应晶体管(FinFET)的三维设计的发展。用从衬底延伸的薄垂直“鳍”(或鳍结构)制造FinFET。FinFET的沟道形成在该垂直鳍中。在鳍上方提供栅极。FinFET的优势可以包括降低短沟道效应和提供更高的电流。
虽然现有的FinFET器件和制造FinFET器件的方法通常已满足它们的预期目的，但是它们并非在所有方面都尽如人意。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种鳍式场效应晶体管(FinFET)器件结构，包括：衬底；鳍结构，从所述衬底延伸；抗穿通注入(APT)区，形成在所述鳍结构中；阻挡层，形成在所述APT区上，其中，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分；以及外延层，形成在所述阻挡层上。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述阻挡层具有凸形结构。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述阻挡层包括碳化硅(SiC)或碳化硅锗(SiGeC)。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述阻挡层是沿着(111)面外延生长的。
在上述鳍式场效应晶体管(FinFET)器件结构中，还包括：隔离结构，形成在所述衬底上，其中，所述鳍结构嵌入在所述隔离结构中，并且所述APT区位于所述隔离结构的顶面下方。
在上述鳍式场效应晶体管(FinFET)器件结构中，还包括：衬垫，形成在所述鳍结构的侧壁上。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述外延层包括硅锗(SiGe)、锗(Ge)或它们的组合。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述中间部分具有位于所述APT区的顶面上方的突起高度，并且所述突起高度在从约5nm至约10nm的范围内。
根据本发明的另一方面，还提供了一种鳍式场效应晶体管(FinFET)器件结构，包括：衬底；第一鳍结构和第二鳍结构，形成在所述衬底上；第一抗穿通注入(APT)区，形成在所述第一鳍结构中；阻挡层，形成在所述第一APT区上，其中，所述阻挡层具有凸形结构；和外延层，形成在所述阻挡层上；以及第二APT区，形成在所述第二鳍结构中。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述第一鳍结构配置为形成p型FinFET，并且所述第二鳍结构配置为形成n型FinFET。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述外延层包括硅锗(SiGe)、锗(Ge)或它们的组合。
在上述鳍式场效应晶体管(FinFET)器件结构中，还包括：隔离结构，形成在所述衬底上，其中，所述第一鳍结构嵌入在所述隔离结构中，并且所述第一APT区位于所述隔离结构的顶面下方。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述第二APT区高于所述隔离结构的顶面。
在上述鳍式场效应晶体管(FinFET)器件结构中，所述阻挡层是沿着(111)面外延生长的。
在上述鳍式场效应晶体管(FinFET)器件结构中，还包括：栅极介电层，形成在所述外延层上；以及栅电极层，形成在所述栅极介电层上。
根据本发明的又一方面，还提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法，包括：提供衬底；在所述衬底上形成鳍结构；在所述鳍结构中形成抗穿通注入(APT)区；在所述APT区上形成阻挡层，其中，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分；以及在所述阻挡层上形成外延层。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中，在所述APT区上形成所述阻挡层包括在所述APT区上实施外延工艺。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中，在腔室中原位实施形成所述阻挡层和形成所述外延层。
在上述用于形成鳍式场效应晶体管(FinFET)器件结构的方法中，还包括：在所述外延层上形成栅极介电层；以及在所述栅极介电层上形成栅电极层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构的立体图。
图2A至图2H示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的截面图。
图3示出了根据本发明的一些实施例的图2F的区域A的放大的截面图。
图4A至图4L示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
描述了实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于代表相同的元件。应当理解，可以在该方法之前、期间和之后提供额外的操作，并且对于该方法的其他实施例，可以取代或消除描述的一些操作。
提供了用于形成鳍式场效应晶体管(FinFET)器件结构的实施例。图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的立体图。
FinFET器件结构100包括衬底102。衬底102可以由硅或其他半导体材料制成。可选地或额外地，衬底102可以包括诸如锗的其他元素半导体材料。在一些实施例中，衬底102是由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成的。在一些实施例中，衬底102是由诸如硅锗、碳化硅锗、磷砷化镓或磷化镓铟的合金半导体制成的。在一些实施例中，衬底102包括外延层。例如，衬底102具有位于块状半导体上方的外延层。
FinFET器件结构100还包括从衬底102延伸的鳍结构110(例如，Si鳍)。在一些其他实施例中，不止一个鳍结构110从衬底102延伸。鳍结构110可任选地包括锗(Ge)。鳍结构110可以通过使用诸如光刻和蚀刻工艺的合适的工艺形成。在一些实施例中，使用干蚀刻或等离子体工艺从衬底102蚀刻鳍结构110。
形成诸如浅沟槽隔离(STI)结构的隔离结构114以围绕鳍结构110。如图1所示，在一些实施例中，鳍结构110的下部由隔离结构114围绕，并且鳍结构110的上部从隔离结构114突出。换句话说，该鳍结构110的一部分嵌入在隔离结构114中。隔离结构114防止电气干扰和串扰。
FinFET器件结构100还包括栅极堆叠结构，栅极堆叠结构包括栅极介电层208和栅电极210。栅极堆叠结构形成在鳍结构110的中心部分上方。在一些实施例中，在鳍结构110上方形成多个栅极堆叠结构。在栅极结构中也可以存在多个其他层，例如，覆盖层、界面层、间隔元件、和/或其他合适的部件。
栅极介电层208可以包括介电材料，诸如氧化硅、氮化硅、氮氧化硅、具有高介电常数(高k)的介电材料或它们的组合。高k介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆等或它们的组合。
栅电极210可以包括多晶硅或金属。金属包括氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、钼(Mo)、铜(Cu)、钨(W)、铝(Al)、钴(Co)、锆(Zr)、铂(Pt)或其他适用的材料。可以以后栅极工艺(或栅极替代工艺)形成栅电极210。在一些实施例中，栅极堆叠结构包括额外的层，诸如界面层、覆盖层、扩散/阻挡层或其他适用的层。
鳍结构110包括由栅电极210和栅极介电层208围绕或包裹的沟道区212。可以掺杂鳍结构110以提供用于n型FinFET(NMOS器件)或p型FinFET(PMOS器件)的合适的沟道。可以使用诸如离子注入工艺、扩散工艺、退火工艺、其他适用的工艺或它们的组合的合适的工艺掺杂鳍结构110。鳍结构110包括源极区214和漏极区216，沟道区212位于源极区214和漏极区216之间。FinFET器件100可以是包括在微处理器、存储器单元(例如，静态随机存取存储器(SRAM))，和/或其他集成电路中的器件。
衬垫层112共形地形成在鳍结构110的侧壁上。抗穿通注入(APT)区120形成在鳍结构110中并且低于隔离结构114的顶面。APT区120用于减少亚阈值源极至漏极泄漏和漏极诱导势垒降低(DIBL)。阻挡层122形成在APT区120上以防止APT区120扩散到沟道区212内。在后文中描述APT区120和阻挡层122的详细的形成方法。
图2A至图2H示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的截面图。图2A至图2H示出了沿着图1的线I-I’截取的截面图。
参考图2A，提供衬底102。在一些实施例中，提供硅(Si)衬底102。之后，在衬底102上形成氧化物层104和硬掩模层106，以及在硬掩模层106上形成光刻胶层108。通过图案化工艺图案化光刻胶层108。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺包括光刻胶涂覆(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗和干燥(例如，硬烘烤)。蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。
氧化物层104是位于衬底102和硬掩模层106之间的缓冲层。此外，当去除硬掩模层106时，氧化物层104用作停止层。氧化物层104可以由氧化硅制成。硬掩模106可以由氧化硅、氮化硅、氮氧化硅、或其他适用的材料制成。在一些其他的实施例中，在氧化物层104上形成不止一个硬掩模层106。
通过沉积工艺形成氧化物层104和硬掩模层106，沉积工艺诸如化学汽相沉积(CVD)工艺、高密度等离子体化学汽相沉积(HDPCVD)工艺、旋涂工艺、溅射工艺或其他适用的工艺。
如图2B所示，根据一些实施例，在图案化光刻胶层108之后，通过将图案化的光刻胶层108用作掩模来图案化氧化物层104和硬掩模层106。结果，得到图案化的氧化物层104和图案化的硬掩模层106。然后，通过将图案化的氧化物层104和图案化的硬掩模层106用作掩模，对衬底102实施蚀刻工艺以形成鳍结构110。
应当指出的是，可以根据实际应用调整鳍结构110的数目，并且鳍结构110的数目不限于一个鳍结构110。鳍结构110具有从顶部至下部逐渐增加的宽度。
蚀刻工艺可以是干蚀刻工艺或湿蚀刻工艺。在一些实施例中，通过干蚀刻工艺蚀刻衬底102，并且氟基蚀刻剂气体包括SF6、CxFy、NF3或它们的组合。蚀刻工艺可以是时间控制的工艺，并且继续进行直到鳍结构110达到预定的高度。
如图2C所示，根据一些实施例，在形成鳍结构110之后，在鳍结构110的侧壁上共形地形成衬垫层112。
衬垫层112用于保护鳍结构110不受随后的工艺(诸如退火工艺或蚀刻工艺)的损坏。因此，通过衬垫层112的保护来维持鳍结构110的轮廓。衬垫层112包括氮化硅、氮氧化硅、碳化硅、碳氮氧化硅或它们的组合。衬垫层112可以是单层或多层。
之后，在鳍结构110和衬垫层112上形成介电材料，和然后减薄或平坦化介电材料以形成隔离结构114。结果，隔离结构114的顶面与鳍结构110的顶面平齐。隔离结构114是由氧化硅、氮化硅、或其他适用的材料制成的。可以通过化学汽相沉积(CVD)工艺、旋涂玻璃工艺或其他适用的工艺沉积隔离结构114。
之后，如图2D所示，根据一些实施例，去除鳍结构110的顶部和衬垫层112的一部分。结果，在隔离结构114中形成凹槽115。在一些实施例中，通过诸如干蚀刻工艺或湿蚀刻工艺的蚀刻工艺去除鳍结构110的部分和衬垫层112的部分。凹槽115具有第一深度D1。在一些实施例中，第一深度D1是在从约40nm到70nm的范围内。
在蚀刻工艺之后，如图2E所示，根据一些实施例，在鳍结构110中形成抗穿通注入(APT)区120。APT区120可以是n型APT区或p型APT区。在一些实施例中，通过掺杂诸如砷(As)、磷(P)或锑(Sb)的n型掺杂剂来获得n型APT区。在一些实施例中，通过掺杂诸如硼(B)或氟化硼(BF2)的p型掺杂剂来获得p型APT区。在一些实施例中，实施离子注入(IMP)工艺以形成APT区120。在一些实施例中，在从约3keV到约7keV的范围内的功率下，对表面区域实施IMP工艺。
在形成APT区120之后，实施热工艺以活化APT区120中的掺杂剂。在一些实施例中，通过快速热退火工艺实施热工艺。
如图2F所示，根据一些实施例，在形成APT区120之后，在APT区120上形成阻挡层122。阻挡层122用于阻挡APT区120的扩散。阻挡层122包括碳化硅(SiC)、碳化硅锗(SiGeC)或它们的组合。
在一些实施例中，阻挡层122是由碳化硅(SiC)制成的，碳浓度在从约0.5％到约1.0％的范围内。如果碳浓度太低，则阻挡层122的阻挡效果不够好。如果碳浓度太高，则阻挡层122的晶格常数会与衬底102的晶格常数失配。
在一些实施例中，阻挡层122是由碳化硅锗(SiGeC)制成的，碳浓度在从约0.5％到约1.0％的范围内，并且锗浓度在从约5％至约20％的范围内。如果碳浓度太低，则阻挡层122的阻挡效果不够好。如果碳浓度太高，则阻挡层122的晶格常数会与衬底102的晶格常数失配。
在一些实施例中，阻挡层122通过外延(epi)工艺形成。外延工艺可包括选择性外延生长(SEG)工艺、CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延或其他合适的外延工艺。在一些实施例中，阻挡层122是通过在从约450度到约650度的范围内的温度下操作的外延工艺形成的。在一些实施例中，阻挡层122是通过在从约1托到约50托的范围内的压力下操作的外延工艺形成的。
图3示出了根据本发明的一些实施例的图2F的区域A的放大的截面图。阻挡层122具有凸形轮廓并且阻挡层122沿着(111)面外延生长。在一些实施例中，阻挡层122具有凸形弯月面结构。
阻挡层122具有中间部分122m和外围部分122p。中间部分122m高于外围部分122p。点P和点R位于外围部分122p的最低位置。点P和点R与APT区120的顶面基本上平齐。最高点Q位于中间部分122m处。中间部分122m在APT区120的顶面上方具有突起高度H1。从中间部分122m的底面至点Q测量突起高度H1。在一些实施例中，突起高度H1在从约5nm到约10nm的范围内。如果突起高度H1太低，则控制APT回扩散的能力可能降低。如果突起高度H1太高，则沟道应力将损失并且迁移率可能会降低。
如图2G所示，根据本发明的一些实施例，在形成阻挡层122之后，在阻挡层122上形成外延层124。外延层124用作应变层。外延层124的位于栅电极层下方的部分称为沟道区。例如，如图1所示，沟道区212形成在栅电极210下方。当形成p型FinFET器件结构时，通过形成外延层124使半导体器件100的沟道区212应变。因此，改进了沟道区212的迁移率。
外延层124包括硅锗(SiGe)、锗(Ge)或它们的组合。在一些实施例中，当外延层124由硅锗(SiGe)制成时，锗浓度在从约50％至约70％的范围内。
在一些实施例中，通过外延(epi)工艺形成外延层124。外延工艺可以包括选择性外延生长(SEG)工艺、CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延、或其他合适的外延工艺。
在一些实施例中，外延层124是通过在从约450度到约650度的范围内的温度下操作的外延工艺形成的。然而，外延工艺是热工艺。应该指出的是，在形成APT区120之后，实施热工艺。如果在APT区120上方没有形成阻挡层，则掺杂剂可能扩散到位于APT区120之上的沟道区(诸如外延层124)内。结果，由于掺杂剂的扩散，可能会降低沟道区的迁移率。为了减缓或阻挡APT区120的掺杂剂的扩散，阻挡层122形成在APT区120之上。换句话说，阻挡层122形成在APT区120和外延层124(或沟道区)之间。
应该指出的是，阻挡层122和外延层124均由外延(epi)工艺形成。因此，为了方便和有效，在腔室中原位实施形成阻挡层122和形成外延层124而不被运到另一个工作台。此外，降低了制造成本。
如图2H所示，根据本发明的一些实施例，在形成外延层124之后，去除隔离结构114的一部分，以暴露外延层124的顶面。
如果阻挡层122具有矩形形状，则由于阻挡层122占据空间而可以减小鳍高度。相反，由于阻挡层122具有凸形弯月面结构，鳍高度H2不减小。从点P或点R测量鳍高度H2，并且点P或点R处于阻挡层122的最低位置。从点P至外延层124的顶面测量鳍高度H2。因此，由于凸形轮廓的阻挡层122的形成，没有减小鳍高度。在一些实施例中，鳍高度H2在从约20nm到约60nm的范围内。
图4A至图4L示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构200的截面图。
参考图4A，衬底102被划分为第一区10和第二区20。第一鳍结构110a形成在第一区10中并且第二鳍结构110b形成在第二区20中。p型FinFET器件结构将在第一区10中形成，并且n型FinFET器件结构将在第二区20中形成。
如图4B所示，根据本发明的一些实施例，在形成第一鳍结构110a和第二鳍结构110b之后，在第一鳍结构110a和第二鳍结构110b的侧壁上共形地形成衬垫层112。
如图4C所示，根据本发明的一些实施例，在形成衬垫层112后，在衬垫层112上沉积介电层113。
之后，对介电层113实施平坦化工艺以暴露第一鳍结构110a和第二鳍结构110b的顶面。结果，获得隔离结构114。在一些实施例中，该平坦化工艺是化学机械抛光(CMP)工艺。
之后，如图4D所示，根据本发明的一些实施例，在第一区10上的第一鳍结构110a上形成第一光刻胶(PR)层402。在第一区10和第二区20上沉积第一光刻胶层402，并且图案化第一光刻胶层402以在第一区10中形成图案化的第一光刻胶层402。图案化的第一光刻胶层402用于保护下面的层。
之后，对第二鳍结构110b实施第一离子注入工艺15以在第二鳍结构110b的顶部中形成第二APT区220。在一些实施例中，在第二区20中形成n型FinFET器件结构，将诸如硼(B)或氟化硼(BF2)的p型掺杂剂掺杂至第二鳍结构110b内。
如图4E所示，根据本发明的一些实施例，在形成第二APT区220之后，在第一鳍结构110a和第二APT区220上形成硬掩模层404。之后，在硬掩模层404上形成并且图案化第二光刻胶层406以形成图案化的第二光刻胶层406。
如图4F所示，根据本发明的一些实施例，在形成图案化的第二光刻胶层406之后，通过将图案化的第二光刻胶层406用作掩模来图案化硬掩模层404。
之后，去除第一鳍结构110a的顶部以在隔离结构114中形成凹槽115。此外，去除衬垫层112的顶部。因此，隔离结构114暴露在凹槽115中。凹槽115具有第二深度D2。在一些实施例中，第二深度D2在从约40nm到约70nm的范围内。
如图4G所示，根据一些实施例，在蚀刻工艺之后，对第一区10实施第二离子注入工艺17以在第一鳍结构110a中形成第一APT区120。在一些实施例中，在第一区10中形成p型FinFET器件结构，将诸如砷(As)、磷(P)或锑(Sb)的n型掺杂剂掺杂到第一鳍结构110a内。
如图4H所示，根据一些实施例，在形成第一APT区120之后，在APT区120上形成阻挡层122。阻挡层122用于阻挡APT区120扩散到沟道区(之后形成)内。阻挡层122具有凸形结构，凸形结构具有高于外围部分122p的中间部分122m。阻挡层122包括碳化硅(SiC)、碳化硅锗(SiGeC)或它们的组合。
如图4I所示，根据一些实施例，在形成阻挡层122之后，在阻挡层122上形成外延层124。当在第一区10中形成p型FinFET器件结构时，外延层124用作应变层。外延层124包括硅锗(SiGe)、锗(Ge)或它们的组合。通过外延工艺中形成外延层124。
在一些实施例中，在相同腔室中原位形成阻挡层122和外延层124而不被运到另一个腔室。此外，减少了制造操作和成本。
如图4J所示，根据一些实施例，在形成外延层124之后，对外延层124实施平坦化工艺以使外延层124的顶面与隔离结构114的顶面平齐。在一些实施例中，平坦化工艺是化学机械抛光(CMP)工艺。
如图4K所示，根据一些实施例，在平坦化工艺之后，去除隔离结构114的一部分以暴露外延层124和阻挡层122。通过诸如干蚀刻工艺或湿蚀刻工艺的蚀刻工艺去除介电层114的部分。
如图4L所示，根据一些实施例，在去除隔离结构114的部分之后，在第一鳍结构110a和第二鳍结构110b上形成栅极介电层208。之后，在栅极介电层208上形成栅电极210。
应当注意的是，外延层124的一部分用作沟道区。阻挡层122被配置为阻挡APT区120的扩散。由于通过在APT区120和外延层124之间形成阻挡层120而阻挡了APT区120的扩散，因此改进了沟道区的迁移率。因此，提高了鳍式场效应晶体管(FinFET)器件结构200的性能。此外，阻挡层120具有特定的凸形形状，并且因此鳍高度H3不减小。
提供了形成鳍式场效应晶体管(FinFET)器件结构的实施例，在衬底上形成鳍结构。在鳍结构中形成抗穿通注入(APT)区，并且在APT区上形成阻挡层。在阻挡层上形成外延层，外延层的一部分用作沟道区。阻挡层形成在APT区和沟道区之间以减缓或阻挡APT区的掺杂剂的扩散。因此，改进了沟道区的迁移率，并且进一步改进了FinFET器件结构的性能。
在一些实施例中，提供了一种鳍式场效应晶体管(FinFET)器件结构。FinFET器件结构包括衬底和从衬底延伸的鳍结构。FinFET器件结构也包括形成在鳍结构中的抗穿通注入(APT)区和形成在APT区上的阻挡层。阻挡层具有中间部分和外围部分，并且中间部分高于外围部分。FinFET器件结构还包括形成在阻挡层上的外延层。
在一些实施例中，提供了一种鳍式场效应晶体管(FinFET)器件结构。FinFET器件结构包括衬底和形成在衬底上的第一鳍结构和第二鳍结构。FinFET器件结构还包括形成在第一鳍结构中的第一抗穿通注入(APT)区和形成在第一APT区上的阻挡层。阻挡层具有凸形结构。FinFET器件结构还包括形成在阻挡层上的外延层和形成在第二鳍结构中的第二APT区。
在一些实施例中，提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法。该方法包括：提供衬底和在衬底上形成鳍结构。该方法也包括在鳍结构中形成抗穿通注入(APT)区和在APT区上形成阻挡层。阻挡层具有中间部分和外围部分，并且中间部分高于外围部分。该方法也包括在阻挡层上形成外延层。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种鳍式场效应晶体管(FinFET)器件结构，包括：
衬底；
鳍结构，从所述衬底延伸；
抗穿通注入(APT)区，形成在所述鳍结构中；
阻挡层，形成在所述抗穿通注入区上，其中，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分，所述外围部分顶面最低处与所述抗穿通注入区的上表面处于相同的高度；以及
外延层，形成在所述阻挡层上。
2.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述阻挡层具有凸形结构。
3.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述阻挡层包括碳化硅(SiC)或碳化硅锗(SiGeC)。
4.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述阻挡层是沿着(111)面外延生长的。
5.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，还包括：
隔离结构，形成在所述衬底上，其中，所述鳍结构嵌入在所述隔离结构中，并且所述抗穿通注入区位于所述隔离结构的顶面下方。
6.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，还包括：
衬垫，形成在所述鳍结构的侧壁上。
7.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述外延层包括硅锗(SiGe)、锗(Ge)或它们的组合。
8.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述中间部分具有位于所述抗穿通注入区的顶面上方的突起高度，并且所述突起高度在从5nm至10nm的范围内。
9.一种鳍式场效应晶体管(FinFET)器件结构，包括：
衬底；
第一鳍结构和第二鳍结构，形成在所述衬底上；
第一抗穿通注入(APT)区，形成在所述第一鳍结构中；
阻挡层，形成在所述第一抗穿通注入区上，其中，所述阻挡层具有凸形结构，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分，所述外围部分顶面最低处与所述第一抗穿通注入区的上表面处于相同的高度；和
外延层，形成在所述阻挡层上；以及
第二抗穿通注入区，形成在所述第二鳍结构中。
10.根据权利要求9所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述第一鳍结构配置为形成p型FinFET，并且所述第二鳍结构配置为形成n型FinFET。
11.根据权利要求9所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述外延层包括硅锗(SiGe)、锗(Ge)或它们的组合。
12.根据权利要求9所述的鳍式场效应晶体管(FinFET)器件结构，还包括：
隔离结构，形成在所述衬底上，其中，所述第一鳍结构嵌入在所述隔离结构中，并且所述第一抗穿通注入区位于所述隔离结构的顶面下方。
13.根据权利要求12所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述第二抗穿通注入区高于所述隔离结构的顶面。
14.根据权利要求9所述的鳍式场效应晶体管(FinFET)器件结构，其中，所述阻挡层是沿着(111)面外延生长的。
15.根据权利要求9所述的鳍式场效应晶体管(FinFET)器件结构，还包括：
栅极介电层，形成在所述外延层上；以及
栅电极层，形成在所述栅极介电层上。
16.一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法，包括：
提供衬底；
在所述衬底上形成鳍结构；
在所述鳍结构中形成抗穿通注入(APT)区；
在所述抗穿通注入区上形成阻挡层，其中，所述阻挡层具有中间部分和外围部分，并且所述中间部分高于所述外围部分，所述外围部分顶面最低处与所述抗穿通注入区的上表面处于相同的高度；以及
在所述阻挡层上形成外延层。
17.根据权利要求16所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，在所述抗穿通注入区上形成所述阻挡层包括在所述抗穿通注入区上实施外延工艺。
18.根据权利要求17所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，在腔室中原位实施形成所述阻挡层和形成所述外延层。
19.根据权利要求16所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，还包括：
在所述外延层上形成栅极介电层；以及
在所述栅极介电层上形成栅电极层。
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