TW201620041A - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TW201620041A
TW201620041A TW104111746A TW104111746A TW201620041A TW 201620041 A TW201620041 A TW 201620041A TW 104111746 A TW104111746 A TW 104111746A TW 104111746 A TW104111746 A TW 104111746A TW 201620041 A TW201620041 A TW 201620041A
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layer
gate
growth control
semiconductor device
trench
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TW104111746A
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TWI550719B (zh
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張簡旭珂
吳志楠
林俊澤
徐辜文正
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台灣積體電路製造股份有限公司
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Abstract

本發明提供用於半導體裝置之改良的導電結構，以及其形成技術。在一實施例中，半導體裝置包含基板與形成其上的閘極結構。閘極結構包含閘極介電層於基板上、成長控制材料位於閘極結構之側壁表面上、以及閘極填充材料位於成長控制材料上。閘極填充材料亦位於閘極結構之下表面上，且下表面不具有任何成長控制材料。在某些實施例中，閘極填充材料接觸的第一表面與第二表面之材料組成不同。

Description

半導體裝置與其形成方法
本發明係關於IC裝置製程，更特別關於形成導電結構如裝置閘極、接點、與通孔。
半導體產業朝向奈米技術的製程節點邁進，以達更高的裝置密度、更高的效能、與更低的成本。除非材料與製程有開創性的進展，平面的裝置如習知的MOSFET已面臨挑戰。在某些實例中，沉積技術、蝕刻技術、與其他製程中採用的液體、氣體、或電漿在分佈較鬆散的結構中可運作良好，且結構可順利接觸製程中的反應物。然而細窄的高深寬比溝槽與空洞會限制反應物進入溝槽的量，造成溝槽中不均勻的沉積或蝕刻。
為了改善本技術領域，電路設計朝向新結構發展以改善效能。其中一種發展為3D設計如鰭狀場效電晶體(FinFET)。FinFET可視作習知平面裝置自基板朝閘極凸出。一般的FinFET之薄鰭狀物(或鰭狀結構)自基板朝上延伸。FET之通道係形成於垂直的鰭狀物中，而閘極係位於鰭狀物之通道區上並包圍通道區。由於閘極包圍鰭狀物，可增加通道區與閘極的接觸面積，使閘極可由不同側控制通道區。這有許多操作方法，且某些情況下的FinFET具有較小的短通道效應、較少漏電 流、與較高的電流。換言之，FinFET比平面裝置快、小、且更有效率。
然而FinFET與其他非平面裝置具有更複雜的形狀，且具有更高深寬比的溝槽待填充。綜上所述，習知製程的技術僅能適用於某些製程，而不適用於其他製程。為了達到日益增加的設計需求，需要改善裝置製程與其他領域。本發明提供的方法除了可改良平面裝置外，還可改良FinFET與其他非平面裝置。
本發明一實施例提供之半導體裝置的形成方法，包括：接收基板，其中基板具有閘極結構於其上，且閘極結構包括犧牲部份；移除犧牲部份以定義溝槽於閘極結構中，其中溝槽具有相對的側壁表面與下表面；選擇性地形成材料層於相對的側壁表面上，其中下表面不具有材料層；以及沉積閘極的填充材料於溝槽中的材料層與下表面上。
本發明一實施例提供之半導體裝置的形成方法，包括：接收基板，其具有凹陷定義於其中，且凹陷具有至少兩個相對的側壁表面與下表面；沉積成長控制材料於凹陷中的相對的側壁表面上，且下表面不具有成長控制材料；以及沉積填充材料層於凹陷中，使填充材料層位於成長控制材料與下表面上。
本發明一實施例提供之半導體裝置，包括：基板，具有閘極結構形成其上，其中閘極結構包括：閘極介電層，位於基板上；成長控制材料，位於閘極結構之側壁表面上；以及 閘極填充材料位於成長控制材料上與閘極結構的下表面上，且下表面不具有成長控制材料。
100、200、2900‧‧‧半導體裝置
102‧‧‧基板
104、208‧‧‧源極/汲極區
106、212‧‧‧閘極結構
108、214‧‧‧界面層
110、216‧‧‧閘極介電層
112、218‧‧‧蓋層
114、220‧‧‧閘極
116、222‧‧‧側壁間隔物
118‧‧‧導電線路
120‧‧‧層間介電層
122‧‧‧通孔
124‧‧‧接點
202、204‧‧‧剖面
206‧‧‧鰭狀結構
210‧‧‧通道區
300、2000‧‧‧方法
302、304、306、308、310、312、314、316、318、320、2002、2004、2006、2008、2010、2012、2014、2016‧‧‧步驟
402‧‧‧犧牲閘極
404‧‧‧溝槽
406‧‧‧功函數層
408‧‧‧濕潤層
410‧‧‧阻障層
412、2402‧‧‧成長控制層
414‧‧‧溝槽側壁表面
416‧‧‧溝槽底部
418、2502‧‧‧填充材料
2102‧‧‧圖案化之層狀物
2202‧‧‧凹陷
2302‧‧‧黏著層
2404‧‧‧側壁表面
2406‧‧‧下表面
第1圖係本發明實施例中，半導體裝置的剖視圖。
第2A圖係本發明實施例中，非平面之半導體裝置的透視圖。
第2B圖係本發明實施例中，穿過非平面之半導體裝置之通道區的剖視圖。
第2C圖係本發明實施例中，穿過非平面之半導體裝置之源極/汲極區的剖視圖。
第3圖係本發明實施例中，形成閘極之方法流程圖。
第4-8、9A-9B、10-11圖係本發明實施例中，以形成閘極之方法形成的非平面裝置的部份剖視圖。
第12-16、17A-17B、18-19圖係本發明實施例中，以形成閘極之方法形成的平面裝置的部份剖視圖。
第20圖係本發明實施例中，形成接點/通孔的方法流程圖。
第21-23、24A-24B、25、26A-26B圖係本發明實施例中，以形成接點之方法形成的平面裝置的部份剖視圖。
第27A與27B圖係本發明實施例中，以形成接點之方法形成的非平面裝置之源極/汲極區的剖視圖。
第28A與28B圖係本發明實施例中，以形成接點之方法形成的非平面裝置之通道區的剖視圖。
第29A與29B圖係本發明實施例中，以形成通孔之方法形 成之半導體裝置的剖視圖。
可以理解的是，下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。另一方面，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。舉例來說，若圖式中的裝置翻轉，則「下方」的元件轉為「上方」的元件。如此一來，「下方」應包含「上方」或「下方」。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
下述製程形成的導電結構，可改良高深寬比的溝槽之間隙填充率。此技術可減少甚至消除其他沉積技術可能產生的頸狀物、孔洞、與不連續，且可應用於形成裝置閘極、接點、通孔、與其他結構。在上下文中，第1與2A至2C圖顯示平面與非平面的半導體裝置，其某些結構可之形成方法可採用本發明的製程。然而這些結構僅用以舉例，本發明之技術可用於形成任何裝置中的任何合適結構。
第1圖係本發明實施例之半導體裝置100的剖視圖。第1圖已簡化，以清楚說明本發明概念。半導體裝置100為一般的平面MOSFET，其可為N型金氧半電晶體裝置(NMOS裝置)或P型金氧半電晶體裝置(PMOS裝置)。半導體裝置100係形成於基板102如基體矽基板上。在其他實施例中，基板102可包含半導體元素(單一元素)如結晶態的矽或鍺；半導體化合物如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；及/或上述之組合。基板102亦可包含絕緣層上矽(SOI)基板。SOI基板的製作方法採用佈植氧隔離(SIMOX)、晶圓接合、及/或其他合適方法。在其他實例中，基板102可包含多層的半導體結構。
基板102可包含多種掺雜區(如p型井區或n型井區)，比圖示的源極/汲極區104。掺雜區可掺有p型掺質如磷或砷，及/或n型掺質如硼或BF2，端視設計需求。掺雜區可直接形成於基板上、形成於P型井結構中、形成於N型井結構中、形成於雙井結構中、或採用隆起結構。掺雜區之形成方法可為佈植掺質原子、磊晶成長的臨場掺雜、及/或其他合適技術。在某些實施例中，掺雜區包含環形/袋狀區以降低短通道效應(如擊穿效應)，且可由斜向離子佈植或其他合適技術形成。
半導體裝置100可包含閘極結構106，其位於源極/汲極區104之間的基板102上。藉由施加至閘極結構106之電壓，可控制穿過源極/汲極區104之間的通道區之載子流(n型通道裝置之電子流或p型通道裝置的電洞流)。合適的閘極結構106包含多晶矽與金屬閘極。在閘極優先的實施例中，閘極結 構106為功能閘極。相反地，在閘極後製的實施例中，閘極結構106可為功能閘極或犧牲(虛置閘極)。在閘極後置的製程中，移除部份的犧牲閘極，並取代以功能閘極材料(如金屬)，即形成功能閘極結構106。閘極結構106可包含多層層狀物。在此實施例中，閘極結構106包含界面層108、閘極介電層110、蓋層112、與閘極114。在某些實施例中，側壁間隔物116係形成於閘極結構的一或多個橫向表面上。
為了進一步詳述此結構，界面層108係位於基板102上，且可包含界面材料如氧化矽、氮化矽、氮氧化矽、其他半導體氧化物、其他合適的界面材料、及/或上述之組合。界面層108可採用任何合適技術如原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿CVD(HDP-CVD)、物理氣相沉積(PVD)、旋轉塗佈沉積、及/或其他合適沉積製程形成，以具有任何合適厚度。
閘極介電層110係位於界面層108上，且可包含一或多種介電材料，其介電性質通常以氧化矽之介電常數作基準。舉例來說，閘極介電層110可包含高介電常數之介電材料如氧化鉿、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、其他合適的高介電常數之介電材料、及/或上述之組合。此外，其他實施例之閘極介電層110可包含其他介電物如氧化矽、氮化矽、氮氧化矽、碳化矽、非晶碳、四乙氧基矽烷(TEOS)、其他合適的介電材料、及/或上述之組合。閘極介電層110可採用任何合適技術如ALD、CVD、HDP-CVD、PVD、旋轉塗佈沉積、及/或 其他合適沉積製程形成，以具有任何合適厚度。
閘極結構106可包含蓋層112於閘極介電層110上。蓋層112可包含氧化矽、氮化矽、氮氧化矽、其他半導體氧化物、其他半導體氮化物、其他合適材料、及/或上述之組合。
閘極114可位於閘極介電層110與蓋層112上。除了習知的名稱如MOSFET外，半導體裝置100之閘極114可包含含多晶矽閘極或含金屬閘極114。閘極114可包含多層結構，其包含一或多層的黏著層、濕潤層、襯墊層、與金屬填充層。綜上所述，閘極114可包含任何合適材料如多晶矽、鋁、銅、鈦、鉭、鎢、鉬、氮化鉭、鎳矽化物、鈷矽化物、氮化鈦、氮化鎢、鈦鋁合金、氮化鈦鋁、氮化鉭碳、碳化鉭、氮化鉭矽、金屬合金、其他合適材料、及/或上述之組合。
某些實施例採用閘極後製製程，其閘極114包含犧牲(虛置)部份如多晶矽、介電層、遮罩層、及/或其他合適材料。在此實施例中，犧牲部份可完全或部份移除，其移除方法可為合適的濕式及/或乾式蝕刻製程。接著以另一閘極取代移除的犧牲部份，形成含金屬的閘極114。在下文中將進一步詳述本發明之沉積技術，其適於在移除犧牲閘極部份後形成的凹陷中形成金屬閘極，即使凹陷具有習知沉積技術難以處理的高深寬比(深度與寬度的比例)。
在某些實施例中，側壁間隔物116係形成於閘極結構106的每一側(閘極結構106之側壁)上。側壁間隔物116可用以對準源極/汲極區104，並提供剛性表面以避免溝槽崩塌於閘極 置換製程中。側壁間隔物116可包含任何合適的介電材料如半導體氧化物、半導體氮化物、半導體碳化物、半導體氮氧化物、其他合適材料、及/或上述之組合。
為了將半導體裝置100整合至電路中，可形成內連線結構於半導體裝置100上。在此實施例中，內連線結構包括多個導電線路118夾設於多個層間介電層120中。層間介電層120可包含任何合適的介電材料如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、TEOS氧化物、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(PBSG)、氟化氧化矽玻璃(FSG)、掺雜碳之氧化矽、Black Diamond®、乾凝膠、氣膠、非晶氟化碳、聚對二甲苯、雙苯環丁烯(BCB)、SiLK(購自Dow Chemical,Midland,Michigan)、聚醯亞胺、其他合適材料、及/或上述之組合。層間介電層120作為絕緣物，可支撐及隔離導電線路118。通孔122延伸穿過層間介電層120，以連接不同水平位置的導電線路118。接點124延伸穿過層間介電層120，以連接至源極/汲極區104、閘極結構106、與靠近基板120或位於基板102中的其他結構。如下述內容所示，本發明的技術適於形成接點124與通孔122。這些接點124、通孔122、與前述之閘極114僅為裝置結構的某些實施例，且可用本發明之技術形成。
第1圖特別說明平面裝置之結構可採用本發明之技術形成，而第2A至2C圖亦顯示非平面裝置之結構可由本發明之技術形成。第2A圖係本發明實施例中，非平面的半導體裝置200之透視圖。第2B圖係本發明實施例中，穿過半導體裝置200之通道區(如剖面202)的部份剖視圖。第2C圖係本發明實施 例中，穿過半導體裝置200(如剖面204)的部份剖視圖。第2A至2C圖已簡化，以利說明本發明概念。
如第2A至2C圖所示，半導體裝置200包含基板102(或晶圓)，其具有一或多個鰭狀結構206形成其上。鰭狀結構206可為任何隆起結構，此實施例包含FinFET之鰭狀結構，而其他實施例包含形成於基板102上之其他隆起的主動或被動裝置。鰭狀結構206各自包含一對相對的源極/汲極區208，其可包含多種掺雜的半導體材料；以及位於源極/汲極區208之間的通道區210。藉由施加電壓至包覆通道區210並與其相鄰的閘極結構212，可控制通道區210之間的載子流。閘極結構212之一者為半透明，以利顯示其下之通道區210。在此實施例中，通道區210自形成其上的基板102之平面上隆起，且鰭狀結構206可稱作非平面裝置。與平面裝置相較，隆起的通道區210與相鄰的閘極結構212之間具有較大的表面積，可強化閘極結構212與通道區210之間的電磁場作用，進而降低較小裝置之漏電流與短通道效應。在許多實施例中，FinFET與其他非平面裝置在較小腳距的設計中，比平面的對應裝置效能更佳。
半導體裝置200的元件將詳述於下。基板102可與第1圖所示之基板102實質上相同，且可包含任何合適的半導體及/或非半導體材料。舉例來說，基板102可包含一或多層的半導體元素如矽或鍺；半導體化合物如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；非半導體材料如鈉鈣玻璃、熔融氧化矽、熔融石英、或氟化鈣；其他合適材料；及/或上述之組合。
鰭狀結構206形成於基板102上的方法可為使基板102之周圍部份凹陷以保留鰭狀結構206，及/或沉積材料以成長鰭狀結構206於基板102上。形成閘極結構212以保護鰭狀結構之通道區210後，可將額外的半導體材料添加至鰭狀結構206之源極/汲極區208。在許多實施例中，額外材料係以一或多道磊晶製程沉積，使矽結構、矽鍺結構、及/或其他合適結構以結晶態成長於鰭狀結構206上。合適的磊晶製程包含CVD沉積技術如氣態磊晶(VPE)及/或超高真空CVD(UHV-CVD)、原子束磊晶、及/或其他合適製程。源極/汲極區208的材料可在磊晶製程中臨場掺雜p型掺質如硼或BF2、n型掺質如磷或砷、及/或其他合適掺質如上述之組合。若源極/汲極區208未採用臨場掺雜，則可進行佈植製程(如接面佈植製程)以掺雜源極/汲極區208。
閘極結構212係形成於一或多個鰭狀結構206之頂部上，且可包含界面層214、閘極介電層216、蓋層218、與閘極220包覆鰭狀結構206之通道區210與位於其上。上述的每一單元的組成，可與前述之平面裝置中對應的部份實質上相同。舉例來說，界面層214可包含氧化物、氧化鉿矽、氮化物、氮氧化物、及/或其他合適材料，且其沉積方法可為任何合適方法如熱氧化、ALD、CVD、臭氧氧化、或類似方法。閘極介電層216可包含任何合適介電物如高介電常數之介電材料(包含氧化鑭、氧化鋁、氧化鋯、氧化鈦、氧化鉭、氧化釔、氧化鍶鈦(STO)、氧化鋇鈦(BTO)、氧化鋇鋯、氧化鉿鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、氧化 (鋇,鍶)鈦(BST)、氧化鋁、氮化矽、氮氧化矽、及/或其他合適材料。蓋層218可包含氧化矽、氮化矽、氮氧化矽、其他半導體氧化物、其他半導體氮化物、其他合適材料、及/或上述之組合。
閘極220係位於閘極介電層216與蓋層218上。在多種實施例中，閘極220包含多晶矽、金屬、金屬合金、金屬化合物、及/或非金屬導體。合適金屬包括鎢、鋁、銅、鈦、銀、氮化鈦鋁、碳化鉭、氮化鉭碳、氮化鉭矽、錳、鋯、氮化鈦、氮化鉭、釕、鉬、氮化鎢、及/或其他合適材料。在某些實施例中，nMOS裝置與pMOS裝置可採用不同的閘極材料。閘極220可具有多層結構，其包含一或多層的黏著層、濕潤層、襯墊層、與金屬填充層。在平面裝置中，本發明的技術可用以形成閘極220，其可作為閘極置換製程或其他閘極形成技術的一部份。
閘極結構212亦可包含一或多個側壁間隔物222，如圖示的兩個。適用於側壁間隔物222的材料包含介電物如半導體氧化物、半導體氮化物、半導體氮氧化物、半導體碳化物、及/或其他介電物。在某些實施例中，側壁間隔物222包含交錯的不同介電物，比如第一半導體氧化物的間隔層與第二半導體氮化物的間隔層。上述側壁間隔物222的形成方法可為CVD、PVD、ALD、及/或其他合適沉積技術。
與平面裝置類似，位於基板102與閘極結構212上的內連線結構包含數個導電線路118夾設於多個層間介電層120中。為了清楚說明，內連線結構並未繪示於第2A圖中，以避免造成其他結構不清楚。如第1圖所示之平面裝置，本發明 的技術適於形成非平面的半導體裝置200之內連線結構中的接點124與通孔122。
如第3至11圖所示，本發明之技術可用以形成閘極。第3圖係本發明之實施例中，用以形成閘極之方法300的流程圖。可以理解的是在方法300之前、之中、或之後可進行額外步驟，且其他實施例中方法300的某些步驟可省略或取代為其他步驟。第4至11圖係本發明實施例中，以方法300形成部份非平面裝置200之閘極的剖視圖。至於以方法300形成平面裝置的實施例，將搭配更後面的圖式說明。
如第3圖之步驟302與第4圖所示，接收的基板102具有半導體裝置200。基板102與半導體裝置200可與第2A至2C圖中的對應元件實質上相同，在此不贅述相同的部份。在第4圖之實施例中，半導體裝置200包含部份的閘極結構212，其與第2A圖中對應的元件實質上相同。閘極結構包含犧牲閘極402，其可包含多晶矽、介電物、遮罩材料、及/或其他合適材料。如第3圖之步驟304與第5圖所示，移除犧牲閘極402以保留由側壁間隔物222定義的溝槽404。由於溝槽404形狀的關係，在溝槽404中形成層狀物面臨挑戰。舉例來說，溝槽404具有高深寬比及/或窄內部空洞，而沉積的反應物無法有效流動其中。
閘極結構212的閘極介電層216可在移除犧牲閘極402之前或之後形成。如3圖之步驟306與第6圖所示，在移除犧牲閘極402之後，形成介電層216形成於溝槽404中。在此實施例中，閘極介電層216係形成於溝槽404中的界面層214上，亦可沿著側壁間隔物222之垂直表面延伸，使垂直表面上的部份 閘極介電層216延伸至界面層214上的閘極介電層216上，即形成U型結構。在某些實施例中，高順應性的沉積製程如CVD或ALD可用以沉積U型的閘極介電層216，雖然非順應性的沉積製程亦可用於類似目的。在這些實施例中，合適的沉積製程包括CVD、HDP-CVD、ALD、PVD、旋轉塗佈沉積、及/或其他合適沉積技術。閘極介電層216之組成可與第1至2C圖之對應元件類似。
在移除犧牲閘極層402之前或之後，亦可形成閘極結構212的功函數層406。如第3圖之步驟308與第6圖所示，在移除犧牲閘極層402後，形成功函數層406於溝槽404中的閘極介電層216上。功函數層406可調整最後形成之半導體裝置的臨界電壓，其材質需對應半導體裝置200的型態：p型的裝置需採用p型功函數材料，而n型的裝置需採用n型功函數材料。舉例來說，p型功函數金屬包含氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢、鋯矽化物、鉬矽化物、鉭矽化物、鎳矽化物、氮化鎢、其他合適的p型功函數材料、及/或上述之組合。舉例來說，n型功函數金屬包含鈦、銀、鉭鋁、碳化鉭鋁、氮化鈦鋁、碳化鉭、氮化鉭碳、氮化鉭矽、錳、鋯、其他合適的n型功函數材料、及/或上述之組合。功函數層406可包含多個層狀物，其沉積方法可為CVD、PVD、及/或其他合適製程以達任何合適厚度。在此實施例中，功函數層406沿著閘極介電層216的垂直表面形成，以形成U型結構。
如第3圖之步驟310與第7圖所示，濕潤層408可沉積於閘極介電層216及/或功函數層406上。濕潤層408可改善層 狀物之間的接合，以及後續沉積之層狀物的平整性。在多種實施例中，濕潤層408包含鈦、鉭、鎳、鈷、其他金屬、及/或上述之組合。形成濕潤層408於溝槽404中的方法可為任何合適的沉積技術，比如ALD、CVD、及/或濺鍍以達任何合適厚度。
如第3圖之步驟310與第8圖所示，阻障層410可沉積於濕潤層408上。阻障層410可用以避免後續沉積製程劣化半導體裝置200的其他層狀物。舉例來說，某些金屬在沉積時(甚至在製程完成後)傾向於擴散至含矽層。綜上所述，阻障層410可包含氮化鈦、氮化鉭、及/或其他合適金屬、金屬氧化物、及/或金屬氮化物。阻障層410與濕潤層408類似，其沉積於溝槽404中的方法可為任何合適製程如ALD、CVD、及/或濺鍍以達任何合適厚度。在某些實施例中，單一沉積步驟沉積之金屬可同時作為濕潤層408與阻障層410。接著可對阻障層410進行氧化或氮化，或進行其他製程以形成氧化物、氮化物、及/或其他金屬化合物於阻障層410中。
當溝槽404的深寬比較大時，填充材料可直接沉積於阻障層410上，不過順應性的沉積製程在靠近溝槽404頂部的沉積速率較快。這會使材料在溝槽404的最頂部快速相接，並保留孔洞於溝槽404的底部。孔洞問題在溝槽深寬比大於或等於10：1(深度：寬度)時特別明顯，但在低深寬比的溝槽中依然可見。綜上所述，某些實施例在相對的溝槽側壁表面414上形成成長控制層412，但不需在溝槽底部416形成成長控制層412。上述步驟如第3圖之步驟314與第9A及9B圖所示。成長控制層412影響後續沉積填充材料的沉積速率。在一實施例中，成長 控制層12使溝槽側壁表面414的沉積速率低於溝槽底部416的沉積速率，因此後續順應性的沉積技術，其溝槽404的底部填充速率比溝槽404的頂部填充速率快。換言之，填充控制層412使ALD、CVD、濺鍍、及/或其他順應性沉積製程，自溝槽404之底部往上填充。
成長控制層412可包含任何合適金屬、金屬氧化物、金屬碳化物、金屬氮化物、及/或上述之組合，且可與阻障層410的組成不同。在多種實施例中，成長控制層412包含碳化鎢、氮化鎢、碳化鋁、氮化鋁、及/或其他合適材料。在某些實施例中，成長控制層412的一或多種金屬組成選擇，需搭配後續沉積的填充材料418的金屬組成。在這些實施例中，若填充材料418為含鎢材料，則成長控制層412可採用碳化鎢或氮化鎢。在其他實施例中，若填充材料418為含鋁材料，則成長控制層412可採用碳化鋁或氮化鋁。
成長控制層412可沉積至任何厚度(垂直於溝槽側壁表面414的厚度)，然而成長控制層412之材料導電性較低，因此其厚度較薄(比如介於約1Å至約20Å之間)。成長控制層412至少沿著溝槽側壁表面414的上側部份延伸至溝槽底部416，如第9B圖所示。成長控制層412定義之溝槽側壁表面414的組成，將不同於溝槽底部416之組成。上述差異可用以調整後續的沉積製程。
任何合適的順應性或非順應性沉積均可用以形成成長控制層412。在多種實施例中，ALD、CVD、濺鍍、及/或其他合適技術可用以形成成長控制層412於溝槽側壁表面414 上。在一實施例中，成長控制層412的金屬組成係由ALD沉積，接著以含氮及/或含碳之電漿處理，以形成金屬氮化物及/或金屬碳化物。某些實施例中的沉積技術為順應性沉積，因此溝槽404的形狀會阻止沉積的反應物到達溝槽404的底部。如此一來，成長控制層412之順應性沉積在溝槽側壁表面414的沉積速率會比在溝槽底部416的沉積速率快，難以填充溝槽底部416的缺點反而變成優點。在沉積後可進行非等向蝕刻製程，自溝槽404之溝槽底部416移除任何沉積的材料。舉例來說，一實施例以濺鍍法沉積成長控制層412後，接著進行非等向乾蝕刻以移除溝槽底部416上的沉積材料。
如第3圖之步驟316與第10及11圖所示，可沉積閘極220之填充材料418至溝槽404中與成長控制層412上。第10圖對應第9A圖之實施例，其成長控制層412未延伸至溝槽底部416。第11圖對應第9B圖之實施例，其成長控制層412延伸至溝槽底部416。填充材料418可包含任何合適的導電物如鎢、鋁、銅、鈦、銀、釕、鉬、其他合適金屬、或上述之合金。填充材料418之形成方法可為任何合適技術，比如ALD、CVD、及/或濺鍍。由於成長控制層412的存在，填充材料418在溝槽404之溝槽底部416的沉積速率，比在溝槽側壁表面414的沉積速率快。在特定實施例中，金屬碳化物組成的成長控制層412可讓溝槽側壁表面414的沉積速率下降10倍。經由實驗分析證明，以上述技術形成之高深寬比的溝槽404中的填充材料418，可大幅減少孔洞與其他缺陷。
如第3圖之步驟318所示，接著可進行平坦化技術 如化學機械研磨(CMP)於半導體裝置200上，以移除超出溝槽404的多餘材料。如第3圖之步驟320所示，可對半導體裝置200進行額外製程。
方法300亦可用於形成平面裝置中的閘極，如第3圖與第12至19圖所示。第12至19圖係本發明實施例中，以方法300形成之平面的半導體裝置100的部份剖視圖。
如第3圖之步驟302與第12圖所示，接收包含半導體裝置100的基板102。基板102與半導體裝置可與第1圖之對應元件實質上相同，為簡化說明將不再次贅述。在第12圖之實施例中，半導體裝置100包含之部份閘極結構116與第1圖之對應元件實質上相同，其包含犧牲閘極402。犧牲閘極402可包含多晶矽、介電物、遮罩材料、及/或其他合適材料。如第3圖之步驟304與第13圖所示，移除犧牲閘極402以保留側壁間隔物116所定義之溝槽404。由於溝槽404的形狀，形成層狀物於其中仍具有挑戰。舉例來說，溝槽404可能具有高深寬比及/或窄內部空洞，而沉積的反應物無法有效流動其中。
在移除犧牲閘極402之前或之後，可形成閘極介電層110。綜上所述，如第3圖之步驟306與第14圖所示，在移除犧牲閘極402後可形成閘極介電層110於溝槽404中。在此實施例中，閘極介電層110係形成於溝槽404中的界面層108上，且亦沿著側壁間隔物116之垂直表面延伸，以形成U形層狀物。閘極介電層110的合適沉積製程包含CVD、HDP-CVD、ALD、PVD、旋轉塗佈法、及/或其他合適沉積製程。閘極介電層110可與第1至2C圖中對應的元件相同。
在移除犧牲閘極402之前或之後，亦可形成功函數層406。以第3圖之步驟308及第14圖為例，在移除犧牲閘極402後可形成功函數層406於溝槽404中的閘極介電層110上。功函數層406可依半導體裝置100之特定型態調整其材料，且可與第4圖之功函數層406的組成相同。在此實施例中，功函數層406沿著閘極介電層110之垂直側壁延伸，以形成U型結構。功函數層406可包含多層結構，其沉積方法可為CVD、PVD、及/或其他合適製程以達任何合適厚度。
如第3圖之步驟310與第15圖所示，可沉積濕潤層408於閘極介電層110及/或功函數層406上。濕潤層408可包含鈦、鉭、鎳、鈷、其他金屬、及/或上述之組合，且其形成方法可為任何合適技術如ALD、CVD、或濺鍍。形成於溝槽404中的濕潤層408可採用任何合適沉積技術如ALD、CVD、及/或濺鍍以達任何合適厚度。
如第3圖之步驟312與第16圖所示，阻障層410可沉積於濕潤層408上。阻障層410可包含氮化鈦、氮化鉭、及/或其他合適金屬、金屬氧化物、及/或金屬氮化物，且其沉積方法可為任何合適技術如ALD、CVD、及/或濺鍍。在某些實施例中，單一沉積製程可用以沉積濕潤層408與阻障層410所用之共同的金屬。阻障層410的金屬可進一步進行氧化或氮化，或採用其他製程以形成氧化物、氮化物、及/或其他金屬化合物於阻障層410中。
如第3圖之步驟314與第17A及17B圖所示，成長控制層412係形成於溝槽側壁表面414上，但不必形成於溝槽底部 416上。成長控制層412影響後續沉積填充材料之技術的沉積速率。綜上所述，成長控制層412可包含任何合適金屬、金屬氧化物、金屬氮化物、及/或上述之組合。舉例來說，成長控制層412可包含碳化鎢、氮化鎢、碳化鋁、氮化鋁、及/或其他合適材料。在某些實施例中，成長控制層412的一或多個金屬組成需搭配後續沉積之填充材料418之金屬組成。
成長控制層412可沉積至任何厚度(垂直於溝槽側壁表面414的厚度)，然而成長控制層412之材料導電性較低，因此其厚度較薄(比如介於約1Å至約20Å之間)。成長控制層412至少沿著溝槽側壁表面414的上側部份延伸至溝槽底部416，如第17B圖所示。成長控制層412定義之溝槽側壁表面414的組成，將不同於溝槽底部416之組成。上述差異可用以調整後續的沉積製程。
任何合適的順應性或非順應性沉積均可用以形成成長控制層412。在多種實施例中，ALD、CVD、濺鍍、及/或其他合適技術可用以形成成長控制層412於溝槽側壁表面414上。在一實施例中，成長控制層412的金屬組成係由ALD沉積，接著以含氮及/或含碳之電漿處理，以形成金屬氮化物及/或金屬碳化物。某些實施例中的沉積技術為順應性沉積，因此溝槽404的形狀會阻止沉積的反應物到達溝槽404的底部。在沉積後可進行非等向蝕刻製程，自溝槽404之溝槽底部416移除任何沉積的材料。舉例來說，一實施例以濺鍍法沉積成長控制層412後，接著進行非等向乾蝕刻以移除溝槽底部416上的沉積材料。
如第3圖之步驟316與第18及19圖所示，可沉積閘 極220之填充材料418至溝槽404中與成長控制層412上。第18圖對應第17A圖之實施例，其成長控制層412未延伸至溝槽底部416。第19圖對應第17B圖之實施例，其成長控制層412延伸至溝槽底部416。填充材料418可包含任何合適的導電物如鎢、鋁、銅、鈦、銀、釕、鉬、其他合適金屬、或上述之合金。填充材料418之形成方法可為任何合適技術，比如ALD、CVD、及/或濺鍍。由於成長控制層412的存在，填充材料418在溝槽404之溝槽底部416的沉積速率，比在溝槽側壁表面414的沉積速率快。本發明已確認上述技術形成之高深寬比的溝槽404中的填充材料418，可大幅減少孔洞與其他缺陷。
如第3圖之步驟318所示，接著可進行平坦化技術如化學機械研磨(CMP)於半導體裝置100上，以移除超出溝槽404的多餘材料。如第3圖之步驟320所示，可對半導體裝置100進行額外製程。
本發明的上述技術亦可用以形成接點與通孔，如第20至29B圖所示。第20圖係本發明實施例中，形成接點/通孔的方法2000之流程圖。可以理解的是，在方法2000之前、之中、或之後可進行額外製程，且其他實施例之方法2000中的某些步驟可省略或取代為其他步驟。第21至26圖係本發明實施例中，以方法2000形成接點/通孔之半導體裝置100的部份剖視圖。第27A與27B圖係本發明實施例中，以方法2000形成之非平面的半導體裝置200其源極/汲極區的剖視圖。第28A與28B圖係本發明實施例中，以方法2000形成之非平面的半導體裝置200其通道區的剖視圖。第29A與29B圖係本發明實施例中，以方法2000 形成之半導體裝置2900的剖視圖。
如第20圖之步驟2002與第21圖所示，接收包含半導體裝置100之基板102。基板102與半導體裝置可與第1圖之對應元件實質上相同，為簡化說明將不再次贅述。在此實施例中，半導體裝置100包含一或多層的層間介電層120於源極/汲極區104與閘極結構116上。如第20圖之步驟2004與第21圖所示，圖案化之層狀物2102如光阻層係形成於層間介電層120上，並露出接點/通孔區。在第21圖的實施例中，露出的接點/通孔區對應接點區。圖案化的層狀物2102之圖案化方式可為直寫、光微影、及/或其他合適製程。在一實施例中，圖案化之層狀物2102所選定的區域照射光微影的射線，導致圖案化之層狀物2102中的光敏化學品進行化學反應。接著進行顯影製程，其製程條件端視化學反應的結果而定，以選擇性地移除圖案化之層狀物的曝光區或非曝光區。
接著如第20圖之步驟2006與第22圖所示，以圖案化之層狀物2102作遮罩，選擇性地蝕刻層間介電層120以定義第22圖所示之接點的凹陷2202。蝕刻層間介電層120的方法可為任何合適的蝕刻技術如濕蝕刻、乾蝕刻、反應性離子蝕刻(RIE)、或類似方法、採用任何合適的蝕刻化學品、或上述之組合。在一實施例中，步驟2006之蝕刻包含第一蝕刻如方向性(或非等向)的蝕刻技術以形成垂直凹陷，以及第二蝕刻如非方向性(或等向)的蝕刻技術以增加凹陷寬度。在蝕刻層間介電層120後，可移除剩餘的圖案化之層狀物2102。
如第20圖之步驟2008與第23圖所示，黏著層2302 係形成於層間介電層上並位於圖案化之層狀物2102其被蝕刻的部份中。黏著層2302如其名，可用以改善現有的材料(如層間介電層120、源極/汲極區104、與閘極結構116)與後續沉積的材料(如接點/通孔之填充材料)的界面品質。綜上所述，黏著層2302可包含一或多層導電材料如金屬(比如鈦、鉭、鎢、鋁、鎳、銅、鈷、或類似物)或金屬氮化物，其沉積方法可為ALD、CVD、PECVD、PEALD、PVD、及/或其他合適沉積製程。在此實施例中，黏著層2302包含鈦與氮化鈦的多層沉積層。在其他實施例中，可添加一或多個額外層如阻障層。
當接點124的形成方法係直接沉積填充材料至黏著層2302上時，接點/通孔的凹陷之深寬比必然變大，孔洞與不連續的問題與前述金屬閘極填充製程一樣。綜上所述，如第20圖之步驟2010與第24A及24B圖所示，某些實施例之成長控制層2402係形成於凹陷的側壁表面2404上，但不必形成於下表面2406上。成長控制層2402可覆蓋側壁表面2404最頂端的部份，如第24A圖所示。成長控制層2402亦可延伸至下表面2406，如第24B圖所示。成長控制層2402影響後續沉積填充材料之製程的沉積速率，並降低其於凹陷之側壁表面2404的沉積速率，使順應性的沉積技術填入凹陷底部的速率比頂部快。
成長控制層2402可包含任何合適金屬、金屬氧化物、金屬碳化物、金屬氮化物、及/或上述之組合，且可與黏著層2303的組成不同。在多種實施例中，成長控制層2402包含碳化鎢、氮化鎢、碳化鋁、氮化鋁、及/或其他合適材料。在某些實施例中，成長控制材料2402的一或多個金屬組成需搭配 後續沉積的填充材料之金屬組成。在某些實施例中，成長控制材料2402為碳化鎢或氮化鎢以搭配含鎢填充材料。在另一實施例中，成長控制材料2402為碳化鋁或氮化鋁以搭配含鋁填充材料。
成長控制層2402可沉積至任何厚度(垂直於側壁表面2404的厚度)，然而成長控制層2402之材料導電性較低，因此其厚度較薄(比如介於約1Å至約20Å之間)。成長控制層2402定義之側壁表面的組成，將不同於凹陷之下表面2406的組成。上述差異可用以調整後續的沉積製程。
任何合適的順應性或非順應性沉積均可用以形成成長控制層2402。在多種實施例中，ALD、CVD、濺鍍、及/或其他合適技術可用以形成成長控制層2402於側壁表面2404上。在一實施例中，成長控制層2402的金屬組成係由ALD沉積，接著以含氮及/或含碳之電漿處理，以形成金屬氮化物及/或金屬碳化物。在沉積後可進行非等向蝕刻製程，自凹陷2202之下表面2406移除任何沉積的材料。舉例來說，一實施例以濺鍍法沉積成長控制層2402後，接著進行非等向乾蝕刻以移除下表面2406上的沉積材料。
如第20圖之步驟2012與第25圖所示，接點/通孔的填充材料2502可沉積於凹陷中的成長控制層2402上。填充材料2502可包含任何合適的導體如金屬(比如鎢、鋁、鉭、鈦、鎳、銅、或類似物)、金屬氧化物、金屬氮化物、及/護上述之組合。接點的填充材料2502之沉積方法可為任何合適沉積技術如PVD(比如濺鍍)、CVD、PECVD、ALD、PEALD、及/或上述 之組合。由於成長控制層2402的關係，填充材料2502沉積於凹陷2202之下表面的速率會大於沉積於側壁表面2404上的速率。經由實驗分析確認，以本發明技術填充之高深寬比凹陷中的填充材料2502，可大幅降低孔洞與缺陷形成其中。
如第20圖之步驟2014與第26A及26B圖所示，可對半導體裝置100進行平坦化製程如CMP以移除超出凹陷的多餘材料。第26A圖對應第24A圖，其成長控制層2402並未延伸至下表面2406。第26B圖對應第24B圖，其成長控制層2402延伸至下表面2406。如第20圖之步驟2016，可對半導體裝置100進行額外製程。
其他以方法2000形成接點與通孔的實施例如第27A至29B圖所示。第27A與27B圖係以本發明技術形成接點124至非平面的半導體裝置200之源極/汲極區208的剖視圖。在許多實施例中，非平面的半導體裝置200與第2A至2C圖之半導體裝置類似，在此不贅述以簡化說明。
在此實施例中，接點124於垂直方向延伸至層間介電層120中，並於水平方向跨過一或多個源極/汲極區208。綜上所述，接點124的黏著層2302與第23圖之對應元件實質上相同，且位於至少一源極/汲極區208的至少一表面上，其形成方法如第20圖之步驟2008所示。黏著層2302亦可位於源極/汲極區208之間的基板102上。
接點124更包含成長控制層2402，其形成方法如第20圖之步驟2010所示。成長控制層2402係位於溝槽的側壁表面2404上，但不必位於下表面2406的基板102上。成長控制層2402 可位於源極/汲極區208上如第27A圖所示，或不位於這些區域如第27B圖所示。填充材料2502(如第25圖所示之填充材料2502)係位於成長控制層2402上，以完成接點124。
如第28A與28B圖所示，連接至非平面的半導體裝置200之閘極結構212之接點124其形成方法可為本發明的技術。在許多實施例中，非平面的半導體裝置200與第2A至2C圖所示之半導體裝置實質上相同，在此不贅述以簡化說明。接點124包含黏著層2302，其與第23圖之對應元件實質上相同。黏著層2302係位於閘極結構212上的層間介電層120中的凹陷內，其形成方法如第20圖之步驟2008所示。
接點124亦包含成長控制層2402，其形成方法儒義20圖之步驟2010所示。成長控制層2402位於溝槽之側壁表面2404上，但不必位於溝槽底部上，因此側壁與底部之組成不同可用以調整後續的沉積製程。成長控制層2402可沿著側壁表面2404的較上部份延伸如第28A圖所示，亦可延伸至底部(比如閘極結構212上的黏著層2302)如第28B圖所示。填充材料2502(與第25圖之填充材料2502類似)係位於成長控制層2402上，以完成接點124。
最後如第29A與29B圖所示，方法2000可用以形成通孔122。第29A與29B圖係本發明實施例中，平面或非平面之半導體裝置2900之內連線結構的剖視圖。與接點124類似，通孔122可包含黏著層2302，其與第23圖之對應元件實質上相同。位於層間介電層120中的凹陷內之黏著層2302，其形成方法如第20圖之步驟2008所示。黏著層2302可接觸其下方之導電 線路118。
通孔122包括第20圖之步驟2010形成的成長控制層2402。成長控制層2402位於凹陷的側壁表面2404上，但不必形成於下表面2406上，因此側壁與下表面的不同組成可用以調整後續的沉積製程。成長控制層2402沿著側壁表面2404的較上部份延伸如第29A圖所示，亦可延伸至閘極結構212上的黏著層2302如第29B圖所示。填充材料2502(如第25圖所示之填充材料2502)係位於成長控制層2402上，以完成通孔122。在某些實施例中，填充材料2502可形成導電線路118。
綜上所述，本發明揭露形成導電結構之技術，以及此技術形成之結構。在某些實施例中，此方法包含接收基板，其具有閘極結構於其上。閘極結構包括犧牲部份。移除犧牲部份以定義溝槽於閘極結構中。溝槽具有相對的側壁表面與下表面。選擇性地形成材料層於相對的側壁表面上，其中下表面不具有材料層。沉積閘極的填充材料於溝槽中的材料層與下表面上。在某些實施例中，形成材料層的步驟包括以ALD沉積金屬，並以含碳氣體對金屬進行電漿處理。在此實施例中，形成材料層的步驟包括沉積製程，以及自下表面移除沉積材料的蝕刻製程。
在其他實施例中，方法包括接收一基板，其具有一凹陷定義於其中，且凹陷具有至少兩個相對的側壁表面與下表面。沉積成長控制材料於凹陷中的相對的側壁表面上，且下表面不具有成長控制材料。沉積填充材料層於凹陷中，使填充材料層位於成長控制材料與下表面上。在某些實施例中，成長 控制材料包括金屬氮化物或金屬碳化物。在某些實施例中，成長控制材料與填充材料層包括共同的金屬。
在又一實施例中，半導體裝置包括基板，其具有閘極結構形成其上。閘極結構包括閘極介電層位於基板上、成長控制材料位於閘極結構之側壁表面上、以及閘極填充材料位於成長控制材料上與閘極結構的下表面上，且下表面不具有成長控制材料。在某些實施例中，閘極結構更包括阻障層位於閘極控制材料與閘極介電層之間，以及位於閘極填充材料與閘極介電層之間。在某些實施例中，阻障層與成長控制材料之組成不同。在某些實施例中，閘極填充材料接觸的第一表面與第二表面之組成不同。
雖然本發明已以數個實施例揭露如上，然其並非用以限定本發明，任何本技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧基板
200‧‧‧半導體裝置
206‧‧‧鰭狀結構
208‧‧‧源極/汲極區
210‧‧‧通道區
212‧‧‧閘極結構
214‧‧‧界面層
216‧‧‧閘極介電層
220‧‧‧閘極
222‧‧‧側壁間隔物
406‧‧‧功函數層
408‧‧‧濕潤層
410‧‧‧阻障層
412‧‧‧成長控制層
414‧‧‧溝槽側壁表面
416‧‧‧溝槽底部
418‧‧‧填充材料

Claims (11)

  1. 一種半導體裝置的形成方法，包括：接收一基板，其中該基板具有一閘極結構於其上，且該閘極結構包括一犧牲部份；移除該犧牲部份以定義一溝槽於該閘極結構中，其中該溝槽具有相對的側壁表面與一下表面；選擇性地形成一材料層於該些相對的側壁表面上，其中該下表面不具有該材料層；以及沉積一閘極的填充材料於該溝槽中的該材料層與該下表面上。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該材料層之步驟包括以原子層沉積法沉積金屬，並以含碳氣體對金屬進行電漿處理。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該材料層之步驟包括沉積製程，以及自該下表面移除沉積的該材料層之蝕刻製程。
  4. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該材料層包括金屬碳化物或金屬氮化物。
  5. 一種半導體裝置的形成方法，包括：接收一基板，其具有一凹陷定義於其中，且該凹陷具有至少兩個相對的側壁表面與一下表面；沉積一成長控制材料於該凹陷中的該些相對的側壁表面上，且該下表面不具有該成長控制材料；以及沉積一填充材料層於該凹陷中，使該填充材料層位於該成 長控制材料與該下表面上。
  6. 如申請專利範圍第5項所述之半導體裝置的形成方法，其中該成長控制材料包括金屬氮化物或金屬碳化物。
  7. 如申請專利範圍第6項所述之半導體裝置的形成方法，其中沉積該成長控制材料之步驟包括沉積金屬，以及以含氮氣體或含碳氣體對該金屬進行電漿處理。
  8. 如申請專利範圍第6項所述之半導體裝置的形成方法，其中形成該成長控制材料之步驟包括一沉積製程，與自下表面移除沉積的材料之一蝕刻製程。
  9. 一種半導體裝置，包括：一基板，具有一閘極結構形成其上，其中該閘極結構包括：一閘極介電層，位於該基板上；一成長控制材料，位於該閘極結構之側壁表面上；以及一閘極填充材料位於該成長控制材料上與該閘極結構的下表面上，且該下表面不具有該成長控制材料。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該成長控制材料包括金屬碳化物或金屬氮化物，且其中該成長控制材料與該閘極填充材料包括共同的金屬。
  11. 如申請專利範圍第9項所述之半導體裝置，其中該閘極填充材料接觸的一第一表面與一第二表面之組成不同。
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US20190058063A1 (en) 2019-02-21
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US10797176B2 (en) 2020-10-06
US20160141179A1 (en) 2016-05-19
US9466494B2 (en) 2016-10-11
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US10109741B2 (en) 2018-10-23
US20170033222A1 (en) 2017-02-02
CN105609420A (zh) 2016-05-25
KR101684772B1 (ko) 2016-12-08
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US11257953B2 (en) 2022-02-22

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