TW201539650A - 用於積體電路裝置之間隔物啟用之主動隔離 - Google Patents
用於積體電路裝置之間隔物啟用之主動隔離 Download PDFInfo
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Abstract
本發明揭示一種用於在一半導體積體電路晶粒中形成一主動隔離結構之方法。在一半導體基板上沈積一第一硬遮罩層。移除該第一硬遮罩層之部分以形成至少一溝渠。在該第一硬遮罩上沈積一間隔物層且該間隔物層延伸至各溝渠內以覆蓋各溝渠中之該半導體基板表面的暴露部分。移除該間隔物層之部分使得剩餘部分界定覆蓋各溝渠之側壁的間隔物層壁。沈積一第二硬遮罩層且該第二硬遮罩層延伸至各溝渠內且於相對間隔物層壁之間。移除該等間隔物層壁使得該第一及該第二硬遮罩層之剩餘部分界定一遮罩圖案,接著將該遮罩圖案轉移至該基板以在該基板中形成開口,該開口填充有一隔離材料。
Description
本發明係關於半導體積體電路(IC)製造,且更特定言之,在其之製造期間於一半導體晶粒(例如,積體電路晶粒)中形成次微影主動隔離結構。
可得微影程序通常已限制減小一半導體晶粒中(例如)用於定位電晶體及/或其他電路元件之主動隔離結構的尺寸。因為歸因於微影製造程序之改良,電晶體之尺寸已減小且半導體晶粒上的電晶體之密度已增大,所以隨著電晶體變得更小及/或填充更密集,用於定位此等電晶體之主動隔離結構的尺寸已不能按比例減小。
因此,需要減小主動隔離結構之尺寸的一方法,例如超過可得用於製造半導體積體電路之微影程序的典型限制。
根據本發明之教示,可由包含一間隔物層或膜之一程序形成主動隔離結構。此程序可啟用按比例調整遠低於當前光微影能力之主動隔離。例如,所揭示之用於形成隔離結構之程序可藉由使用一犧牲間隔物層或膜以使溝渠壁襯有一硬遮罩材料來使針對一給定的光微影圖案化之主動隔離圖案加倍。可填充間隔物膜側壁之間之間隙或使其經受一CMP程序以暴露間隔物膜側壁之頂面使得可移除間隔物膜側壁,
藉此在相同溝渠內留有兩個通道,可接著將該等通道圖案化為底層基板且填充其等以形成兩個隔離區域。
在一實施例中,一種用於在一半導體積體電路晶粒中形成一主動隔離結構之方法可包含:在一半導體基板之一表面上沈積一第一硬遮罩層;移除該第一硬遮罩層之部分以形成至少一溝渠,各溝渠界定壁及暴露該半導體基板表面的一開放底部;在該第一硬遮罩上沈積一間隔物層且延伸至各溝渠內以覆蓋各溝渠中之該暴露半導體基板表面;移除該間隔物層之部分,包含該間隔物層覆蓋各溝渠中之該暴露半導體基板表面的部分,使得該間隔物層之剩餘部分界定覆蓋各溝渠之該等壁的間隔物層壁;沈積延伸至各溝渠內且於各各自之溝渠中的相對間隔物層壁之間之一第二硬遮罩層;移除該等間隔物層壁使得該第一及該第二硬遮罩層之剩餘部分界定一遮罩圖案;藉由移除該基板之部分來將該遮罩圖案轉移至該基板以在該基板中形成開口;且使用一隔離材料填充該基板中之該等開口。
在另一實施例中,一半導體晶粒可包含一半導體基板及藉由一程序在該半導體基板上形成之一主動隔離結構,該程序包含:在該半導體基板之一表面上沈積一第一硬遮罩層;移除該第一硬遮罩層之部分以形成至少一溝渠,各溝渠界定壁及暴露該半導體基板表面的一開放底部;在該第一硬遮罩上沈積一間隔物層且延伸至各溝渠內以覆蓋各溝渠中之該暴露半導體基板表面;移除該間隔物層之部分,包含該間隔物層覆蓋各溝渠中之該暴露半導體基板表面的部分,使得該間隔物層之剩餘部分界定覆蓋各溝渠之該等壁的間隔物層壁;沈積延伸至各溝渠內且於各各自之溝渠中的相對間隔物層壁之間之一第二硬遮罩層;移除該等間隔物層壁使得該第一及該第二硬遮罩層之剩餘部分界定一遮罩圖案;藉由移除該基板之部分來將該遮罩圖案轉移至該基板以在該基板中形成開口;且使用一隔離材料填充該基板中之該等開
口。
在其他實施例中,一半導體晶粒包含一半導體基板及在該半導體基板中形成且具有小於1000nm之一厚度的一主動隔離結構。在一些實施例中,該主動隔離結構之該厚度小於100nm,或甚至小於15nm。
102‧‧‧矽晶圓
104‧‧‧半導體晶粒
200‧‧‧半導體基板
202‧‧‧第一硬遮罩層
206‧‧‧溝渠
210‧‧‧側壁
212‧‧‧半導體基板表面
220‧‧‧犧牲間隔物層或膜
222‧‧‧間隔物層側壁
224‧‧‧區域
226‧‧‧間隔物層側壁區域
230‧‧‧第二硬遮罩層
232‧‧‧間隙
240‧‧‧上表面
244‧‧‧開口
250‧‧‧遮罩圖案
256‧‧‧圖案
260‧‧‧開口
270‧‧‧隔離材料
272‧‧‧主動隔離區域
280‧‧‧主動島狀物
tspacer‧‧‧厚度
WIR‧‧‧寬度
Wopening‧‧‧寬度
Wtrench‧‧‧寬度
2K-2K‧‧‧橫截面線
下文參考附圖討論例示性實施例,其中:圖1繪示包括複數個半導體晶粒之一半導體積體電路晶圓之一示意平面視圖;圖2A至圖2K繪示根據本發明之一實施例之用於在一半導體積體電路晶粒的基板中形成主動隔離區域之一例示性方法;及圖3繪示根據一例示性實施例之由根據圖2A至圖2K之例示性方法形成的隔離區域界定之一對主動島狀物之一俯視圖。
根據本發明之教示,可由包含一間隔物層或膜之一程序形成主動隔離結構。如下文所討論,此程序可啟用按比例調整遠低於當前光微影能力之主動隔離。
現參考附圖,示意性繪示特定例示性實施例之細節。類似數字將表示附圖中之類似元件,且具有一不同小寫字體尾綴之類似數字將表示相似元件。
圖1展示包括複數個半導體晶粒之一半導體積體電路晶圓的一示意平面視圖。可將一矽晶圓102劃片為複數個半導體晶粒104用於進一步處理以在複數個半導體晶粒104之各者上創造平坦電晶體、二極體及導體。在已於複數個半導體晶粒104上製造全部電路之後,單粒化(分離)晶粒104且將其等封裝至積體電路(未展示)內。
圖2A至圖2K繪示根據本發明之一實施例之用於在一半導體積體
電路晶粒(例如,圖1中所展示之晶粒104)的基板中形成主動隔離區域之一例示性方法。該主動隔離區域可具有次微影尺寸(例如,一次微影厚度)。
如圖2A中所展示,在一半導體基板200上形成一第一主動硬遮罩層202。半導體基板200可包括任一合適之材料,例如矽。類似的,硬遮罩層202可包括任一合適之材料或多個材料(例如,SiN、SiON或其他介電材料)且可使用任一合適之技術形成。下一步,如圖2B中所展示,例如藉由一蝕刻程序來移除第一硬遮罩層202之部分以形成至少一溝渠206。各溝渠206可界定一或多個側壁210及暴露半導體基板200之上表面212的一開放底部。
各溝渠可具有任一合適之形狀。例如,各溝渠206之一周界(例如,如自上文觀察,諸如在圖3中)可具有一細長矩形形狀、一方形形狀、一圓形、橢圓或其他經修圓形狀或任一其他合適之形狀。另外,各溝渠206可具有任一合適之尺寸。例如,各溝渠206可具有適以提供一所得之主動島狀物(例如,圖3中所展示之主動島狀物280)的一寬度Wtrench,該寬度係適用於定位電晶體或其他電路結構之尺寸。例如,各溝渠206可具有介於20nm與20000nm之間的一寬度Wtrench。在一些實施例中,各溝渠206之寬度Wtreneh介於20nm與2000nm之間。在特定實施例中,各溝渠206之寬度Wtrench介於20nm與500nm之間。
下一步,如圖2C中所展示,一犧牲間隔物層或膜220形成於第一硬遮罩202上且延伸至各溝渠206內以覆蓋各溝渠206中之暴露半導體基板表面212。犧牲間隔物層220可包括任一合適之材料或多個材料(例如,SiO2或其他介電材料)且可使用任一合適之技術形成。如將就下列程序步驟所瞭解,犧牲間隔物層或膜220之厚度可實質上界定所得之形成於基板200中的主動隔離區域(例如,圖2K及圖3中所展示之主動隔離區域272)之寬度。因此,在一些實施例中,犧牲間隔物層
220可相對或非常薄,以提供一相對或非常薄或窄之主動隔離層。例如,犧牲間隔物層220可具有小於5000nm、小於1000nm或小於100nm之一厚度tspacer。在一些例示性實施例中,犧牲間隔物層220之厚度tspacer介於10nm與1000nm之間。在特定實施例中,犧牲間隔物層220之厚度tspacer介於10nm與100nm之間。
下一步,如圖2D中所展示,例如藉由一蝕刻程序移除犧牲間隔物層220之部分,包含覆蓋各溝渠206中之暴露半導體基板表面212的部分,使得犧牲間隔物層220之剩餘部分界定覆蓋各溝渠206之側壁210的間隔物層側壁222。如所展示,可在各間隔物層側壁222之頂部上發生圓化或角化,因此界定各間隔物層側壁222之一更均勻區域226上方的一經修圓、角形或錐形區域224。
下一步,如在圖2E中所展示,一第二硬遮罩層230形成於結構上且延伸至各各自之溝渠206中之相對間隔物層側壁222之間的間隙232內。第二硬遮罩層230可包括任一合適之材料或多個材料(例如,SiN、SiON或其他介電材料)且可使用任一合適之技術形成。在一些實施例中,第二硬遮罩層230包括與第一硬遮罩層202相同之材料。在其他實施例中,第一及第二硬遮罩層202及230包括不同之材料。
下一步,如圖2F中所展示,以任一合適之方式連同處於各間隔物層側壁222之上側上的經修圓、角形或錐形區域224一起,移除第二硬遮罩層230之部分,使得剩餘間隔物層側壁222之上表面240。在一些實施例中,例如如在圖式中所展示,材料移除程序可延伸穿過角形或錐形區域224以暴露各間隔物層側壁222之底層均勻區域226的一上表面240。在一些實施例中,材料移除程序包括一化學機械平坦化(CMP)程序。
下一步,如在圖2G中所展示,使用任一合適之技術(例如,一汲取程序)移除在材料移除程序(例如,CMP程序)之後剩餘的間隔物層側
壁222之部分,在此實施例中即間隔物層側壁區域226。因此,可能需在間隔物層材料與硬遮罩材料(多個)之間作出較佳選擇。第一及第二硬遮罩層202及230之剩餘部分界定藉由移除間隔物層側壁區域226以環繞開口244形成的一遮罩圖案250。
下一步,如在圖2H中所展示,執行一蝕刻程序或其他合適之材料移除程序以將遮罩圖案250轉移至基板200內,藉此在基板200中形成開口260的一對應圖案256,其中各開口對應於一先前移除之間隔物層側壁222。各開口260之底部可具有自蝕刻程序所得之一大體上經修圓形狀,或如圖2H中所展示的一大體上方格形狀。
歸因於上文所討論之程序,指示為Wopening之各開口的寬度可實質上等於犧牲間隔物層220之厚度tspacer(例如,20%以內)或至少取決於該厚度tspacer。在一些實施例中,一或多個開口260之寬度Wopening可小於可由當前光微影能力(例如,使用當前光阻圖案化技術)形成之寬度。例如,在一些實施例中,一或多個開口260之寬度Wopening可小於1000nm,小於100nm或甚至小於15nm。在一些例示性實施例中,一或多個開口260之寬度Wopening介於5nm與1000nm之間。在特定實施例中,一或多個開口260之寬度Wopening介於5nm與100nm之間。
下一步,如圖2I中所展示,使用任一合適之技術(例如,一剝除或蝕刻程序)移除第一及第二硬遮罩層202及230之剩餘區域,藉此暴露其中形成有開口260的圖案256之底層基板200。
下一步,如圖2J中所展示,執行一隔離填充以在基板200上沈積隔離材料270且該隔離材料270延伸至開口260內。隔離材料可包括一介電質(例如,SiO2)或任何合適之隔離材料。
下一步,如圖2K中所展示,以任一合適之方式(例如,使用一CMP程序)移除隔離材料270之部分,藉此在基板200中提供主動隔離區域272之一圖案。歸因於上文所討論之程序,指示為WIR之各隔離區
域272之寬度可等於在圖2H中所展示的步驟上形成基板200之對應開口260的寬度Wopening,且因此實質上等於犧牲間隔物層220之厚度tspacer(例如,20%以內)或至少取決於該厚度tspacer。因此,在一些實施例中,一或多個隔離區域272之寬度WIR可小於可由當前光微影能力(例如,使用當前光阻圖案化技術)形成之寬度。例如,在一些實施例中,一或多個隔離區域272之寬度WIR可小於1000nm,小於100nm或甚至小於15nm。在一些例示性實施例中,一或多個隔離區域272之寬度WIR介於5nm與1000nm之間。在特定實施例中,一或多個隔離區域272之寬度WIR介於5nm與100nm之間。
圖3繪示根據一例示性實施例之由根據圖2A至圖2K之例示性方法形成的隔離區域272界定之一對隔離主動島狀物280之一俯視圖。展示對應於圖2K之視圖的一橫截面線2K至2K。在此例示性實施例中,隔離區域272之一細長矩形周界界定各主動島狀物280,該細長矩形周界可自在圖2B中所展示之步驟中形成的細長矩形溝渠260所得。在其他實施例中,基於如上文所討論形成之溝渠206的形狀,主動島狀物280可經形成具有任一合適之周界形狀,例如一方形形狀、一圓形、橢圓或另外經修圓形狀或任一其他合適之形狀。
因此,在上文所揭示之方式中,可由包含一間隔物層或膜之一程序形成主動隔離結構。此程序可啟用按比例調整遠低於當前光微影能力之主動隔離,此可提供一般技術者將瞭解之各種優勢。
儘管本發明詳細描述所揭示之實施例,然將瞭解在不背離實施例之精神及範疇的情況下,可對其等進行各種改變、替代或變換。
200‧‧‧半導體基板
272‧‧‧主動隔離區域
280‧‧‧主動島狀物
WIR‧‧‧寬度
2K-2K‧‧‧橫截面線
Claims (20)
- 一種用於在一半導體積體電路晶粒中形成一主動隔離結構之方法,該方法包括:在一半導體基板之一表面上沈積一第一硬遮罩層;移除該第一硬遮罩層之部分以形成至少一溝渠,各溝渠界定側壁及暴露該半導體基板表面的一開放底部;在該第一硬遮罩上沈積一間隔物層且延伸至各溝渠內以覆蓋各溝渠中之該暴露半導體基板表面;移除該間隔物層之部分,包含該間隔物層覆蓋各溝渠中之該暴露半導體基板表面的部分,使得該間隔物層之剩餘部分界定覆蓋各溝渠之該等側壁的間隔物層側壁;沈積延伸至各溝渠內且於各各自之溝渠中的相對間隔物層側壁之間之一第二硬遮罩層;移除該等間隔物層側壁使得該第一及該第二硬遮罩層之剩餘部分界定一遮罩圖案;藉由移除該基板之部分來將該遮罩圖案轉移至該基板以在該基板中形成開口;及使用一隔離材料填充該基板中之該等開口。
- 如請求項1之方法,其中:使用一隔離材料填充該基板中之該等開口包括在該半導體基板上沈積該隔離材料且延伸至該基板之該等開口內;且該方法進一步包括移除該基板中之該等開口外部之該隔離材料的部分,使得各經隔離材料填充之開口界定該半導體基板中之一主動隔離區域。
- 如請求項1之方法,其進一步包括在沈積該第二硬遮罩層之後且 在移除該間隔物層側壁以界定該遮罩圖案之前,移除至少該第二硬遮罩層的部分使得暴露該等間隔物層側壁之表面。
- 如請求項3之方法,其中該移除至少該第二硬遮罩層的部分之步驟亦移除該等間隔物層側壁的部分使得暴露該等間隔物層側壁之該等剩餘部分的表面。
- 如請求項4之方法,其中移除該等間隔物層側壁之部分使得暴露該等間隔物層側壁的該等剩餘部分之表面包括移除該等間隔物層側壁之上部、經修圓部分以暴露該等間隔物層側壁的下部、未經修圓部分。
- 如請求項1之方法,其中移除該等間隔物層側壁暴露介於界定該遮罩圖案的該第一及該第二硬遮罩層之該等剩餘部分之間的該半導體基板表面之底層部分。
- 如請求項1之方法,其進一步包括在將該遮罩圖案轉移至該基板之後且在使用該隔離材料填充該基板中的該等開口之前移除該第一及該第二硬遮罩層之該等剩餘部分。
- 如請求項1之方法,其中該第一硬遮罩層及該第二硬遮罩層包括相同材料。
- 如請求項1之方法,其中至少一間隔物層側壁具有小於1000nm之一厚度。
- 如請求項1之方法,其中至少一間隔物層側壁具有介於15nm與100nm之間的一厚度。
- 如請求項1之方法,其中藉由將該遮罩圖案轉移至該基板以在該基板中形成之該等開口的至少一者具有小於1000nm之一厚度。
- 如請求項1之方法,其中藉由將該遮罩圖案轉移至該基板以在該基板中形成之該等開口的至少一者具有介於15nm與100nm之間的一厚度。
- 如請求項1之方法,其中移除該第一硬遮罩層之部分以形成至少一溝渠包括移除該第一硬遮罩層的部分以形成具有一矩形周界之至少一溝渠。
- 如請求項1之方法,其中移除該第一硬遮罩層之部分以形成至少一溝渠包括移除該第一硬遮罩層的部分以形成具有一圓形或經修圓周界之至少一溝渠。
- 如請求項1之方法,其中該間隔物層包括一介電質。
- 如請求項1之方法,其中該隔離材料包括一介電質。
- 如請求項1之方法,其中該間隔物層及該隔離材料包括該相同材料。
- 一種半導體晶粒,其包括:一半導體基板;及一主動隔離結構,其藉由一程序形成於該半導體基板中,該程序包含:在該半導體基板之一表面上沈積一第一硬遮罩層;移除該第一硬遮罩層之部分以形成至少一溝渠,各溝渠界定側壁及暴露該半導體基板表面的一開放底部;在該第一硬遮罩上沈積一間隔物層且延伸至各溝渠內以覆蓋各溝渠中之該暴露半導體基板表面;移除該間隔物層之部分,包含該間隔物層覆蓋各溝渠中之該暴露半導體基板表面的部分,使得該間隔物層之剩餘部分界定覆蓋各溝渠之該等側壁的間隔物層側壁;沈積延伸至各溝渠內且於各各自之溝渠中的相對間隔物層側壁之間之一第二硬遮罩層;移除該等間隔物層側壁使得該第一及該第二硬遮罩層之剩餘部分界定一遮罩圖案; 藉由移除該基板之部分來將該遮罩圖案轉移至該基板以在該基板中形成開口;及使用一隔離材料填充該基板中之該等開口。
- 一種半導體晶粒,其包括:一半導體基板;及一主動隔離結構,其形成於該半導體基板中且具有小於100nm之一厚度。
- 如請求項19之半導體晶粒,其中該主動隔離結構具有小於15nm之一厚度。
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-
2014
- 2014-02-19 US US14/184,177 patent/US9269606B2/en active Active
-
2015
- 2015-02-18 KR KR1020167016877A patent/KR20160122695A/ko unknown
- 2015-02-18 EP EP15759563.8A patent/EP3108500B1/en active Active
- 2015-02-18 WO PCT/US2015/016334 patent/WO2015187210A2/en active Application Filing
- 2015-02-18 CN CN201580005060.5A patent/CN106030767A/zh active Pending
- 2015-02-24 TW TW104105948A patent/TWI646629B/zh active
Also Published As
Publication number | Publication date |
---|---|
WO2015187210A2 (en) | 2015-12-10 |
US9269606B2 (en) | 2016-02-23 |
WO2015187210A3 (en) | 2016-02-04 |
EP3108500A2 (en) | 2016-12-28 |
KR20160122695A (ko) | 2016-10-24 |
EP3108500B1 (en) | 2021-06-23 |
TWI646629B (zh) | 2019-01-01 |
US20150235895A1 (en) | 2015-08-20 |
CN106030767A (zh) | 2016-10-12 |
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