TW201535752A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201535752A
TW201535752A TW104104420A TW104104420A TW201535752A TW 201535752 A TW201535752 A TW 201535752A TW 104104420 A TW104104420 A TW 104104420A TW 104104420 A TW104104420 A TW 104104420A TW 201535752 A TW201535752 A TW 201535752A
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layer
electrode
less
semiconductor device
substrate
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TWI619255B (zh
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Yohsuke Kanzaki
Seiji Kaneko
Takao Saitoh
Yutaka Takamaru
Keisuke Ide
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Sharp Kk
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Abstract

本發明之半導體裝置(100A)係包含：基板(11)；TFT(10A)，其受基板支持，且具有氧化物半導體層(16)；有機絕緣層(24)，其係以覆蓋TFT之方式設置；下層電極(32)，其設置於有機絕緣層上；介電質層(34)，其設置於下層電極上；及上層電極(36)，其設置於介電質層上，且具有介隔介電質層而與下層電極對向之部分。介電質層係含氫量為5.33×1021個/cm3以下之矽氮化物膜。

Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法，尤其關於具備氧化物半導體TFT之半導體裝置及其製造方法。
近年來，主動矩陣型之液晶顯示裝置被廣泛使用。主動矩陣型液晶顯示裝置係具備：主動矩陣基板(亦稱為「TFT基板」)，其係於各像素設置有薄膜電晶體(TFT)；對向基板，其係與主動矩陣基板對向；及液晶層，其設置於該等構件之間。主動矩陣型液晶顯示裝置係藉由控制經由TFT施加於各像素之液晶層(電性上稱為「液晶電容」)之電壓，而調節透射各像素之光量，並進行顯示。於TFT基板之各像素，設置與液晶電容電性並聯連接之輔助電容。
於專利文獻1，提出用以提高主動矩陣型液晶顯示裝置之開口率之構造。於專利文獻1所提出之構造中，以覆蓋TFT之方式形成有機絕緣層，且於該有機絕緣層上，將輔助電容電極、介電質層及像素電極以該順序(或其相反之順序)積層，藉此形成輔助電容。
另一方面，最近，作為TFT之活性層之材料，氧化物半導體備受矚目。於專利文獻2中，作為變化例2，揭示有使用將氧化物半導體膜設為活性層之TFT作為開關元件之主動矩陣型液晶顯示裝置。氧化物半導體可具有較非晶矽更高之遷移率，以較將非晶矽膜設為活性層之 TFT(以下，為「非晶矽TFT」)更高之速度進行動作。於本申請案說明書中，有時將以氧化物半導體膜作為活性層之TFT稱為「氧化物半導體TFT」。
[先前技術文獻] [專利文獻]
專利文獻1：日本特開平9-171196號公報
專利文獻2：日本特開2010-230744號公報
本申請案發明者已知就具備氧化物半導體TFT之主動矩陣型液晶顯示裝置，採用於覆蓋氧化物半導體TFT之有機絕緣層上形成輔助電容之構成時，若於高溫高濕下進行保存試驗，則會發生於液晶層中產生氣泡之問題。此種氣泡之產生成為顯示品質下降之原因，因而導致液晶顯示裝置之可靠性降低。
本發明係鑑於上述問題而完成者，其目的在於提高具備氧化物半導體TFT之半導體裝置於高溫高濕下之可靠性。
本發明之實施形態之半導體裝置係具備：基板；薄膜電晶體，其受上述基板支持，且具有氧化物半導體層；有機絕緣層，其係以覆蓋上述薄膜電晶體之方式設置；下層電極，其設置於上述有機絕緣層上；介電質層，其設置於上述下層電極上；上層電極，其設置於上述介電質層上，且具有介隔上述介電質層而與上述下層電極對向之部分；且上述介電質層係含氫量為5.33×1021個/cm3以下之矽氮化物膜。
於某實施形態中，上述矽氮化物膜之介電常數為6.56以下。
於某實施形態中，上述氧化物半導體層係包含In-Ga-Zn-O系半導體。
於某實施形態中，上述In-Ga-Zn-O系半導體係包含結晶質部分。
於某實施形態中，上述氧化物半導體層係包含In-Sn-Zn-O系半導體、In-Ga-Sn-O系半導體或In-Ga-O系半導體。
於某實施形態中，上述上層電極及上述下層電極之各者係包含透明導電材料。
本發明之實施形態之半導體裝置之製造方法係包含：準備基板之步驟(a)、於上述基板上形成具有氧化物半導體層之薄膜電晶體之步驟(b)、以覆蓋上述薄膜電晶體之方式形成有機絕緣層之步驟(c)、於上述有機絕緣層上形成下層電極之步驟(d)、於上述下層電極上形成介電質層之步驟(e)、及於上述介電質層上形成上層電極之步驟(f)，上述步驟(e)係形成矽氮化物膜作為上述介電質層之步驟，以上述矽氮化物膜之含氫量為5.33×1021個/cm3以下之成膜條件執行。
於某實施形態中，上述步驟(e)係以上述矽氮化物膜之介電常數為6.56以下之成膜條件執行。
於某實施形態中，上述步驟(e)係藉由電漿CVD法，使用包含SiH4、NH3及/或N2之混合氣體，以腔室內壓力為1200mTorr以上1500mTorr以下，基板溫度為180℃以上220℃以下，電極間距離為18mm以上25mm以下，SiH4相對於上述混合氣體之全流量之流量比為3%以上5%以下，功率密度為0.36W/cm2以上之成膜條件執行。
於某實施形態中，上述步驟(e)係以0.49W/cm2以下之功率密度執行。
根據本發明之實施形態，可提高具備氧化物半導體TFT之半導體裝置於高溫高濕下之可靠性。
10A‧‧‧薄膜電晶體(TFT)
10B‧‧‧薄膜電晶體(TFT)
11‧‧‧基板
12g‧‧‧閘極電極
14‧‧‧閘極絕緣膜
16‧‧‧氧化物半導體層
17‧‧‧蝕刻擋止層
18d‧‧‧汲極電極
18s‧‧‧源極電極
22‧‧‧保護層
22a‧‧‧開口部
24‧‧‧有機絕緣層
24a‧‧‧開口部
32‧‧‧下層電極
34‧‧‧介電質層
34a‧‧‧開口部
36‧‧‧上層電極
100A‧‧‧TFT基板
100B‧‧‧TFT基板
BL‧‧‧氣泡
CH‧‧‧接觸孔
G‧‧‧掃描配線(閘極匯流排線)
P‧‧‧液晶顯示面板
S‧‧‧信號配線(源極匯流排線)
圖1(a)及(b)分別係本發明之實施形態之TFT基板100A之示意性剖 面圖及俯視圖。
圖2(a)~(e)係示意性顯示TFT基板100A之製造步驟之步驟剖面圖。
圖3(a)~(c)係示意性顯示TFT基板100A之製造步驟之步驟剖面圖。
圖4(a)及(b)係示意性顯示TFT基板100A之製造步驟之步驟剖面圖。
圖5係就實施例1~4及比較例1、2之各者，顯示矽氮化物膜之介電常數之算出結果之圖表。
圖6係就實施例1~4及比較例1、2之各者，顯示含氫量之算出結果之圖表。
圖7(a)及(b)分別係本發明之實施形態之其他TFT基板100B之示意性剖面圖及俯視圖。
圖8係示意性顯示液晶層中產生之氣泡BL之圖。
圖9係顯示產生劣化(臨限值電壓偏移到負)之TFT之Id-Vg特性之例之圖表。
首先，關於上述之氣泡之產生，說明本申請案發明者研究得出之見解。
本申請案發明者就具備氧化物半導體TFT之主動矩陣型液晶顯示裝置，採用於覆蓋氧化物半導體TFT之有機絕緣層上形成輔助電容之構成後發現，若於高溫高濕下進行保存試驗，則有時於液晶層中產生氣泡。圖8中係示意性顯示於液晶顯示面板P中產生之氣泡BL。氣泡BL之大小(直徑)為例如約10mm。
氣泡於產生之初期階段小到無法目視，隨著時間之流逝逐漸匯聚變大。到確認氣泡之產生為止之時間係水蒸汽壓越高之條件下越 短。例如，於50℃‧95%RH、60℃‧95%RH及70℃‧95%RH之條件下，到產生氣泡為止之時間係以上述順序漸短。本申請案發明者分析氣泡之成分後發現，氣泡之主成分(體積比約90%)為H2(氫)，剩餘成分為N2(氮)、CO(一氧化碳)及CO2(二氧化碳)。
氣泡產生之機制雖未完全判明，但可推測氣泡所含氫係作為構成輔助電容之介電質層形成之矽氮化物膜所含有者。又，因於有機絕緣層上形成有輔助電容之構成中產生氣泡，故可認為位於矽氮化物膜下之有機絕緣層與氣泡之產生大有關係。
本申請案發明係基於本申請案發明者研究得出之上述見解而設想者。以下，參照圖式說明本發明之實施形態之半導體裝置及其製造方法，本發明並未限定於例示之實施形態。本發明之實施形態之半導體裝置亦可為具備氧化物半導體TFT之各種基板、各種顯示裝置、各種電子機器。以下，以液晶顯示裝置用之TFT基板(主動矩陣基板)為例進行說明。液晶顯示裝置之顯示模式並未特別限定，此處例示以FFS(Fringe Field Switching：邊緣場切換)模式進行顯示之液晶顯示裝置所使用之TFT基板。另，以下說明中，具有實質性相同功能之構成要件係以共通之參照符號顯示，且有時省略說明。
圖1(a)及(b)中係顯示本發明之實施形態之TFT基板100A。圖1(a)及(b)分別為TFT基板100A之示意性剖面圖及俯視圖，圖1(a)係與圖1(b)中之沿A-A'線之剖面(包含TFT10A之剖面)對應。另，於圖1(b)中，省略了圖1(a)所示之構成要件之一部分(下述之上層電極36等)。
TFT基板100A係如圖1(a)及(b)所示，具備基板(典型為透明基板)11、及受基板11支持之薄膜電晶體(TFT)10A。TFT10A具有閘極電極12g、閘極絕緣膜14、氧化物半導體層16、源極電極18s及汲極電極18d。即，TFT10A為氧化物半導體TFT。
閘極電極12g係與掃描配線(閘極匯流排線)G電性連接(於本實施 形態中係自掃描配線G分支)，且自掃描配線G被供給掃描信號。閘極絕緣膜14係以覆蓋閘極電極12g之方式形成。氧化物半導體層16為島狀，且係以介隔閘極絕緣膜14而與閘極電極12g重疊之方式形成。
源極電極18s係與信號配線(源極匯流排線)S電性連接(於本實施形態中係自信號配線S分支)，且自信號配線S被供給顯示信號。源極電極18s係以與氧化物半導體層16之一部分(稱為源極區域)連接之方式設置。與此相對，汲極電極18d係以與氧化物半導體層16之另一部分(稱為汲極區域)連接之方式設置。氧化物半導體層16之位於源極區域與汲極區域之間之區域稱為通道區域。以覆蓋具有上述之構成之TFT10A之方式，形成有保護層22。
本實施形態之TFT100A進而具備有機絕緣層24、下層電極32、介電質層34、及上層電極36。
有機絕緣層24係於保護層22上以覆蓋TFT10A之方式設置。有機絕緣層24典型而言係包含感光性樹脂材料。有機絕緣層24之厚度為例如1μm~3μm。
下層電極32係設置於有機絕緣層24上。此處，下層電極32係以遍及液晶顯示裝置之所有像素連續之方式形成。但，下層電極32係未形成於用以電性連接TFT10A之汲極電極18d與下述之上層電極36之接觸孔CH之附近。下層電極32係藉由被供給共通信號(COM信號)而作為共通電極發揮功能。
介電質層34係設置於下層電極32上。介電質層34係如下所述，為矽氮化物膜。介電質層34之厚度為例如50nm~200nm。
上層電極36係設置於介電質層34上。上層電極36係具有介隔介電質層34而與下層電極32對向之部分。上層電極36係獨立(分離)形成於液晶顯示裝置之各像素，且雖未圖示，但上層電極36係具有至少一個狹縫。上層電極36係於接觸孔CH中與TFT10A之汲極電極18d電性 連接，且作為像素電極而發揮功能。
此處，上層電極36及下層電極32之各者係包含透明導電材料之透明電極。即，藉由上層電極36及下層電極32、與位於其等之間之介電質層34，而於像素內形成透明輔助電容。像素內透明輔助電容所占面積之比例典型而言為50%~80%。
另，雖未圖示，但於上層電極36上形成配向膜。於液晶顯示裝置中，以與TFT基板100A對向之方式配置對向基板，且於TFT基板100A與對向基板之間，設置液晶層。
於本實施形態之TFT基板100A中，介電質層34係含氫量相對較少，即相對緻密之矽氮化物膜。具體而言，介電質層34係含氫量為5.33×1021個/cm3以下之矽氮化物膜，藉此，於此後以加入檢證結果予以詳述之方式，抑制液晶層中氣泡之產生。因此，可提高高溫高濕下之可靠性。
且，根據本申請案發明者之研究，已知若於具備氧化物半導體TFT之TFT基板中形成緻密之矽氮化物膜作為介電質層，則存在無法獲得期望之TFT特性之情形。具體而言，如圖9所示，因臨限值電壓偏移至負，而使TFT為常開設備，內置於液晶顯示裝置內之電路(例如作為閘極驅動器使用之移位暫存器電路)之動作變得困難。
本申請案發明者進而反復研究，結果得出藉由以避免介電常數過高之方式形成矽氮化物膜，可抑制氧化物半導體TFT之特性劣化。具體而言，自抑制氧化物半導體TFT即TFT10A之特性劣化之觀點而言，矽氮化物膜(介電質層34)之介電常數較佳為6.56以下。藉由將矽氮化物膜之含氫量設為5.33×1021個/cm3以下，且將介電常數設為6.56以下，可抑制TFT10A之特性劣化，且抑制液晶層中氣泡之產生。
其次，一面參照圖2、圖3及圖4，一面說明本實施形態之TFT基板100A之製造方法。圖2(a)~(e)、圖3(a)~(c)及圖4(a)、(b)係示意性顯 示TFT基板100A之製造步驟之步驟剖面圖。
首先，如圖2(a)所示，準備基板11。作為基板11，可使用玻璃基板或具有耐熱性之塑膠基板等。此處，使用玻璃基板。
其次，於基板11上，形成具有氧化物半導體層16之TFT10A。
具體而言，首先，如圖2(b)所示，於基板11上藉由濺鍍法等堆積導電膜(以下，稱為「閘極金屬膜」)後，使用光微影製程使閘極金屬膜圖案化，藉此形成閘極電極12g及掃描配線G(未於圖2(b)中圖示)。此處，依序堆積厚度20nm之氮化鉭膜(TaN膜)及厚度300nm之鎢膜(W膜)，且使獲得之積層膜圖案化，藉此形成閘極電極12g及掃描配線G。
其次，如圖2(c)所示，藉由CVD(Chemical Vapor Deposition：化學氣體沈積)法等，形成覆蓋閘極電極12g及閘極匯流排線G之閘極絕緣膜14。此處，藉由依序堆積厚度300nm之矽氮化物膜(SiNx膜)及厚度50nm之矽氧化物膜(SiO2膜)，而形成閘極絕緣膜14。
繼而，如圖2(d)所示，於閘極絕緣膜14上藉由濺鍍法或CVD法等堆積氧化物半導體膜後，使用光微影製程使氧化物半導體膜圖案化，藉此形成島狀之氧化物半導體層16。此處，以濺鍍法堆積厚度50nm之In-Ga-Zn-O系之半導體(以下簡稱為「In-Ga-Zn-O系半導體」)膜後，對基板整體進行熱處理(例如300℃以上500℃以下，1~2小時左右)。藉由進行熱處理，可恢復氧化物半導體之氧欠缺。其後，使用光微影製程使In-Ga-Zn-O系半導體膜圖案化，形成島狀之氧化物半導體層16。
如此，氧化物半導體層16係包含例如In-Ga-Zn-O系半導體。此處，In-Ga-Zn-O系半導體係In(銦)、Ga(鎵)、Zn(鋅)之三元系氧化物，且In、Ga及Zn之比例(組成比)並未特別限定，包含例如In：Ga：Zn=2：2：1，In：Ga：Zn=1：1：1，In：Ga：Zn=1：1：2等。於本 實施形態中，氧化物半導體層16亦可為以例如In：Ga：Zn=1：1：1之比例包含In、Ga、Zn之In-Ga-Zn-O系半導體層。
由於具有In-Ga-Zn-O系半導體層之TFT具有高遷移率(相較於a-SiTFT超過20倍)及低洩漏電流(相較於a-SiTFT不滿百分之一)，因而適合用作驅動TFT及像素TFT。若使用具有In-Ga-Zn-O系半導體層之TFT，可大幅度削減顯示裝置之消耗電力。
In-Ga-Zn-O系半導體亦可為非晶矽，又可包含結晶質部分。作為結晶質In-Ga-Zn-O系半導體，較佳為c軸大致垂直配向於層面之結晶質In-Ga-Zn-O系半導體。此種In-Ga-Zn-O系半導體之結晶構造係例如揭示於日本專利特開2012-134475號公報。為參考，而將日本專利特開2012-134475號公報之揭示內容全部援用於本說明書。
氧化物半導體層16亦可取代In-Ga-Zn-O系半導體，而包含其他氧化物半導體。例如亦可包含Zn-O系半導體(ZnO)、In-Zn-O系半導體(IZO(註冊商標))、Zn-Ti-O系半導體(ZTO)、Cd-Ge-O系半導體、Cd-Pb-O系半導體、CdO(氧化鎘)、Mg-Zn-O系半導體、In-Sn-Zn-O系半導體(例如In2O3-SnO2-ZnO)、In-Ga-Sn-O系半導體、In-Ga-O系半導體等。
其次，如圖2(e)所示，藉由濺鍍法等而於氧化物半導體層16上堆積導電膜(以下稱為「源極金屬膜」)後，使用光微影製程使源極金屬膜圖案化，藉此形成源極電極18s、汲極電極18d及信號配線S(未於圖2(e)中圖示)。此處，依序堆積厚度30nm之鈦膜(Ti膜)、厚度300nm之鋁膜(Al膜)及厚度100nm之Ti膜，並使獲得之積層膜圖案化，藉此形成源極電極18s、汲極電極18d及源極匯流排線S。如此，可於基板11上形成具有氧化物半導體層16之TFT10A。
其次，如圖3(a)所示，藉由CVD(Chemical Vapor Deposition)法等，於TFT10A上堆積保護層22。此處，藉由堆積厚度300nm之二氧 化矽膜(SiO2膜)，而形成保護層22。其後，對基板整體進行熱處理(例如250℃以上450℃以下，1~2小時左右)。藉由進行熱處理，可降低氧化物半導體層16、與源極電極18s及汲極電極18d之間之接觸電阻。又，氧化物半導體層16之通道區域被氧化之結果，可降低通道區域內之氧欠缺。
繼而，如圖3(b)所示，以覆蓋TFT10A之方式形成有機絕緣層24。有機絕緣層24係可藉由將例如正型之感光性樹脂材料(例如丙烯酸系樹脂材料)賦予保護層22上後，進行曝光、顯影而形成。作為有機絕緣層24之材料，亦可使用負型之感光性樹脂材料。此處，使用丙烯酸系樹脂材料形成厚度2.0μm之有機絕緣層24。此時，於與汲極電極18d重疊之位置形成開口部24a。又，其後，藉由將有機絕緣層24設為遮罩進行蝕刻，而於保護層22形成開口部22a，露出汲極電極18d之一部分。
其次，如圖3(c)所示，於有機絕緣層24上形成下層電極32。下層電極32係可藉由於有機絕緣層24上利用濺鍍法等堆積透明導電膜後，使用光微影製程使透明導電膜圖案化而形成。作為透明導電膜之材料，可使用銦錫氧化物(ITO)、銦鋅氧化物(IZO(註冊商標))等。此處，藉由使堆積厚度100nm之IZO膜所獲得之透明導電膜圖案化，而形成下層電極32。
其次，如圖4(a)所示，於下層電極32上形成介電質層34。於本實施形態中，作為介電質層34，藉由電漿CVD法而形成矽氮化物膜。矽氮化物膜之形成係以如下述之成膜條件執行。此處，堆積厚度100nm之矽氮化物膜。其後，藉由於介電質層34之一部分(與保護層22之開口部22a及有機絕緣層24之開口部24a重疊之區域)利用蝕刻形成開口部34a，而形成用以電性連接TFT10A之汲極電極18d與上層電極36之接觸孔CH。
繼而，如圖4(b)所示，於介電質層34上形成上層電極36。上層電極36係可與下層電極32同樣地形成。此處，藉由堆積厚度100nm之IZO膜，且使獲得之透明導電膜圖案化，而形成上層電極36。上層電極36係於接觸孔CH中與TFT10A之汲極電極18d電性連接。
如此，可獲得圖1(a)及(b)所示之TFT基板100A。
此處，說明形成介電質層34之步驟中矽氮化物膜之成膜條件。於本實施形態中，形成矽氮化物膜之步驟係以矽氮化物膜之含氫量為5.33×1021個/cm3以下之成膜條件執行。藉由電漿CVD法形成矽氮化物膜之情形時，作為原料氣體，可使用例如SiH4及NH3之混合氣體、SiH4及N2之混合氣體、或SiH4、NH3及N2之混合氣體。即，可使用包含SiH4、與NH3及/或N2之混合氣體。
作為成膜條件之參數，例舉腔室內壓力、基板溫度、電極間距離、SiH4相對於混合氣體之全流量之流量比、及功率密度。於該等參數中，藉由提高例如功率密度，可使矽氮化物膜更緻密(即，提高介電常數)而減少含氫量。
為了將矽氮化物膜之含氫量設為5.33×1021個/cm3以下，形成矽氮化物膜之步驟較佳為以矽氮化物膜之介電常數為6.25以上之成膜條件執行。具體而言，於腔室內壓力為1200mTorr以上1500mTorr以下，基板溫度為180℃以上220℃以下，電極間距離為18mm以上25mm以下，SiH4相對於混合氣體之全流量之流量比為3%以上5%以下之情形時，將功率密度設為0.36W/cm2以上，藉此可將矽氮化物膜之含氫量設為5.33×1021個/cm3以下。
另，若功率密度過高，則有氧化物半導體TFT即TFT10A之特性劣化(例如臨限值電壓偏移至負)，或有機絕緣層24變色之狀況。為了抑制該等問題之產生，功率密度較佳為0.49W/cm2以下。藉由使功率密度為0.49W/cm2以下，可將矽氮化物膜之介電常數設為6.56以下， 而可抑制TFT10A之特性劣化或對有機絕緣層24之不良影響，並抑制於液晶層產生氣泡。
繼而，說明使用藉由上述製造方法實際製作之TFT基板100A試作液晶顯示裝置，且驗證高溫高濕下之可靠性之結果。
<實施例1>
基於上述之製造方法製作TFT基板，使用該TFT基板製作實施例1之液晶顯示裝置。矽氮化物膜之厚度設為300nm。形成矽氮化物膜之步驟之成膜條件係如以下所示。
功率密度：0.36W/cm2
腔室內壓力：1400mTorr
基板溫度：200℃
氣體流量比：SiH4：NH3：N2=1：4：20
電極間距離：20mm
<實施例2>
除了將功率密度設為0.41W/cm2以外，與實施例1之液晶顯示裝置相同，製作實施例2之液晶顯示裝置。
<實施例3>
除了將功率密度設為0.45W/cm2以外，與實施例1之液晶顯示裝置相同，製作實施例3之液晶顯示裝置。
<實施例4>
除了將功率密度設為0.49W/cm2以外，與實施例1之液晶顯示裝置相同，製作實施例4之液晶顯示裝置。
<比較例1>
除了將功率密度設為0.28W/cm2以外，與實施例1之液晶顯示裝置相同，製作比較例1之液晶顯示裝置。
<比較例2>
除了將功率密度設為0.32W/cm2以外，與實施例1之液晶顯示裝置相同，製作比較例2之液晶顯示裝置。
使用恆溫恒濕器(楠本化成社製FX420N)，將實施例1~4及比較例1、2之液晶顯示裝置於70℃、95%RH之環境下保存300小時後，藉由目視及光學顯微鏡確認有無氣泡產生。其結果，於比較例1及2之液晶顯示裝置中產生氣泡，與此相對，實施例1~4中未產生氣泡。
其次，分解各液晶顯示裝置，使用電容測定裝置(惠普(Hewlett-Packard)社製4284A)，測定各TFT基板之介電質層(矽氮化物膜)之電容，算出介電常數(測定頻率：1kHz)。圖5中就實施例1~4及比較例1、2之各者顯示矽氮化物膜之介電常數之算出結果。
由圖5可知，實施例1~4之矽氮化物膜之介電常數分別為6.25、6.35、6.48、6.56。與此相對，比較例1及2之矽氮化物膜之介電常數分別為5.82、6.05。如此可確認，於實施例1~4中，與比較例1、2相比，介電常數較高，即，形成有緻密之矽氮化物膜。
又，使用升溫脫離氣體分析法(Thermal Desorption Spectroscopy(TDS))就各TFT基板之介電質層(矽氮化物膜)測定脫氫量，且自獲得之脫氫量算出矽氮化物膜之含氫量。於脫氫量之測定中，使用電子科學社製TDS1200。各試料之加熱係藉由使溫度以1×10-7Pa之真空度及1℃/sec之升溫速度自80℃上升至700℃而執行。圖6中係就實施例1~4及比較例1、2之各者顯示含氫量之算出結果。
由圖6可知，比較例1及2中含氫量分別為7.73×10-21個/cm3、6.30×10-21個/cm3，與此相對，實施例1~4中含氫量分別為5.33×1021個/cm3、4.63×1021個/cm3、4.20×1021個/cm3、3.60×1021個/cm3。即，於實施例1~4中，與比較例1及2相比，矽氮化物膜之含氫量較少，任一者皆為5.33×1021個/cm3以下。
由上述之驗證結果可知，藉由將形成輔助電容之介電質層34即 矽氮化物膜之含氫量設為5.33×1021個/cm3以下，可抑制液晶層中產生氣泡，而可提高液晶顯示裝置於高溫高濕下之可靠性。
另，於上述說明中，藉由提高成膜條件之參數中之功率密度，減少矽氮化物膜之含氫量，藉由減少SiH4相對於混合氣體之全流量之流量比，亦可減少矽氮化物膜之含氫量。但，藉由功率密度之調整而控制矽氮化物膜之含氫量之方法在維持基板面內之膜厚之均一性之方面較佳。
其次，說明本發明之實施形態之TFT基板100A之改變例。圖7(a)及(b)中顯示本發明之實施形態之其他TFT基板100B。圖7(a)及(b)分別為TFT基板100B之示意性剖面圖及俯視圖，圖7(a)係與沿圖7(b)中之A-A'線之剖面(包含TFT10B之剖面)對應。另，於圖7(b)中，省略了圖7(a)所示之構成要件之一部分(下述之上層電極36等)。
如圖7(a)及(b)所示，於TFT基板100B中，TFT10B係具有以覆蓋氧化物半導體層16之通道區域之方式設置之蝕刻擋止層17。藉由設置蝕刻擋止層17，可降低產生於氧化物半導體層16之製程損傷。又，若蝕刻擋止層17包含矽氧化物膜等之氧化物膜，則於氧化物半導體產生氧欠缺之情形時，由於可藉由氧化物膜所含之氧恢復氧欠缺，因此可降低氧化物半導體之氧欠缺。
蝕刻擋止層17係可在氧化物半導體層16之形成後，於源極電極18s及汲極電極18d之形成前，藉由例如CVD法，於氧化物半導體層16上堆積保護膜，且使用光微影製程使該保護膜圖案化而形成。圖案化係以藉由蝕刻擋止層17至少覆蓋氧化物半導體層16中作為通道區域之區域之方式執行。此處，作為蝕刻擋止層17，使用厚度150nm之SiO2膜。作為蝕刻擋止層17，亦可使用矽氧化物膜、矽氮化物膜、氮氧化矽膜或其等之積層膜。
另，於上述說明中，顯示下層電極32及上層電極36分別作為共 通電極及像素電極發揮功能之例，但並未限定於此，亦可為下層電極32及上層電極36分別作為像素電極及共通電極發揮功能之構成。又，於上述說明中，例示FFS模式作為顯示模式，亦可採用其他各種顯示模式。例如，本發明之實施形態之半導體裝置亦可為VA(Vertical Alignment：垂直對準)模式或TN(Twisted Nematic：扭轉向列)模式之液晶顯示裝置用之TFT基板。該情形時，可藉由使上層電極36作為像素電極發揮功能，且使介隔介電質層34與上層電極36對向之下層電極32作為輔助電容電極發揮功能，而利用上層電極36、介電質層34及下層電極32於像素內形成透明輔助電容。
[產業上之可利用性]
根據本發明之實施形態，可提高具備氧化物半導體TFT之半導體裝置於高溫高濕下之可靠性。本發明之實施形態之半導體裝置係適合用作例如液晶顯示裝置用之TFT基板。
10A‧‧‧薄膜電晶體(TFT)
11‧‧‧基板
12g‧‧‧閘極電極
14‧‧‧閘極絕緣膜
16‧‧‧氧化物半導體層
18d‧‧‧汲極電極
18s‧‧‧源極電極
22‧‧‧保護層
22a‧‧‧開口部
24‧‧‧有機絕緣層
24a‧‧‧開口部
32‧‧‧下層電極
34‧‧‧介電質層
34a‧‧‧開口部
36‧‧‧上層電極
100A‧‧‧TFT基板
CH‧‧‧接觸孔
G‧‧‧掃描配線(閘極匯流排線)
S‧‧‧信號配線(源極匯流排線)

Claims (10)

  1. 一種半導體裝置，其包含：基板；薄膜電晶體，其受上述基板支持，且具有氧化物半導體層；有機絕緣層，其係以覆蓋上述薄膜電晶體之方式設置；下層電極，其設置於上述有機絕緣層上；介電質層，其設置於上述下層電極上；及上層電極，其設置於上述介電質層上，且具有介隔上述介電質層而與上述下層電極對向之部分；且上述介電質層係含氫量為5.33×1021個/cm3以下之矽氮化物膜。
  2. 如請求項1之半導體裝置，其中上述矽氮化物膜之介電常數為6.56以下。
  3. 如請求項1或2之半導體裝置，其中上述氧化物半導體層係包含In-Ga-Zn-O系半導體。
  4. 如請求項3之半導體裝置，其中上述In-Ga-Zn-O系半導體包含結晶質部分。
  5. 如請求項1或2之半導體裝置，其中上述氧化物半導體層係包含In-Sn-Zn-O系半導體、In-Ga-Sn-O系半導體或In-Ga-O系半導體。
  6. 如請求項1至5中任一項之半導體裝置，其中上述上層電極及上述下層電極之各者係包含透明導電材料。
  7. 一種半導體裝置之製造方法，其包含：步驟(a)，其準備基板；步驟(b)，其係於上述基板上，形成具有氧化物半導體層之薄膜電晶體；步驟(c)，其係以覆蓋上述薄膜電晶體之方式形成有機絕緣 層；步驟(d)，其係於上述有機絕緣層上形成下層電極；步驟(e)，其係於上述下層電極上形成介電質層；及步驟(f)，其係於上述介電質層上形成上層電極；且上述步驟(e)係形成矽氮化物膜作為上述介電質層之步驟，以上述矽氮化物膜之含氫量為5.33×1021個/cm3以下之成膜條件執行。
  8. 如請求項7之半導體裝置之製造方法，其中上述步驟(e)係以上述矽氮化物膜之介電常數為6.56以下之成膜條件執行。
  9. 如請求項7或8之半導體裝置之製造方法，其中上述步驟(e)係藉由電漿CVD法，使用包含SiH4、NH3及/或N2之混合氣體，以腔室內壓力為1200mTorr以上1500mTorr以下，基板溫度為180℃以上220℃以下，電極間距離為18mm以上25mm以下，SiH4相對於上述混合氣體之全流量之流量比為3%以上5%以下，功率密度為0.36W/cm2以上之成膜條件執行。
  10. 如請求項9之半導體裝置之製造方法，其中上述步驟(e)係以0.49W/cm2以下之功率密度執行。
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