CN105981148B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN105981148B
CN105981148B CN201580007934.0A CN201580007934A CN105981148B CN 105981148 B CN105981148 B CN 105981148B CN 201580007934 A CN201580007934 A CN 201580007934A CN 105981148 B CN105981148 B CN 105981148B
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tft
dielectric layer
silicon nitride
layer
nitride film
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CN105981148A (zh
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神崎庸辅
金子诚二
齐藤贵翁
高丸泰
井手启介
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Sharp Corp
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Abstract

半导体器件(100A)包括：基板(11)；由基板支承且具有氧化物半导体层(16)的TFT(10A)；以覆盖TFT的方式设置的有机绝缘层(24)；设置在有机绝缘层上的下层电极(32)；设置在下层电极上的电介质层(34)；和设置在电介质层上且具有隔着电介质层与下层电极相对的部分的上层电极(36)。电介质层是氢含量为5.33×1021个/cm3以下的硅氮化物膜。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，特别涉及具有氧化物半导 体TFT的半导体器件及其制造方法。
背景技术
近年来，有源矩阵型的液晶显示装置被广泛使用。有源矩阵型液 晶显示装置包括：对每个像素设置有薄膜晶体管(TFT)的有源矩阵基 板(也被称为“TFT基板”)；与有源矩阵基板相对的对置基板；和 设置于它们之间的液晶层。有源矩阵型液晶显示装置对经TFT向各像 素的液晶层(电学上称为“液晶电容”)施加的电压进行控制，由此 调节透射各像素的光的量，从而进行显示。在TFT基板的各像素设置 有与液晶电容电并联的辅助电容。
专利文献1中提出了用于使有源矩阵型液晶显示装置的开口率提 高的结构。在专利文献1所提出的结构中，以覆盖TFT的方式形成有 机绝缘层，通过在该有机绝缘层上将辅助电容电极、电介质层和像素 电极按照此顺序(或者与此相反的顺序)层叠而形成辅助电容。
另一方面，最近作为TFT的有源层的材料，氧化物半导体受到注 目。在专利文献2中，作为变形例2公开了将以氧化物半导体膜为有 源层的TFT用作开关元件的有源矩阵型液晶显示装置。氧化物半导体 具有比非晶硅高的迁移率，能够比将非晶硅膜作为有源层的TFT(以 下，称为“非晶硅TFT”)高速地进行动作。在本申请的说明书中， 有时将以氧化物半导体膜为有源层的TFT称为“氧化物半导体TFT”。
现有技术文献
专利文献
专利文献1：日本特开平9-171196号公报
专利文献2：日本特开2010-230744号公报
发明内容
发明要解决的技术问题
本申请的发明人对于具有氧化物半导体TFT的有源矩阵型液晶显 示装置采用了在覆盖氧化物半导体TFT的有机绝缘层上形成辅助电容 的结构后，在高温高湿下进行保存试验时，出现在液晶层中产生气泡 的问题。这种气泡的产生成为显示品质下降的原因，因此使液晶显示 装置的可靠性降低。
本发明是鉴于上述问题而完成的，其目的在于，提高具有氧化物 半导体TFT的半导体器件在高温高湿下的可靠性。
解决技术问题的技术方案
本发明的实施方式的半导体器件包括：基板；由上述基板支承且 具有氧化物半导体层的薄膜晶体管；以覆盖上述薄膜晶体管的方式设 置的有机绝缘层；设置在上述有机绝缘层上的下层电极；设置在上述 下层电极上的电介质层；和设置在上述电介质层上且具有隔着上述电 介质层与上述下层电极相对的部分的上层电极，上述电介质层是氢含 量为5.33×1021个/cm3以下的硅氮化物膜。
在某实施方式中，上述硅氮化物膜的相对介电常数为6.56以下。
在某实施方式中，上述氧化物半导体层包含In-Ga-Zn-O类半导 体。
在某实施方式中，上述In-Ga-Zn-O类半导体包含结晶部分。
在某实施方式中，上述氧化物半导体层包含In-Sn-Zn-O类半导 体、In-Ga-Sn-O类半导体或In-Ga-O类半导体。
在某实施方式中，上述上层电极和上述下层电极各自由透明的导 电材料形成。
本发明的实施方式的半导体器件的制造方法包括：准备基板的工 序(a)；在上述基板上形成具有氧化物半导体层的薄膜晶体管的工序 (b)；以覆盖上述薄膜晶体管的方式形成有机绝缘层的工序(c)； 在上述有机绝缘层上形成下层电极的工序(d)；在上述下层电极上形 成电介质层的工序(e)；和在上述电介质层上形成上层电极的工序(f)， 上述工序(e)是形成硅氮化物膜作为上述电介质层的工序，以使上述 硅氮化物膜的氢含量成为5.33×1021个/cm3以下的成膜条件来执行。
在某实施方式中，上述工序(e)以使上述硅氮化物膜的相对介电 常数成为6.56以下的成膜条件来执行。
在某实施方式中，上述工序(e)利用等离子体CVD法，使用包 含SiH4且包含NH3和/或N2的混合气体，以腔室内压力为1200mTorr 以上1500mTorr以下、基板温度为180℃以上220℃以下、电极间距离 为18mm以上25mm以下、SiH4的流量与上述混合气体的总流量之比为3％以上5％以下、功率密度为0.36W/cm2以上的成膜条件来执行。
在某实施方式中，上述工序(e)以0.49W/cm2以下的功率密度执 行。
发明效果
根据本发明的实施方式，能够提高具有氧化物半导体TFT的半导 体器件在高温高湿下的可靠性。
附图说明
图1的(a)和(b)分别是本发明的实施方式的TFT基板100A 的示意性剖视图和俯视图。
图2的(a)～(e)是示意性地表示TFT基板100A的制造工序的 工序剖视图。
图3的(a)～(c)是示意性地表示TFT基板100A的制造工序的 工序剖视图。
图4的(a)和(b)是示意性地表示TFT基板100A的制造工序 的工序剖视图。
图5是表示实施例1～4和比较例1、2各自的硅氮化物膜的相对介 电常数的计算结果的曲线图。
图6是表示实施例1～4和比较例1、2各自的氢含量的计算结果的 曲线图。
图7的(a)和(b)分别是本发明的实施方式的另一个TFT基板 100B的示意性剖视图和俯视图。
图8是示意性地表示液晶层中产生的气泡BL的图。
图9是表示发生了劣化的(阈值电压转变为负)TFT的Id-Vg特 性的例子的曲线图。
具体实施方式
首先，对于上述的气泡的产生，说明本申请的发明人所发现的内 容。
本申请的发明人对于具有氧化物半导体TFT的有源矩阵型液晶显 示装置采用了在覆盖氧化物半导体TFT的有机绝缘层上形成辅助电容 的结构后，当在高温高湿下进行保存试验时，在液晶层中产生了气泡。 图8中示意性地示出在液晶显示面板P中产生的气泡BL。气泡BL的 大小(直径)例如为约10mm。
气泡在产生的初始阶段小到看不到，但随着时间的流逝，逐渐集 中而变大。至确认到气泡的产生为止的时间，越是在水蒸汽压高的条 件下越短。例如，在50℃95％RH、60℃95％RH和70℃95％RH的条件 下，至产生气泡为止的时间按照上述顺序变短。本申请的发明人对气 泡的成分进行了分析，气泡的主成分(体积比约90％)为H2(氢)， 剩余的成分为N2(氮)、CO(一氧化碳)和CO2(二氧化碳)。
虽然产生气泡的原理还没有完全明确，但推测气泡中含有的氢是 作为构成辅助电容的电介质层形成的硅氮化物膜中含有的氢。此外， 由于在有机绝缘层上形成有辅助电容的结构中产生气泡，所以可以认 为位于硅氮化物膜之下的有机绝缘层与气泡的产生很大程度相关。
本申请发明是本申请的发明人基于所发现的上述问题而想到的。 以下，参照附图，对本发明的实施方式的半导体器件及其制造方法进 行说明，但本发明不限于例示的实施方式。本发明的实施方式的半导 体器件可以为具有氧化物半导体TFT的各种基板、各种显示装置、各 种电子设备。以下，以液晶显示装置用的TFT基板(有源矩阵基板) 为例进行说明。液晶显示装置的显示模式没有特别限定，这里举例说 明以FFS(Fringe FieldSwitching：边缘场开关)模式进行显示的液晶 显示装置中使用的TFT基板。另外，在以下的说明中，具有实质相同 的功能的构成要素，以相同的参照附图标记表示，有时省略说明。
图1的(a)和(b)示出本发明的实施方式的TFT基板100A。图 1的(a)和(b)分别是TFT基板100A的示意性剖视图和俯视图，图 1的(a)与沿着图1的(b)中的A-A’线的剖面(包含TFT10A的剖 面)对应。另外，在图1的(b)中，省略了图1的(a)中所示的结 构要素的一部分(后述的上层电极36等)。
如图1的(a)和(b)所示，TFT基板100A包括：基板(典型地， 透明基板)11；和由基板11支承的薄膜晶体管(TFT)10A。TFT10A 具有栅极电极12g、栅极绝缘膜14、氧化物半导体层16、源极电极18s 和漏极电极18d。也就是说，TFT10A为氧化物半导体TFT。
栅极电极12g与扫描配线(栅极总线)G电连接(在本实施方式 中，从扫描配线G分支)，从扫描配线G被供给扫描信号。栅极绝缘 膜14以覆盖栅极电极12g的方式形成。氧化物半导体层16为岛状， 以隔着栅极绝缘膜14与栅极电极12g重叠的方式形成。
源极电极18s与信号配线(源极总线)S电连接(本实施方式中， 从信号配线S分支)，从信号配线S被供给显示信号。源极电极18s 以与氧化物半导体层16的一部分(被称为源极区域)接触的方式设置。 与此相对，漏极电极18d以与氧化物半导体层16的另一部分(被称为 漏极区域)接触的方式设置。氧化物半导体层16的位于源极区域与漏 极区域之间的区域被称为沟道区域。以覆盖具有上述结构的TFT10A 的方式形成有保护层22。
本实施方式的TFT100A还包括有机绝缘层24、下层电极32、电 介质层34和上层电极36。
有机绝缘层24以覆盖TFT10A的方式设置在保护层22上。有机 绝缘层24典型地由感光性树脂材料形成。有机绝缘层24的厚度为例 如1μm～3μm。
下层电极32设置在有机绝缘层24上。这里，下层电极32以遍及 液晶显示装置的所有像素地连续的方式形成。不过，下层电极32没有 形成在用于将TFT10A的漏极电极18d与后述的上层电极36电连接的 接触孔CH的附近。下层电极32通过被供给共用信号(COM信号)而作为共用电极起作用。
电介质层34设置在下层电极32上。电介质层34如后所述，为硅 氮化物膜。电介质层34的厚度例如为50nm～200nm。
上层电极36设置在电介质层34上。上层电极36具有隔着电介质 层34与下层电极32相对的部分。上层电极36独立(分离)地形成于 液晶显示装置的每个像素，虽然未图示，但上层电极36具有至少1个 狭缝。上层电极36在接触孔CH中与TFT10A的漏极电极18d电连接， 作为像素电极起作用。
这里，上层电极36和下层电极32分别为由透明的导电材料形成 的透明电极。也就是说，由上层电极36和下层电极32以及位于它们 之间的电介质层34在像素内形成透明的辅助电容。在像素内透明的辅 助电容所占的面积的比例典型地为50％～80％。
另外，虽然没有图示，但在上层电极36上形成取向膜。在液晶显 示装置中，以与TFT基板100A相对的方式配置有对置基板，在TFT 基板100A与对置基板之间设置有液晶层。
在本实施方式的TFT基板100A中，电介质层34的氢含量比较少， 也就是说，是比较致密的硅氮化物膜。具体而言，电介质层34是氢含 量为5.33×1021个/cm3以下的硅氮化物膜，由此，如在后文中基于验证 结果详细叙述的那样，能够抑制液晶层中的气泡的产生。因此，能够 提高在高温高湿下的可靠性。
其中，根据本申请的发明人的研究，获知在具有氧化物半导体TFT 的TFT基板中，如果形成致密的硅氮化物膜作为电介质层，则存在得 不到希望的TFT特性的情况。具体而言，如图9所示，由于阈值电压 转变为负，TFT成为常导通元件，内置于液晶显示装置内的电路(例 如作为栅极驱动器使用的移位寄存器电路)的动作变得困难。
本申请的发明人进行了进一步的研究，结果发现了通过将硅氮化 物膜以相对介电常数不过高的方式形成，能够抑制氧化物半导体TFT 的特性劣化。具体而言，从抑制作为氧化物半导体TFT的TFT10A的 特性劣化的观点来看，优选硅氮化物膜(电介质层34)的相对介电常 数为6.56以下。通过使硅氮化物膜的氢含量为5.33×1021个/cm3以下， 并且使相对介电常数为6.56以下，能够在抑制TFT10A的特性劣化的 同时抑制液晶层中的气泡的产生。
接着，参照图2、图3和图4，对本实施方式的TFT基板100A的 制造方法进行说明。图2的(a)～(e)、图3的(a)～(c)和图4 的(a)、(b)是示意性地表示TFT基板100A的制造工序的工序剖 视图。
首先，如图2的(a)所示，准备基板11。作为基板11，能够使 用玻璃基板、具有耐热性的塑料基板等。这里，使用玻璃基板。
接着，在基板11上形成具有氧化物半导体层16的TFT10A。
具体而言，首先，如图2的(b)所示，在基板11上通过溅射法 等沉积导电膜(以下称为“栅极金属膜”)之后，利用光刻工艺对栅 极金属膜进行图案化，由此形成栅极电极12g和扫描配线G(图2的 (b)中未图示)。这里，通过将依次沉积厚20nm的氮化钽膜(TaN 膜)和厚300nm的钨膜(W膜)而得到的层叠膜图案化，形成栅极电 极12g和扫描配线G。
接着，如图2的(c)所示，利用CVD(Chemical Vapor Deposition： 化学气相沉积)法等形成覆盖栅极电极12g和栅极总线G的栅极绝缘 膜14。这里，通过依次沉积厚300nm的硅氮化物膜(SiNx膜)和厚50nm 的硅氧化物膜(SiO2膜)，形成栅极绝缘膜14。
接着，如图2的(d)所示，在栅极绝缘膜14上通过溅射法或CVD 法等沉积氧化物半导体膜之后，利用光刻工艺对氧化物半导体膜进行 图案化，由此形成岛状的氧化物半导体层16。这里，利用溅射法，沉 积厚50nm的In-Ga-Zn-O类的半导体(以下简称为“In-Ga-Zn-O类 半导体”)膜之后，对基板整体进行热处理(例如300℃以上500℃以 下，1～2小时左右)。通过进行热处理，能够恢复氧化物半导体的氧空 位。然后，利用光刻工艺将In-Ga-Zn-O类半导体膜图案化，形成岛状 的氧化物半导体层16。
像这样，氧化物半导体层16例如包含In-Ga-Zn-O类半导体。这 里，In-Ga-Zn-O类半导体是In(铟)、Ga(镓)、Zn(锌)的三元 系氧化物，In、Ga和Zn的比例(组分比)没有特别限定，例如包括 In﹕Ga﹕Zn＝2﹕2﹕1、In﹕Ga﹕Zn＝1﹕1﹕1、In﹕Ga﹕Zn＝1﹕1﹕2 等。在本实施方式中，氧化物半导体层16可以是以例如In﹕Ga﹕Zn＝1 ﹕1﹕1的比例包含In、Ga、Zn的In-Ga-Zn-O类半导体层。
具有In-Ga-Zn-O类半导体层的TFT具有高迁移率(与a-SiTFT 相比超过20倍)和低泄漏电流(与a-SiTFT相比不足100分之1)， 因此适宜用作驱动TFT和像素TFT。如果使用具有In-Ga-Zn-O类半 导体层的TFT，则能够大幅削减显示装置的耗电。
In-Ga-Zn-O类半导体可以为非晶硅，也可以包含结晶部分。作为 晶质In-Ga-Zn-O类半导体，优选c轴与层面大致垂直地取向的晶质 In-Ga-Zn-O类半导体。这种In-Ga-Zn-O类半导体的结晶结构例如公 开在日本特开2012-134475号公报中。将日本特开2012-134475号公 报的所有公开内容援引至本说明书中以供参考。
氧化物半导体层16也可以包含其它氧化物半导体来代替 In-Ga-Zn-O类半导体。例如也可以包含Zn-O类半导体(ZnO)、 In-Zn-O类半导体(IZO(注册商标))、Zn-Ti-O类半导体(ZTO)、 Cd-Ge-O类半导体、Cd-Pb-O类半导体、CdO(氧化镉)、Mg-Zn-O 类半导体、In-Sn-Zn-O类半导体(例如In2O3-SnO2-ZnO)、In-Ga-Sn-O 类半导体、In-Ga-O类半导体等。
接着，如图2的(e)所示，利用溅射法等在氧化物半导体层16 上沉积导电膜(以下称为“源极金属膜”)之后，利用光刻工艺将源 极金属膜图案化，由此形成源极电极18s、漏极电极18d和信号配线S (图2的(e)中未图示)。这里，通过将依次沉积厚30nm的钛膜(Ti膜)、厚300nm的铝膜(Al膜)和厚100nm的Ti膜而得到的层叠膜 图案化，形成源极电极18s、漏极电极18d和源极总线S。像这样，能 够在基板11上形成具有氧化物半导体层16的TFT10A。
接着，如图3的(a)所示，利用CVD(Chemical Vapor Deposition： 化学气相沉积)法等在TFT10A上沉积保护层22。这里，通过沉积厚 300nm的二氧化硅膜(SiO2膜)来形成保护层22。然后，对基板整体 进行热处理(例如250℃以上450℃以下、1～2小时左右)。通过进行 热处理，能够减小氧化物半导体层16与源极电极18s以及漏极电极18d 之间的接触电阻。此外，氧化物半导体层16的沟道区域被氧化，结果 能够减小沟道区域内的氧空位。
接着，如图3的(b)所示，以覆盖TFT10A的方式形成有机绝缘 层24。有机绝缘层24例如能够通过在保护层22上赋予正型的感光性 树脂材料(例如丙烯酸类树脂材料)后进行曝光和显影而形成。作为 有机绝缘层24的材料，也可以使用负型的感光性树脂材料。这里，使 用丙烯酸类树脂材料形成厚2.0μm的有机绝缘层24。此时，在与漏极 电极18d重叠的位置形成开口部24a。然后，以有机绝缘层24为掩模 进行蚀刻，由此在保护层22上形成开口部22a而使漏极电极18d的一 部分露出。
接着，如图3的(c)所示，在有机绝缘层24上形成下层电极32。 下层电极32能够通过在有机绝缘层24上利用溅射法等沉积透明导电 膜之后，利用光刻工艺将透明导电膜图案化而形成。作为透明导电膜 的材料，能够使用铟锡氧化物(ITO)、铟锌氧化物(IZO(注册商标)) 等。这里，通过对将厚100nm的IZO膜沉积而得到的透明导电膜进行 图案化而形成下层电极32。
接着，如图4的(a)所示，在下层电极32上形成电介质层34。 在本实施方式中，作为电介质层34利用等离子体CVD法形成硅氮化 物膜。硅氮化物膜的形成在后述那样的成膜条件下执行。这里，沉积 厚100nm的硅氮化物膜。然后，在电介质层34的一部分(与保护层 22的开口部22a和有机绝缘层24的开口部24a重叠的区域)通过蚀刻 形成开口部34a，由此形成用于将TFT10A的漏极电极18d与上层电极 36电连接的接触孔CH。
接着，如图4的(b)所示，在电介质层34上形成上层电极36。 上层电极36能够与下层电极32同样地形成。这里，通过将沉积厚 100nm的IZO膜而得到的透明导电膜图案化而形成上层电极36。上层 电极36在接触孔CH中与TFT10A的漏极电极18d电连接。
这样，得到图1的(a)和(b)所示的TFT基板100A。
这里，对形成电介质层34的工序中的硅氮化物膜的成膜条件进行 说明。在本实施方式中，形成硅氮化物膜的工序在使硅氮化物膜的氢 含量成为5.33×1021个/cm3以下的成膜条件下执行。利用等离子体CVD 法形成硅氮化物膜的情况下，作为原料气体，能够使用例如SiH4和NH3的混合气体、SiH4和N2的混合气体或者SiH4、NH3和N2的混合气体。 也就是说，能够使用包含SiH4且包含NH3和/或N2的混合气体。
作为成膜条件的参数，例如可以举出腔室内压力、基板温度、电 极间距离、SiH4的流量与混合气体的总流量之比和功率密度。通过提 高这些参数中的例如功率密度，能够使硅氮化物膜更致密(即提高相 对介电常数)而减少氢含量。
为了使硅氮化物膜的氢含量为5.33×1021个/cm3以下，形成硅氮化 物膜的工序优选在硅氮化物膜的相对介电常数成为6.25以上这样的成 膜条件下执行。具体而言，在腔室内压力为1200mTorr以上1500mTorr 以下、基板温度为180℃以上220℃以下、电极间距离为18mm以上 25mm以下、SiH4的流量与混合气体的总流量之比为3％以上5％以下 的情况下，通过使功率密度为0.36W/cm2以上，能够使硅氮化物膜的 氢含量为5.33×1021个/cm3以下。
另外，如果使功率密度过高，则存在作为氧化物半导体TFT的 TFT10A的特性劣化(例如阈值电压转变为负)或者有机绝缘层24变 色的情况。为了抑制这些问题的产生，优选功率密度为0.49W/cm2以 下。通过使功率密度为0.49W/cm2以下，能够使硅氮化物膜的相对介 电常数为6.56以下，能够在抑制TFT10A的特性劣化以及对于有机绝 缘层24的不良影响的同时抑制液晶层中的气泡的产生。
接着，使用由上述的制造方法实际制作的TFT基板100A试制液 晶显示装置，说明对其在高温高湿下的可靠性进行验证得到的结果。
<实施例1>
基于上述的制造方法制作TFT基板，使用该TFT基板制作实施例 1的液晶显示装置。硅氮化物膜的厚度为300nm。形成硅氮化物膜的工 序中的成膜条件如以下所示。
功率密度：0.36W/cm2
腔室内压力：1400mTorr
基板温度：200℃
气体流量比：SiH4﹕NH3﹕N2＝1﹕4﹕20
电极间距离：20mm
<实施例2>
除了使功率密度为0.41W/cm2以外与实施例1的液晶显示装置同 样地制作实施例2的液晶显示装置。
<实施例3>
除了使功率密度为0.45W/cm2以外与实施例1的液晶显示装置同 样地制作实施例3的液晶显示装置。
<实施例4>
除了使功率密度为0.49W/cm2以外与实施例1的液晶显示装置同 样地制作实施例4的液晶显示装置。
<比较例1>
除了使功率密度为0.28W/cm2以外与实施例1的液晶显示装置同 样地制作比较例1的液晶显示装置。
<比较例2>
除了使功率密度为0.32W/cm2以外与实施例1的液晶显示装置同 样地制作比较例2的液晶显示装置。
使用恒温恒湿器(楠本化成株式会社制FX420N)，将实施例1～4 和比较例1、2的液晶显示装置在70℃、95％RH的环境下保存300小 时后目测并且用光学显微镜确认有无气泡的产生。其结果是，在比较 例1和2的液晶显示装置中产生了气泡，而在实施例1～4中没有产生 气泡。
接着，将各液晶显示装置拆开，使用电容测定装置(惠普公司制 4284A)对各TFT基板的电介质层(硅氮化物膜)的电容进行测定， 算出相对介电常数(测定频率：1kHz)。图5中示出实施例1～4和比 较例1、2各自的硅氮化物膜的相对介电常数的计算结果。
由图5可知，实施例1～4的硅氮化物膜的相对介电常数分别为 6.25、6.35、6.48、6.56。与此相对，比较例1和2的硅氮化物膜的相 对介电常数分别为5.82、6.05。这样，确认了在实施例1～4中，与比较 例1、2相比，形成了相对介电常数高、即致密的硅氮化物膜。
此外，使用升温脱离气体分析法(Thermal Desorption Spectroscopy (TDS)：热脱附谱)法对各TFT基板的电介质层(硅氮化物膜)测 定氢脱离量，根据得到的氢脱离量算出硅氮化物膜的氢含量。氢脱离 量的测定使用了电子科学株式会社制造的TDS1200。各试料的加热通 过以1×10-7Pa的真空度和1℃/sec的升温速度使温度从80℃上升到 700℃而执行。图6中示出实施例1～4和比较例1、2各自的氢含量的 计算结果。
由图6可知，比较例1和2中，氢含量分别为7.73×1021个/cm3、 6.30×1021个/cm3，而实施例1～4中，氢含量分别为5.33×1021个/cm3、 4.63×1021个/cm3、4.20×1021个/cm3、3.60×1021个/cm3。也就是说，实施例1～4中，与比较例1和2相比，硅氮化物膜的氢含量少，均为 5.33×1021个/cm3以下。
由上述的验证结果可知，通过使作为形成辅助电容的电介质层34 的硅氮化物膜的氢含量为5.33×1021个/cm3以下，能够抑制液晶层中的 气泡的产生，能够使液晶显示装置在高温高湿下的可靠性提高。
另外，在上述的说明中，通过提高成膜条件的参数中的功率密度， 减小了硅氮化物膜的氢含量，但通过减小SiH4的流量与混合气体的总 流量之比，也能够减少硅氮化物膜的氢含量。不过，通过功率密度的 调整来控制硅氮化物膜的氢含量的方式在维持基板面内的膜厚的均匀 性方面优选。
接着，说明本发明的实施方式的TFT基板100A的变形例。在图7 的(a)和(b)中示出本发明的实施方式的另一个TFT基板100B。图 7的(a)和(b)分别是TFT基板100B的示意性剖视图和俯视图，图 7的(a)与沿着图7的(b)中的A-A’线的剖面(包含TFT10B的剖 面)对应。另外，在图7的(b)中，省略了图7的(a)中示出的构 成要素的一部分(后述的上层电极36等)。
如图7的(a)和(b)所示，在TFT基板100B中，TFT10B具有 以覆盖氧化物半导体层16的沟道区域的方式设置的蚀刻阻挡层17。通 过设置蚀刻阻挡层17，能够减少氧化物半导体层16中产生的工艺损 伤。此外，如果蚀刻阻挡层17包含硅氧化物膜等的氧化物膜，则在氧化物半导体中产生氧空位的情况下，能够由氧化物膜中包含的氧恢复 氧空位，因此能够减少氧化物半导体的氧空位。
蚀刻阻挡层17能够通过在氧化物半导体层16的形成后、源极电 极18s和漏极电极18d的形成前，利用例如CVD法在氧化物半导体层 16上沉积保护膜，利用光刻工艺将该保护膜图案化而形成。图案化以 至少氧化物半导体层16中的成为沟道区域的区域被蚀刻阻挡层17覆 盖的方式执行。这里，作为蚀刻阻挡层17，使用厚150nm的SiO2膜。 作为蚀刻阻挡层17，可以使用硅氧化物膜、硅氮化物膜、氧化氮化硅 膜或它们的层叠膜。
另外，在上述的说明中，示出了下层电极32和上层电极36分别 作为共用电极和像素电极起作用的例子，但不限于此，也可以为下层 电极32和上层电极36分别作为像素电极和共用电极起作用的结构。 此外，在上述的说明中，作为显示模式例示了FFS模式，但也可以采 用其它各种显示模式。例如，本发明的实施方式的半导体器件可以为 VA(VerticalAlignment：垂直取向)模式、TN(Twisted Nematic：扭 转向列)模式的液晶显示装置用的TFT基板。在此情况下，通过使上 层电极36作为像素电极起作用，使隔着电介质层34与上层电极36相 对的下层电极32作为辅助电容电极起作用，能够由上层电极36、电介 质层34和下层电极32在像素内形成透明的辅助电容。
产业上的可利用性
根据本发明的实施方式，能够提高具有氧化物半导体TFT的半导 体器件在高温高湿下的可靠性。本发明的实施方式的半导体器件能够 适宜地用作例如液晶显示装置用的TFT基板。
符号说明
10A、10B 薄膜晶体管(TFT)
11 基板
12g 栅极电极
14 栅极绝缘膜
16 氧化物半导体层
17 蚀刻阻挡层
18s 源极电极
18d 漏极电极
22 保护层
24 有机绝缘层
32 下层电极
34 电介质层
36 上层电极
100A、100B TFT基板
G 扫描配线(栅极总线)
S 信号配线(源极总线)。

Claims (8)

1.一种半导体器件，其特征在于，包括：
基板；
由所述基板支承且具有氧化物半导体层的薄膜晶体管；
以覆盖所述薄膜晶体管的方式设置的有机绝缘层；
设置在所述有机绝缘层上的下层电极；
设置在所述下层电极上的电介质层；和
设置在所述电介质层上且具有隔着所述电介质层与所述下层电极相对的部分的上层电极，
所述电介质层是氢含量为5.33×1021个/cm3以下的硅氮化物膜，
所述硅氮化物膜的相对介电常数为6.56以下。
2.如权利要求1所述的半导体器件，其特征在于：
所述氧化物半导体层包含In-Ga-Zn-O类半导体。
3.如权利要求2所述的半导体器件，其特征在于：
所述In-Ga-Zn-O类半导体包含结晶部分。
4.如权利要求1所述的半导体器件，其特征在于：
所述氧化物半导体层包含In-Sn-Zn-O类半导体、In-Ga-Sn-O类半导体或In-Ga-O类半导体。
5.如权利要求1至4中任一项所述的半导体器件，其特征在于：
所述上层电极和所述下层电极各自由透明的导电材料形成。
6.一种半导体器件的制造方法，其特征在于，包括：
准备基板的工序(a)；
在所述基板上形成具有氧化物半导体层的薄膜晶体管的工序(b)；
以覆盖所述薄膜晶体管的方式形成有机绝缘层的工序(c)；
在所述有机绝缘层上形成下层电极的工序(d)；
在所述下层电极上形成电介质层的工序(e)；和
在所述电介质层上形成上层电极的工序(f)，
所述工序(e)是形成硅氮化物膜作为所述电介质层的工序，以使所述硅氮化物膜的氢含量成为5.33×1021个/cm3以下的成膜条件来执行，
所述工序(e)以使所述硅氮化物膜的相对介电常数成为6.56以下的成膜条件来执行。
7.如权利要求6所述的半导体器件的制造方法，其特征在于：
所述工序(e)利用等离子体CVD法，使用包含SiH4且包含NH3和/或N2的混合气体，以腔室内压力为1200mTorr以上1500mTorr以下、基板温度为180℃以上220℃以下、电极间距离为18mm以上25mm以下、SiH4的流量与所述混合气体的总流量之比为3％以上5％以下、功率密度为0.36W/cm2以上的成膜条件来执行。
8.如权利要求7所述的半导体器件的制造方法，其特征在于：
所述工序(e)以0.49W/cm2以下的功率密度执行。
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