TW201535594A - 半導體裝置之製造方法及半導體裝置 - Google Patents

半導體裝置之製造方法及半導體裝置 Download PDF

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Publication number
TW201535594A
TW201535594A TW103134881A TW103134881A TW201535594A TW 201535594 A TW201535594 A TW 201535594A TW 103134881 A TW103134881 A TW 103134881A TW 103134881 A TW103134881 A TW 103134881A TW 201535594 A TW201535594 A TW 201535594A
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Taiwan
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layer
insulating layer
semiconductor device
conductive layer
manufacturing
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TW103134881A
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English (en)
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Atsuko Kawasaki
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Toshiba Kk
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Publication of TW201535594A publication Critical patent/TW201535594A/zh

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Abstract

本發明係一種半導體裝置之製造方法及半導體裝置，其中，如根據實施形態之半導體裝置之製造方法，形成第1導電層及第1絕緣層則從表面露出之第1配線層，形成第2導電層及第2絕緣層則從表面露出之第2配線層，經由前述第1絕緣層表面之中，將包含前述第1導電層周圍之一部分範圍，作為較前述第1導電層表面為低之時，於前述第1絕緣層表面，形成第1非接合面，接合前述第1導電層表面與前述第2導電層表面之同時，接合除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面。

Description

半導體裝置之製造方法及半導體裝置 〔關連申請之參照〕
本申請係享有在2013年12月11日所提出申請之日本國專利申請號碼2013-256070之優先權的利益，其日本國專利申請之全內容係在本申請中加以援用。
本實施形態係一般半導體裝置之製造方法及半導體裝置。
伴隨著近年來之半導體積體電路之高集成化及高性能，具有層積配線於垂直方向之多層配線層的半導體裝置之研究則持續進展。
作為此種半導體裝置所具有之多層配線層之製造方法，知道有以下的方法。首先，將第1配線層，形成於第1半導體基板上。第1配線層係具有經由CMP(Chemical Mechanical Polishing)法而加以研磨之表 面。從此表面係露出有配線或貫穿孔導電體等之導電層，及絕緣層。接著，將第2配線層，形成於第2半導體基板上。第2配線層係具有經由CMP法而加以研磨之表面。從此表面係露出有配線或貫穿孔導電體等之導電層，及絕緣層。接著，於第1半導體基板及第2半導體基板，施加壓接負載，固態接合(Solid State Bonding)第1配線層之表面與第2配線層之表面。由如此作為，加以製造多層配線層。
具有如此作為所製造之多層配線層的半導體裝置係經由使第1配線層之表面與第2配線層之表面固態接合而加以製造之故，而可容易地防止電磁放射干擾。更且，具有如此加以製造之多層配線層的半導體裝置係經由固態接合貫穿孔導電體彼此而加以製造之故，可將配線縮短，且容易作為者。
在上述之半導體裝置之製造方法中，確實地使從第1配線層之表面露出之導電層，和從第2配線層之表面露出之導電層接合，可製造信賴性更高之半導體裝置之製造方法為佳。
作為欲解決本發明之課題，係提供信賴性高之半導體裝置之製造方法及半導體裝置者。
一實施形態之半導體裝置之製造方法係其特徵為具有第1導電層及第1絕緣層，將前述第1導電層及 前述第1絕緣層則從表面露出之第1配線層，形成於第1基板上，具有第2導電層及第2絕緣層，將前述第2導電層及前述第2絕緣層則從表面露出之第2配線層，形成於第2基板上，而前述第1絕緣膜之表面之中，經由將包含前述第1導電層之周圍的一部分範圍，作為較前述第1導電層之表面為低之時，於前述第1絕緣層之表面，形成第1非接合面，電性連接前述第1導電層表面與前述第2導電層表面之同時，接合除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面者。
另外的實施形態之半導體裝置係其特徵為具有第1導電層及第1絕緣層，於前述第1絕緣層表面之中，包含前述第1導電層周圍之一部分範圍，具備：具有使前述第1導電層突出為凸狀之第1非接合面之第1配線層，和具有除了加以接合於前述第1導電層表面之第2導電層及前述第1非接合面之加以接合於前述第1絕緣層表面之第2絕緣層的第2配線層者。
如根據上述構成之半導體裝置之製造方法及半導體裝置，可提供信賴性高之半導體裝置之製造方法及半導體裝置者。
10、30、100‧‧‧半導體裝置
11‧‧‧多層配線層
11a、31a、111a‧‧‧下層部
12a‧‧‧第1基板
13a‧‧‧第1配線層
14a、34a、114a‧‧‧第1絕緣層
15a‧‧‧第1配線
16a、116a‧‧‧第1貫穿孔導電體
11b、31b、111b‧‧‧上層部
12b‧‧‧第2基板
13b‧‧‧第2配線層
14b、34b、114b‧‧‧第2絕緣層
15b‧‧‧第2配線
16b、116b‧‧‧第2貫穿孔導電體
Sa‧‧‧第1接合面
Sb‧‧‧第2接合面
22‧‧‧第1半導體晶圓
22a‧‧‧第1絕緣體
23a‧‧‧第2絕緣體
24a‧‧‧複數之貫穿孔
25a‧‧‧導電層
26a‧‧‧碟狀部
27a‧‧‧光阻層
28、38‧‧‧空間
121b‧‧‧第2半導體晶圓
圖1係模式性地顯示經由有關第1實施例之半導體裝置之製造方法而加以製造之半導體裝置之要部的剖面圖。
圖2係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖3係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖4係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖5係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖6係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖7係從上側而視在圖6所示之工程的第1半導體晶圓之平面圖。
圖8係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖9係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖10係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖11係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖12係模式性地顯示第1絕緣層與第2絕緣層之接合範圍及非接合範圍的平面圖。
圖13係為了說明有關第1實施例之半導體裝置之製造方法之對應圖1的剖面圖。
圖14係為了說明有關比較例之半導體裝置之製造方法的剖面圖。
圖15係為了說明有關比較例之半導體裝置之製造方法的剖面圖。
圖16係為了說明有關比較例之半導體裝置之製造方法的剖面圖。
圖17係為了說明有關第2實施例之半導體裝置之製造方法的剖面圖。
圖18係為了說明有關第2實施例之半導體裝置之製造方法的剖面圖。
圖19係為了說明有關第2實施例之半導體裝置之製造方法的剖面圖。
圖20係為了說明有關第2實施例之半導體裝置之製造方法的剖面圖。
圖21係從上側而視加以形成有關變形例之光阻層的第1半導體晶圓之平面圖。
圖22係模式性地顯示在形成有關變形例之光阻層之後的工程，固態接合下層部與上層部時之第1絕緣層與第2絕緣層之接合範圍及非接合範圍的平面圖。
於以下，對於有關本實施例之半導體裝置之製造方法及半導體裝置加以說明。
(第1實施例)
圖1係模式性地顯示經由有關實施例之半導體裝置之製造方法而加以製造之半導體裝置10之要部的剖面圖。圖1所示之半導體裝置10係具有：經由第1部分之下層部11a，和第2部分之上層部11b則相互加以固態接合而加以形成之多層配線層11。
即，第1部分之下層部11a係具有第1基板12a及加以形成於第1基板12a上之第1配線層13a。第1配線層13a係具有第1配線15a及第1貫穿孔導電體16a等之第1導電層，及第1絕緣層14a。第1導電層係於第1絕緣層14a內，加以形成於之中。然而，圖示之第1配線15a係第1配線層13a之最上層配線，而第1配線層13a係具有包含此最上層配線15a之多層配線構造亦可。
從第1配線層13a之表面係露出有絕緣範圍之第1絕緣層14a，及作為導電範圍，例如第1貫穿孔導電體16a。經由第1絕緣層14a所構成之絕緣範圍係在其一部分中成為凹狀，而導電範圍之第1貫穿孔導電體16a係從絕緣範圍之凹狀的範圍，突出為凸狀而露出。然而，在以下的說明中，第1絕緣層14a之凹狀的範圍之底面，稱作第1非接觸面。第1貫穿孔導電體16a係從第1非接觸面突出成凸狀。
經由如此之絕緣範圍及導電範圍，即經由除了第1非接觸面之第1絕緣層14a的表面，及第1貫穿孔導電體16a之上端表面，加以構成第1接合面Sa。
第2部分之上層部11b亦同樣地，具有第2基板12b及加以形成於第2基板12b上之第2配線層13b。第2配線層13b係具有第2配線15b及第2貫穿孔導電體16b等之第2導電層，及第2絕緣層14b。第2導電層係加以形成於第2絕緣層14b內。然而，圖示之第2配線15b係第2配線層13b之最上層配線，而第2配線層13b係具有包含此最上層配線15b之多層配線構造亦可。
從第2配線層13b之表面係露出有絕緣範圍之第2絕緣層14b，及作為導電範圍，例如第2貫穿孔導電體16b。經由第2絕緣層14b所構成之絕緣範圍係在其一部分中成為凹狀，而導電範圍之第2貫穿孔導電體16b係從絕緣範圍之凹狀的範圍，突出為凸狀而露出。然而，在以下的說明中，第2絕緣層14b之凹狀的範圍之底面，稱作第2非接觸面。第2貫穿孔導電體16b係從第2非接觸面突出成凸狀。
經由如此之絕緣範圍及導電範圍，即經由除了第2非接觸面之第2絕緣層14b的表面，及從此表面露出之第2貫穿孔導電體16b之上端表面，加以構成第2接合面Sb。
並且，圖1所示之半導體裝置10之多層配線層11係經由下層部11a之第1接合面Sa，和上層部11b之第2接合面Sb則固態接合之同時，下層部11a之第1接合面Sa之導電範圍(第1貫穿孔導電體16a之上端表面)，和上層部11b之第2接合面Sb之導電範圍(第2 貫穿孔導電體16b之上端表面)則固態接合，下層部11a之第1非接合面，和上層部11b之第2非接合面則相互隔離之時而加以形成。其結果，下層部11a與上層部11b係作為呈加以形成有空間於第1非接合面與第2非接合面之間而接合。
然而，圖示係雖省略，但對於下層部11a與上層部11b，係各實際上製作有電晶體，電容器等之半導體元件。
如此之多層配線層11係作為電性連接例如加以設置於上層部11b之將光受光之感測器部，和加以設置於下層部11a之處理在感測器部所得到之信號的邏輯電路之配線層而加以利用。
於以下，參照圖2~圖13，對於圖1所示之半導體裝置10之製造方法加以說明。除了圖7，圖12之圖2~圖13係各為為了說明有關第1實施例之半導體裝置10之製造方法的對應圖1之剖面圖。圖7係從上側而視在圖6所示之工程之第1半導體晶圓的平面圖，而圖12係模式性地顯示第1絕緣層與第2絕緣層之接合範圍及非接合範圍之平面圖。
首先，製造第1部分之下層部11a(圖1)。首先，如圖2所示地，於第1半導體晶圓21a之表面上，形成成為第1絕緣層14a(圖1)之一部分之第1絕緣體22a，再於第1絕緣體22a之表面，形成作為導電層之一例的第1配線15a。第1半導體晶圓21a係之後成為第1 基板12a(圖1)之第1晶圓的一例。第1半導體晶圓21a係由矽等所成，第1配線15a係由銅，鋁合金等之金屬，摻雜不純物之多結晶矽，矽化物等所成。並且，第1絕緣體22a係由氧化矽，氮化矽等所成。
然而，圖2所示之2條的點線間之範圍D係在後述的切割工程中所切斷之切斷範圍D(切割線D)。上述之第1配線15a係實際上各加以形成於經由格子狀的切割線D所區劃之第1絕緣體22a的表面之各範圍。
接著，如圖3所示，於包含第1配線15a之第1絕緣體22a的表面上，形成氧化矽，氮化矽等所成之第2絕緣體23a。之後，使用光微影法與乾蝕刻的技術，於第2絕緣體23a，形成包含到達至第1配線15a之貫穿孔的複數之貫穿孔24a。
然而，經由上述之第1絕緣體22a，及層積於此之第2絕緣體23a，加以形成有第1絕緣層14a。
接著，如圖4所示，被覆第1絕緣層14a之全體，而完全填滿複數之貫穿孔24a內地，形成例如由銅所成之導電層25a。
接著，如圖5所示，至第1絕緣層14a的表面露出為止，經由CMP法而研磨導電層25a，將包含導電層25a之第1絕緣層14a的表面進行平坦化。經由此工程，埋入貫穿孔24a內之導電層25a係成為第1貫穿孔導電體16a。
在此工程中，第1貫穿孔導電體16a之上端 表面及第1絕緣層14a之表面係成為略平坦，但由銅等所成之第1貫穿孔導電體16a係硬度則較氧化矽，氮化矽等所成之第1絕緣層14a為低之故，經由CMP，第1貫穿孔導電體16a之表面則較第1絕緣層14a之表面凹陷成皿狀而變低。即，於第1貫穿孔導電體16a之上端表面，加以形成有凹陷成皿狀之碟狀部26a。
經由此工程，於第1部份之下層部11a的第1配線層13a的表面，加以形成有露出有第1絕緣層14a之絕緣範圍，及露出有第1貫穿孔導電體16a之上端表面(碟狀部26a)之導電範圍所成之第1接合面Sa。
接著，如圖6所示，於從第1接合面Sa露出之絕緣範圍上之中，切割線D上及其周邊部上(即，第1絕緣層14a之周邊部表面上)，形成光阻層27a。光阻層27a係經由於包含第1貫穿孔導電體16a之表面的第1絕緣層14a之表面，塗佈光阻劑材料，歷經曝光，顯像工程，除去光阻劑材料之不需要的部分之時而加以形成。
在此，如圖7所示，切割線D係一般，對於第1半導體晶圓21a而言，加以形成為格子狀。隨之，所形成之光阻層27a亦同樣地，於加以形成於第1半導體晶圓21a上之第1絕緣層14a的表面上，加以形成為格子狀。然而，實際上，從由光阻層27a所圍住之範圍係除了第1絕緣層14a以外，第1貫穿孔導電體16a亦露出，但在圖7中係省略之。
接著，如圖8所示，經由反應性離子蝕刻 (Reactive Ion Etching)法，從光阻層27a所露出之第1絕緣層14a的中央部表面(從光阻層27a露出之第1接合面Sa的絕緣範圍)之高度則至成為與第1貫穿孔導電體16a之碟狀部26a的底部略同一高度為止，選擇性地蝕刻第1絕緣層14a。反應性離子蝕刻係為選擇性，且有向異性之故，細微加工第1絕緣層14a，而可將第1絕緣層14a之中央部表面的高度，作為略均等於碟狀部26a之底部高度。
經由此工程，第1接合面Sa之絕緣範圍之中，包含各第1貫穿孔導電體16a周圍之一部分範圍的中央部高度則較導電範圍之各第1貫穿孔導電體16a之上端表面下降，於第1接合面Sa之絕緣範圍之一部分範圍，加以形成有凹狀範圍之底面的第1非接合面。並且，各第1貫穿孔導電體16a係從第1非接合面突出成凸狀。
然而，在此蝕刻工程中，第1貫穿孔導電體16a則如從其周圍之第1絕緣層14a的表面(第1非接合面)突出成凸狀即可。隨之，從光阻層27a露出之第1絕緣層14a的表面高度則呈成為較第1貫穿孔導電體16a之碟狀部26a的底部，例如為低地進行蝕刻亦可。
最後，如圖9所示，例如經由灰化等而除去光阻層27a。由如此作為，加以形成具備經由除了第1非接合面之第1絕緣層14a之表面而加以構成之絕緣範圍，及經由從第1非接合面突出成凸狀之第1貫穿孔導電體16a的上端表面而加以構成之導電範圍所成之第1接合面 Sa的半導體裝置10之下層部11a。
接著，歷經與半導體裝置10之下層部11a之製造工程同樣之工程，如圖10所示，形成具備經由除了第2非接合面之第2絕緣層14b之表面而加以構成之絕緣範圍，及經由從第2非接合面突出成凸狀之第2貫穿孔導電體16b的上端表面而加以構成之導電範圍所成之第2接合面Sb的半導體裝置10之上層部11b。然而，在所形成之上層部11b中，對於第2貫穿孔導電體16b的上端表面，係加以形成碟狀部26b。
接著，對於下層部11a之第1接合面Sa及上層部11b之第2接合面Sb，進行表面處理。即，活性化第1，第2之接合面Sa、Sb。之後，如圖11所示，在真空或非活性氣體之環境中，於第1非接合面與第2非接合面之間，加以形成空間28，且呈第1接合面Sa之絕緣範圍與第2接合面Sb之絕緣範圍則進行整合，而第1接合面Sa之導電範圍與第2接合面Sb之導電範圍則進行整合地，對向配置下層部11a與上層部11b。並且，於下層部11a之第1半導體晶圓21a及上層部11b之第2半導體晶圓21b，例如以依據150℃程度之低溫條件，施加壓接負載F、F，使第1貫穿孔導電體16a與第2貫穿孔導電體16b固態接合之同時，使第1絕緣層14a的周邊部與第2絕緣層14b的周邊部作氫結合。之後，對於結合之半導體晶圓21a，21b，進行例如400℃程度之熱處理。由如此作為，第1貫穿孔導電體16a與第2貫穿孔導電體16b係加 以金屬結合，而第1絕緣層14a與第2絕緣層14b係加以共有結合。在此，第1接合面Sa之導電範圍係對於其周圍的第1接合面Sa之絕緣範圍而言成為凸，而第2接合面Sb之導電範圍係對於其周圍的第2接合面Sb之絕緣範圍而言成為凸之故，可確實地固態結合構成兩者之導電範圍的第1貫穿孔導電體16a與第2貫穿孔導電體16b者。並且，相互固態結合之第1貫穿孔導電體16a之一部分與第2貫穿孔導電體16b之一部分係加以配置於空間28內。
在此，如圖11及圖12所示，第1絕緣層14a的周邊部與第2絕緣層14b的周邊部則共有結合之結合範圍J，係沿著切割線D而加以設置成格子狀。即，包含第1絕緣層14a之第1非接觸面及第2絕緣層14b之第2非接觸面之非接合範圍NJ係成為由兩者之結合範圍J所圍住之範圍。
最後，如圖13所示，沿著切割線D而切斷下層部11a及上層部11b。即，切斷切割線D上之第1半導體晶圓21a，第1絕緣層14a，第2絕緣層14b，第2半導體晶圓21b。經由此，一次加以製造複數之半導體裝置10。在如此作為所製造之半導體裝置10中，對於第1絕緣層14a與第2絕緣層14b之非接合範圍NJ係加以形成有空間28，但此空間28係由第1絕緣層14a與第2絕緣層14b之接合範圍J所圍住。
如以上說明地，在有關實施例之半導體裝置 10之製造方法及半導體裝置10中，將下層部11a之導電層的第1貫穿孔導電體16a，從加以設置於其周圍之第1絕緣層14a之第1非接觸面，突出成凸狀的同時，將上層部11b之導電層的第2貫穿孔導電體16b，從加以設置於其周圍之第2絕緣層14b之第2非接觸面，突出成凸狀之後，固態接合此等。隨之，即使經由CMP法而於第1貫穿孔導電體16a之上端面，加以形成有碟狀部26a，而於第2貫穿孔導電體16b之上端面，加以形成有碟狀部26b，亦可確實地使此等接合。隨之，可確實地進行第1貫穿孔導電體16a與第2貫穿孔導電體16b之電性的接合，而製造信賴性優越之半導體裝置10者。
另外，在有關實施例之半導體裝置10之製造方法及半導體裝置10中，在接合下層部11a與上層部11b時，固態接合下層部11a之第1絕緣層14a的周邊部表面，和上層部11b之第2絕緣層14b的周邊部表面。並且，第1貫穿孔導電體16a與第2貫穿孔導電體16b係在由第1絕緣層14a與第2絕緣層14b之接合範圍J所圍住之非接合範圍NJ內(第1非接合面與第2非接合面之間的空間28內)，相互加以固態接合。隨之，在所製造之半導體裝置10中，相互加以固態接合之第1貫穿孔導電體16a及第2貫穿孔導電體16b係於空間28內，呈由第1絕緣層14a與第2絕緣層14b之接合範圍J所圍繞地加以配置。因此，抑制了經由從半導體裝置10之外部侵入有藥液之時，而對於第1貫穿孔導電體16a及第2貫穿孔 導電體16b產生不良之情況。
更且，在有關實施例之半導體裝置10之製造方法及半導體裝置10中，在最終工程的切割工程中所切斷之範圍D係第1絕緣層14a及第2絕緣層14b之中，兩者所共有結合之接合範圍J。隨之，在切割工程中，亦加以抑制第1絕緣層14a或第2絕緣層14b產生破損之情況(晶片刮傷)。
如以上說明地，在有關實施例之半導體裝置10之製造方法及半導體裝置10中，加以抑制經由藥液之侵入的第1貫穿孔導電體16a及第2貫穿孔導電體16b的不良，而亦抑制在切割工程中，第1絕緣層14a或第2絕緣層14b產生破損之情況(晶片刮傷)。隨之，可產率佳地製造信賴性更優越之半導體裝置10者。
又，在有關實施例之半導體裝置10之製造方法及半導體裝置10中，下層部11a之第1絕緣層14a的表面，和上層部11b之第2絕緣層14b的表面則加以共有結合之故，堅固地接合下層部11a與上層部11b。隨之，可製造信賴性更優越之半導體裝置10者。
對此，將單純地可確實地使第1貫穿孔導電體與第2貫穿孔導電體固態接合之半導體裝置的製造方法，作為有關本實施例之半導體裝置之製造方法的比較例，參照圖14~圖16加以說明。圖14~圖16係為了說明各有關比較例之半導體裝置之製造方法的剖面圖。然而，在圖14~圖16中，對於與本實施例同一處，附上同一的 符號。
在有關比較例之半導體裝置的下層部111a之製造方法中，歷經圖2~圖5所示之各工程，經由CMP法而平坦化第1貫穿孔導電體116a所露出之第1絕緣層114a的表面之後，於第1絕緣層114a的表面上，未形成光阻層，而如圖14所示地，蝕刻第1絕緣層114a之表面全體，使第1貫穿孔導電體116a，突出成凸狀。
另外，圖示係雖省略，但在上層部111b之製造中，亦同樣地，經由CMP法而平坦化第2貫穿孔導電體116b所露出之第2絕緣層114b的表面之後，於第2絕緣層114b的表面上，未形成光阻層，蝕刻第2絕緣層114b之表面全體，使第2貫穿孔導電體116a，突出成凸狀。
之後，從第1絕緣層114a，第1貫穿孔導電體116a則突出成凸狀之下層部111a的表面，及從第2絕緣層114b，第2貫穿孔導電體116b則突出成凸狀之上層部111b的表面，在真空中，進行清淨化處理而做呈清淨表面，如圖15所示，在真空或非活性氣體的環境中，第1貫穿孔導電體116a與第2貫穿孔導電體116b則呈整合地，對向配置下層部111a與上層部111b。並且，於下層部111a之第1半導體晶圓121a及上層部111b之第2半導體晶圓121b，施加壓接負載F、F，固態接合第1貫穿孔導電體116a與第2貫穿孔導電體116b。
並且，如圖16所示，在最終工程中，沿著切 割線D而切斷下層部111a及上層部111b，一次製造複數之半導體裝置100。
在有關如此之比較例的半導體裝置100之製造方法中，將下層部111a之導電層的第1貫穿孔導電體116a，從其周圍之第1絕緣層114a突出成凸狀之同時，將上層部111b之導電層的第2貫穿孔導電體116b，從其周圍之第2絕緣層114b突出成凸狀之後，固態接合此等。隨之，可確實地使第1貫穿孔導電體116a與第2貫穿孔導電體116b接合者。
但在如此所製造之半導體裝置100中，如圖16所示，於第1絕緣層114a與第2絕緣層114b之間，產生有間隙128。並且，此間隙128係從裝置100的側面所露出。隨之，從半導體裝置100之外部侵入有藥液之時，而對於第1貫穿孔導電體116a及第2貫穿孔導電體116b產生不良之情況。隨之，經由有關此比較例之製造方法所製造之半導體裝置100係與經由有關本實施例之半導體裝置之製造方法所製造之半導體裝置10做比較，對於信賴性不佳。更且，在切割線D上，於第1絕緣層114a與第2絕緣層114b之間產生有間隙128之故，在沿著切割線D而切斷第1絕緣層114a及第2絕緣層114b時，第1絕緣層114a或第2絕緣層114b則產生破損(產生晶片刮傷)。隨之，經由有關此比較例之製造方法所製造之半導體裝置100係與經由有關本實施例之半導體裝置之製造方法所製造之半導體裝置10做比較，對於信賴性 不佳，另外，製造產率亦下降。
即，如根據有關本實施例之半導體裝置10之製造方法，與有關比較例之半導體裝置100之製造方法做比較，可產率佳地製造對於信賴性更優越之半導體裝置。
在有關第1實施例之半導體裝置10之製造方法及半導體裝置10中，使將下層部11a之第1貫穿孔導電體16a，從其周圍之第1絕緣層14a(第1非接觸面)突出成凸狀之同時，使上層部11b之第2貫穿孔導電體16b，從其周圍之第2絕緣層14b(第2非接觸面)突出成凸狀之後，固態接合此等。但，僅使一方的貫穿孔導電體，從其周圍的絕緣層突出成凸狀，而另一方之貫穿孔導電體係未從其周圍的絕緣層作為突出，亦可確實地固態接合兩者。於以下，說明其製造方法。
(第2實施例)
於以下，參照圖17~圖20，對於有關第2實施例之半導體裝置之製造方法加以說明。圖17~圖20係為了說明各有關第2實施例之半導體裝置之製造方法的剖面圖。然而，在各圖中，對於與有關第1實施例之半導體裝置同一部分，係附上同一的符號。
在此製造方法中，第1部分之下層部31a係歷經圖2~圖7所示之各工程，而於第1絕緣層34a之表面上，形成光阻層27a之後，如圖17所示，蝕刻從光阻層27a露出之第1絕緣層34a。至與第1貫穿孔導電體 16a之碟狀部26a底部相同程度或第1絕緣層34a之高度變低為止，進行蝕刻。經由此，於第1貫穿孔導電體16a周圍之第1絕緣層34a，加以形成第1非接觸面。
並且，進行如此之蝕刻工程之後，除去光阻層27a。從除去光阻層27a之後的第1絕緣層34a表面(第1非接觸面)，係第1貫穿孔導電體16a則大突出。如此之除了第1非接觸面之第1絕緣層34a的表面所成之絕緣範圍，及第1貫穿孔導電體16a之上端表面所成之導電範圍則成為第1接合面Sa’。
另一方面，在第2部分之上層部31b中，係如圖18所示，至第2絕緣層34b的表面露出為止，經由CMP法而研磨導電層(成為第2貫穿孔導電體16b之導電層)，而平坦化第2貫穿孔導電體16b則從表面露出之第2絕緣層34b的表面。並且，在此狀態之第2絕緣層34b的表面所成之絕緣範圍，及第2貫穿孔導電體16b之上端表面所成之導電範圍則成為第2接合面Sb’。
如此作為而形成第1，第2接合面Sa’，Sb’之後，於此等之接合面Sa’，Sb’，進行表面處理。即，活性化第1，第2之接合面Sa’，Sb’。之後，如圖19所示，在真空或非活性氣體之環境中，於第1非接合面與第2接合面Sb’之間，加以形成空間38，且呈第1接合面Sa’之絕緣範圍與第2接合面Sb’之絕緣範圍則進行整合，而第1接合面Sa’之導電範圍與第2接合面Sb’之導電範圍則進行整合地，對向配置下層部31a與上層部31b。並且，於 下層部31a之第1半導體晶圓21a及上層部31b之第2半導體晶圓21b，例如以依據150℃程度之低溫條件，施加壓接負載F、F，使第1貫穿孔導電體16a與第2貫穿孔導電體16b固態接合之同時，使第1絕緣層34a的周邊部與第2絕緣層34b的周邊部作氫結合。之後，對於接合之半導體晶圓21a，21b，進行例如400℃程度之熱處理。由如此作為，第1貫穿孔導電體16a與第2貫穿孔導電體16b係加以金屬結合，而第1絕緣層34a與第2絕緣層34b係加以共有結合。在此，第1接合面Sa’之導電範圍係對於其周圍之第1接合面Sa’之絕緣範圍而言成為凸之故，可確實地固態接合構成第1接合面Sa’之導電範圍的第1貫穿孔導電體16a，和構成第2接合面Sb’之導電範圍的第2貫穿孔導電體16b者。並且，相互固態接合之第1貫穿孔導電體16a之一部分與第2貫穿孔導電體16b之一部分係加以配置於空間38內。
並且，如圖20所示，在最終工程中，沿著切割線D而切斷下層部31a及上層部31b。經由此，一次加以製造複數之半導體裝置30。在如此作為所製造之半導體裝置30中，對於第1絕緣層34a與第2絕緣層34b之非接合範圍NJ係加以形成有空間38，但此空間38係由第1絕緣層34a與第2絕緣層34b之接合範圍J所圍住。
在有關以上說明之第2實施例的半導體裝置30之製造方法及半導體裝置30中，使下層部31a之導電層的第1貫穿孔導電體16a，從加以設置於其周圍的第1 絕緣層34a之第1非接觸面，突出成凸狀之後，固態接合此第1貫穿孔導電體16a，和加以形成有碟狀部26b，從第2絕緣體34b的表面僅凹陷變低成皿狀之第2貫穿孔導電體16b。隨之，即使經由CMP法而各於第1貫穿孔導電體16a之上端面，及第2貫穿孔導電體16b之上端面，加以形成有碟狀部26a，26b，亦可確實地使此等接合。因此，可確實地進行第1貫穿孔導電體16a與第2貫穿孔導電體16b之電性的接合，而製造信賴性優越之半導體裝置30者。
另外，在有關實施例之半導體裝置30之製造方法及半導體裝置30中，亦在接合下層部31a與上層部31b時，固態接合下層部31a之第1絕緣層34a的周邊部表面，和上層部31b之第2絕緣層34b的周邊部表面。並且，第1貫穿孔導電體16a與第2貫穿孔導電體16b係在由第1絕緣層34a與第2絕緣層34b之接合範圍J所圍住之非接合範圍NJ內(經由第1絕緣層34a與第2絕緣層34b所圍住的空間38內)，相互加以固態接合。隨之，在所製造之半導體裝置30中，相互加以固態接合之第1貫穿孔導電體16a及第2貫穿孔導電體16b係於空間38內，呈由第1絕緣層34a與第2絕緣層34b之接合範圍J所圍繞地加以配置。因此，加以抑制經由從半導體裝置30之外部侵入有藥液之時，而對於第1貫穿孔導電體16a及第2貫穿孔導電體16b產生有不良之情況同時，亦加以抑制在切割工程中，第1絕緣層34a或第2絕緣層34b產 生破損(晶片刮傷)。因此，與經由有關上述比較例之半導體裝置之製造方法而製造之半導體裝置100做比較，可產率佳地製造對於信賴性更優越之半導體裝置30者。
然而，在有關第2實施例之半導體裝置30之製造方法及半導體裝置30中，僅對於第1部分之下層部31a之第1絕緣層34a的一部分範圍而言，選擇性地進行蝕刻，使第1貫穿孔導電體16a突出，而對於第2部分之上層部31b之第2絕緣層34b而言係未進行選擇性的蝕刻，而未使第2貫穿孔導電體16b突出，但將第1部分作為上層部31b，而將第2部分作為下層部31a亦可。即，僅對於上層部31b之第2絕緣膜34b的一部分範圍而言，選擇性地進行蝕刻，使第2貫穿孔導電體16b突出，而對於下層部31a之第1絕緣膜34a而言係未進行選擇性的蝕刻，而未使第1貫穿孔導電體16a突出亦可。在如此之製造方法，亦可得到與有關本實施例之半導體裝置30之製造方法及半導體裝置30同樣之效果。
雖已說明過本發明之幾個實施形態，但此等實施形態係作為例而提示之構成，未特意限定發明之範圍者。此等新穎之實施形態係可由其他種種形態而加以實施，在不脫離發明的內容範圍，可進行種種省略，置換，變更者。此等實施形態或其變形係與包含於發明範圍或內容之同時，包含於記載於申請專利申請範圍之發明與其均等的範圍。
例如，在上述各實施例中，在蝕刻第1絕緣 層或第2絕緣層之工程中，作為光罩所使用之光阻層27a係如圖7所示，沿著切割線D而加以形成為格子狀。但光阻層係未必加以形成為如此亦可。於以下，對於光阻層之變形例加以說明。
圖21係從上側而視加以形成有有關變形例之光阻層47之第1半導體晶圓21a的平面圖，圖22係模式性地顯示在形成有關變形例之光阻層47之後的工程中，在固態接合下層部與上層部時之第1絕緣層與第2絕緣層之接合範圍J及非接合範圍NJ的平面圖。
如圖21所示，光阻層47係於第1絕緣層14a(34a)之表面上，沿著切割線D而加以設置為格子狀之其他，又第1絕緣層14a(34a)之表面上之中，沿著第1半導體晶圓21a的周圍加以設置亦可。然而，對於將光阻層47，適用於有關第1實施例之半導體裝置之製造方法之情況，將光阻層47，於第2絕緣層14b之表面上，沿著切割線D而加以設置為格子狀之其他，又第2絕緣層14b之表面上之中，沿著第2半導體晶圓21b的周圍加以設置。如此形成光阻層47之情況，如圖22所示，第1絕緣層14a(34a)與第2絕緣層14b(34b)之接合範圍J係沿著切割線D而加以設置為格子狀之其他，又沿著第1，第2半導體晶圓21a，21b之周圍加以設置，第1絕緣層14a(34a)與第2絕緣層14b(34b)之非接合範圍NJ係經由接合範圍J所圍住。
在歷經形成有關以上所說明之變形例的光阻 層47之工程而製造之半導體裝置之製造方法及半導體裝置中，亦可得到與有關上述之各實施例之半導體裝置10，30之製造方法及半導體裝置10，30同樣之效果。
以上所說明之光阻層的變形例之其他，例如，經由蝕刻第1，第2絕緣層14a(34a)，14b(34b)而從此絕緣層14a(34a)，14b(34b)的表面突出之導電層(構成第1，第2接合面之導電範圍)係亦可為貫穿孔導電體16a、16b以外的導電體，例如配線。
16a‧‧‧第1貫穿孔導電體
26a‧‧‧碟狀部
27a‧‧‧光阻層
Sa‧‧‧第1接合面
14a‧‧‧第1絕緣層

Claims (20)

  1. 一種半導體裝置之製造方法，其特徵為具有第1導電層及第1絕緣層，將前述第1導電層及前述第1絕緣層則從表面露出之第1配線層，形成於第1基板上，具有第2導電層及第2絕緣層，將前述第2導電層及前述第2絕緣層則從表面露出之第2配線層，形成於第2基板上，經由將前述第1絕緣層表面之中，包含前述第1導電層周圍之一部分範圍，作為較前述第1導電層表面為低之時，於前述第1絕緣層表面，形成第1非接合面，電性連接前述第1導電層表面與前述第2導電層表面之同時，接合除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面者。
  2. 如申請專利範圍第1項記載之半導體裝置之製造方法，其中，呈於前述第1非接合面與前述第2絕緣層之間，加以形成有空間地，接合除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面。
  3. 如申請專利範圍第2項記載之半導體裝置之製造方法，其中，將前述空間，使前述第1非接合面，從前述第2絕緣層隔開，且經由接合除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面之時而形成。
  4. 如申請專利範圍第3項記載之半導體裝置之製造方法，其中，將經由前述第1導電層表面與前述第2導電層表面接合之時而加以形成之導電體的一部分，配置於前 述空間內。
  5. 如申請專利範圍第1項記載之半導體裝置之製造方法，其中，於從前述第1配線層表面露出之前述第1絕緣層表面上的特定範圍，形成第1光阻層，經由蝕刻從此第1光阻層露出之前述第1絕緣層，將包含前述第1導電層周圍之一部分範圍，作為較前述第1導電層表面為低之時，形成前述第1非接合面。
  6. 如申請專利範圍第5項記載之半導體裝置之製造方法，其中，前述第1基板係為第1晶圓之同時，前述第2基板係為第2晶圓，將前述第1光阻層，在前述第1絕緣層表面上，形成於切割線上。
  7. 如申請專利範圍第5項記載之半導體裝置之製造方法，其中，前述第1基板係為第1晶圓之同時，前述第2基板係為第2晶圓，將前述第1光阻層，在前述第1絕緣層表面上，形成於前述切割線上之同時，沿著前述第1晶圓周邊而形成。
  8. 如申請專利範圍第1項記載之半導體裝置之製造方法，其中，經由將前述第2絕緣層表面之中，包含前述第2導電層周圍之一部分範圍，作為較前述第2導電層表面為低之時，於前述第2絕緣層表面，形成第2非接合面，電性連接前述第1導電層表面與前述第2導電層表面之同時，接合除了前述第1非接合面之前述第1絕緣層表 面與除了前述第2非接合面之前述第2絕緣層表面者。
  9. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，呈於前述第1非接合面與前述第2非接合面之間，加以形成有空間地，接合除了前述第1非接合面之前述第1絕緣層表面與除了前述第2非接合面之前述第2絕緣層表面。
  10. 如申請專利範圍第9項記載之半導體裝置之製造方法，其中，將前述空間，經由使前述第1非接合面與前述第2非接合面隔離，且接合除了前述第1非接合面之前述第1絕緣層表面與除了前述第2非接合面之前述第2絕緣層表面之時而形成。
  11. 如申請專利範圍第10項記載之半導體裝置之製造方法，其中，將經由前述第1導電層表面與前述第2導電層表面接合之時而加以形成之導電體的一部分，配置於前述空間內。
  12. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，在前述第1非接合面，於從前述第1配線層表面露出之前述第1絕緣層表面上的特定範圍，形成第1光阻層，經由蝕刻從此第1光阻層露出之前述第1絕緣層，將包含前述第1導電層周圍的一部分範圍，作為較前述第1導電層表面為低之時而形成，在前述第2非接合面，於從前述第2配線層表面露出之前述第2絕緣層表面上的特定範圍，形成第2光阻層， 經由蝕刻從此第2光阻層露出之前述第2絕緣層，將包含前述第2導電層周圍之一部分範圍，作為較前述第2導電層表面為低之時而形成。
  13. 如申請專利範圍第12項記載之半導體裝置之製造方法，其中，前述第1基板係為第1晶圓之同時，前述第2基板係為第2晶圓，將前述第1光阻層，在前述第1絕緣層表面上，形成於切割線上，將前述第2光阻層，在前述第2絕緣層表面上，形成於切割線上。
  14. 如申請專利範圍第12項記載之半導體裝置之製造方法，其中，前述第1基板係為第1晶圓之同時，前述第2基板係為第2晶圓，將前述第1光阻層，在前述第1絕緣層表面上，形成於前述切割線上之同時，沿著前述第1晶圓周邊而形成，將前述第2光阻層，在前述第2絕緣層表面上，形成於前述切割線上之同時，沿著前述第2晶圓周邊而形成。
  15. 一種半導體裝置，具備：具有第1導電層及第1絕緣層，於前述第1絕緣層表面之中，包含前述第1導電層周圍之一部分範圍，具有使前述第1導電層突出為凸狀之第1非接合面的第1配線層，和具有加以接合於前述第1導電層表面之第2導電層及加以接合於除了前述第1非接合面之前述第1絕緣層表面的第2絕緣層之第2配線層者。
  16. 如申請專利範圍第15項記載之半導體裝置，其中，前述第2配線層係於前述第2絕緣層表面之中，包含前述第2導電層周圍之一部分範圍，具有使前述第2導電層突出為凸狀之第2非接合面。
  17. 如申請專利範圍第15項記載之半導體裝置，其中，對於前述第1配線層之前述第1非接合面，和前述第2配線層之前述第2絕緣層表面之間，係加以形成有空間。
  18. 如申請專利範圍第17項記載之半導體裝置，其中，前述空間係呈由除了前述第1非接合面之前述第1絕緣層表面與前述第2絕緣層表面的接合部分所圍繞地，加以形成。
  19. 如申請專利範圍第17項記載之半導體裝置，其中，將經由前述第1導電層表面與前述第2導電層表面接合之時而加以形成之導電體的一部分，係配置於前述空間內。
  20. 如申請專利範圍第15項記載之半導體裝置，其中，前述第1導電層與前述第2導電層係加以金屬結合之同時，前述第1絕緣層與前述第2絕緣層係共有結合。
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