TW201532229A - 具有缺陷排除之整合式銲線接合器與三維測量系統 - Google Patents

具有缺陷排除之整合式銲線接合器與三維測量系統 Download PDF

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Publication number
TW201532229A
TW201532229A TW103138823A TW103138823A TW201532229A TW 201532229 A TW201532229 A TW 201532229A TW 103138823 A TW103138823 A TW 103138823A TW 103138823 A TW103138823 A TW 103138823A TW 201532229 A TW201532229 A TW 201532229A
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Taiwan
Prior art keywords
wire
wire bonding
dimensional
bonding system
electronic assembly
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TW103138823A
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English (en)
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Daren W Keller
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Fairchild Semiconductor
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Publication of TW201532229A publication Critical patent/TW201532229A/zh

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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1432Central processing unit [CPU]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]

Abstract

本發明揭示一種設備,其包含銲線接合系統,該銲線接合系統包括銲線接合裝置、測量裝置、及排除裝置。該銲線接合裝置經組態以附接銲線型電互連至電子總成。銲線係形成於第一半導體裝置與第二電子裝置之間而形成該電子總成之至少一部分。該測量裝置經組態以執行與銲線相關聯之三維測量,且該排除裝置經組態以根據該三維銲線測量值來辨識電子總成以供排除。

Description

具有缺陷排除之整合式銲線接合器與三維測量系統 【相關申請案之交互參照】
本專利申請案主張美國專利臨時申請案第61/914,573號(申請日為2013年12月11日)的優先權。
本文件是關於電子裝置,且更具體而言是關於半導體裝置的自動化銲線接合。
銲線接合(Wire bonding)係指在半導體裝置(例如積體電路或IC)與其封裝之間加入電互連(electrical interconnection)、或加入對另一電子裝置(例如用於半導體裝置或印刷電路板之導線架)之電互連的程序。一旦完成銲線接合程序,會例如由作業員使用顯微鏡對該些銲線進行人工檢驗以辨識出缺陷。本發明人已體認出需要對銲線接合程序有所改進。
本文件大致上是關於用於組裝電子裝置與系統之系統、裝置、以及方法,且具體而言是關於半導體裝置的銲線接合。如之前 所解釋,銲線接合程序完成後,該些銲線即會經過人工檢驗以辨識出缺陷。因為接合程序與其檢驗是分開的,因此在經由人工檢驗發現出問題前,可能已有一或多個批量被完成。這可能會導致大量的缺陷產品。除此以外,人工檢驗也會增加製造程序中的成本與時間。本發明之標的可藉由即時整合檢驗與銲線接合程序來改進製造程序,以取代執行離線階段進行的檢驗。
本發明標的之設備實例包括銲線接合系統,其具有銲線接合裝置、測量裝置、及排除裝置。該銲線接合裝置經組態以將銲線型電互連附接至電子總成。銲線係形成於第一半導體裝置與第二電子裝置之間,而形成該電子總成的至少一部分。該測量裝置經組態以執行與銲線相關之三維測量,且該排除裝置經組態以根據該三維銲線測量,辨識出電子組件以供排除。
本段落之目的在於提供本專利申請案標的之概要。其目的非在於提供本發明之排他性解釋或詳盡之解釋。實施方式係被包括以提供本專利申請案之更進一步的資訊。
105‧‧‧方塊
110‧‧‧方塊
115‧‧‧方塊
205‧‧‧輸入處理器
210‧‧‧銲線接合裝置
215‧‧‧測量裝置
220‧‧‧排除裝置
225‧‧‧輸出處理器
230‧‧‧晶粒附接裝置
235‧‧‧控制器
310‧‧‧銲線接合/檢驗模組
320‧‧‧排除裝置
405‧‧‧方塊
410‧‧‧方塊
415‧‧‧方塊
420‧‧‧方塊
425‧‧‧方塊
435‧‧‧方塊
在圖式(其未必按比例繪製)中,相似元件符號可描述不同視角的相似組件。具有不同字母後綴的相似元件符號,可代表相似元件的不同例示。該些圖式大致上係以例示方式(而非以限制方式)圖解說明本文件所討論之各種實施例。
圖1為一種銲線接合電子裝置或電子總成的方法的實例之流程圖。
圖2為銲線接合系統的實例之示圖。
圖3為銲線接合系統之另一實例的示圖。
圖4顯示具有回授控制之銲線接合系統中的製作流程圖。
如本文先前所解釋,若檢驗可與製造產品的過程整合,則銲線接合程序可被改進。於是,檢驗可在組裝進行時即時完成,而非在銲線被完成後才以離線方式進行。
圖1為一種銲線接合電子裝置或電子總成的方法100的實例之流程圖。在方塊105中,使用銲線接合系統將一或多條銲線附接於第一半導體裝置與第二電子裝置之間。一或多條銲線在第一半導體裝置與第二電子裝置之間形成了一或多個電互連。第一半導體裝置、第二電子裝置、及電互連形成了電子總成的至少一部分。第一半導體裝置可包括IC或其他半導體裝置。第二電子裝置可包括用於第一半導體裝置之封裝,例如導線架。第二電子裝置可包括印刷電路板或基板。在某些實例中,第二電子裝置為第二半導體裝置。
在方塊110中,以銲線接合系統之測量裝置執行與一或多條銲線相關聯之一或多個三維測量。與一或多條銲線相關聯之三維測量的一些實例包括(除其他種種測量外)一或多條銲線的拉弧高度(loop height)以及一或多條銲線之位置。測量係由測量裝置自動執行,且不需由作業員進行測量。測量裝置可自銲線接合系統之銲線接合站接收電子總成。銲線接合站可在對該總成完成銲線接合時,將電子總成傳遞至測量裝置。可在銲線接合系統在線上且在執行銲線接合時即 時完成測量。三維測量可用來偵測總成之銲線中的缺陷,例如(除其他種種缺陷外),銲線分離(lifted wire bond)、銲線短路、以及銲線過長或過高(過量的拉弧高度)。
在方塊115中,根據三維銲線測量而選擇性地辨識出電子總成,以供銲線接合系統之排除裝置排除。當三維測量值不滿足三維測量值之特定範圍時,排除裝置可辨識出電子總成以供排除。舉例來說,當銲線拉弧高度之三維測量值高於特定拉弧高度臨界值時,或高於或低於拉弧高度之特定範圍值時,可辨識出電子總成以供排除。
圖2為銲線接合系統之實例的示圖。系統包括銲線接合裝置210、測量裝置215、以及排除裝置220。作為製造程序的一部分,可使用輸入處理器(input handler)205或輸入匣處理器(input magazine handler)將所要進行銲線的電子裝置饋入銲線接合裝置210中。銲線接合裝置210將銲線型電互連(例如,具有微米直徑的線(wire)或是帶(ribbon))附接至所接收裝置。銲線係形成於第一半導體裝置與第二電子裝置之間,而形成電子總成的至少一部分。銲線接合裝置210所形成之銲線可包括含有(除其他以外)銅、鋁、或金中之一或多者之線或帶,且銲線可附接至第一半導體裝置之一或多個接觸墊。半導體裝置可包括分立零件(例如二極體或電晶體)或可包括具有許多半導體電路的IC,例如,處理器或特定應用積體電路(ASIC)。第二電子裝置可包括用於半導體裝置之封裝的至少一部分,或可包括附接有第一半導體裝置之PCB或基板。在某些實例中,第二電子裝置可為第二半導體裝置。銲線的末端可使用焊料或環氧樹脂其中之一或 二者來附接或接合至接觸墊。銲線接合裝置可將銲線應用至電子總成中所包括的額外半導體裝置或電子裝置。輸出處理器(output handler)225或輸出匣處理器(output magazine handler)用來收集完成的總成。
測量裝置215可與銲線接合裝置210分離,且可自銲線接合裝置210接收電子總成。圖3為銲線接合系統之另一實例的示圖。在所示實例中,銲線接合裝置與測量裝置被整合為單一銲線接合/檢驗模組310。銲線接合之檢驗可在執行銲線接合時或是完成銲線接合時,但是在電子總成被傳遞至排除裝置320之前進行。
回到圖2,測量裝置215執行與銲線相關之三維測量。與一或多條銲線相關之三維測量的一些實例包括(除其他種種測量以外)一或多條銲線的拉弧高度、一或多條銲線的長度、一或多條銲線的位置、以及第一半導體裝置與第二電子裝置其中之一或兩者的旋轉量。
測量裝置215可包括三維成像裝置(例如3D攝影機),其獲取電子總成的影像。該等影像可包括銲線接合裝置210所完成之電子總成的一或多個預定之關注區域。測量裝置215可包括處理器,例如微處理器或數位訊號處理器,以處理三維成像裝置所獲取的影像。可使用圖型識別以辨識與測量銲線。舉例來說,處理器可在使用成像裝置所獲取之影像的畫素上使用邊緣探測演算法,以自影像之背景中辨識出銲線之線或帶。可辨識出銲線之特徵,且可使用測得之銲線的座標來計算參數,例如銲線拉弧高度與位置。可辨識出待接合裝置的特徵,以判定裝置的旋轉與傾斜。一種在電子總成中三維測 量的方法可參看Chung等人於2010年2月8日所申請之巴黎合作條約(PCT)專利公開申請案號WO2010090605,該申請案之全文在此併入以供參照。
在某些實例中,測量裝置215包括紅外線成像裝置,以獲取電子總成之熱影像。測量裝置215可包括處理器,以處理熱影像來測量銲線的參數。在某些實例中,測量裝置215包括雷射測量或成像裝置。測量裝置215可使用干涉測量法來判定銲線的特徵。
三維測量可在銲線接合裝置完成總成的接合且該等總成移動至測量裝置時即時地完成,或是若兩個裝置經整合則在執行接合之時完成。三維測量可提供比二維測量更多的細節與更佳的準確度。然而,處理三維影像以特徵化銲線會比二維測量需要更長的時間。在某些實例中,若需要較快的處理,可切換測量裝置215以實施二維分析。舉例來說,成像裝置可包括立體相機,以產生三維影像。可切換測量裝置215以僅使用相機來產生二維影像以供處理。另一種加速處理的方法是抽樣測量該些總成。測量裝置可對少於銲線接合裝置所形成之所有複數個電子總成(例如五個中的一個或是十個中的一個)執行三維測量。
在某些實例中,銲線接合系統包括晶粒附接裝置230。晶粒附接裝置230可被整合至銲線接合裝置210中。作為組裝程序的一部分,晶粒附接裝置230可將半導體裝置或其他電子裝置安裝於基板或PCB上。在某些實例中,晶粒附接裝置230將第一半導體裝置安裝於鄰接一或多個其他電子裝置之處。在某些實例中,晶粒附接裝置 230堆疊第一半導體裝置與至少一第二半導體裝置以作為電子總成的一部分。測量裝置215可產生第一半導體裝置與第二半導體裝置之堆疊高度的三維測量。
排除裝置220根據三維銲線測量值,辨識出電子總成以供排除。在某些實例中,當與銲線相關之三維測量值並不滿足三維測量值之特定範圍時,排除裝置220辨識出電子總成以供排除。舉例來說,測量值可高於或低於可接受值之範圍,或可高於或低於測量值之特定臨界值。
根據某些實例,排除裝置220根據三維銲線測量值來選擇性地修改(alter)電子總成。修改可為機械性修改,其使得能在製造程序下游容易辨識出具缺陷之零件。在某些實例中,當與銲線相關之三維測量值並未滿足三維測量值之特定範圍時,排除裝置220於銲線中形成電性不連續。如此一來,具缺陷的零件可在稍後的製造程序中使用電性測試(例如一種用來評估功能性與電性連續性其中之一或兩者的電性測試)而被辨識出來。
在一些變化例中,排除裝置220包括銲線切割機制,以在辨識出缺陷時切割銲線。銲線可藉由使用刀片或雷射透過加熱或切片來加以切割。在某些變化例中,排除裝置220包括抬升機制,以在辨識出缺陷時將銲線中的一條線抬升離開銲墊。在某些變化例中,排除裝置220包括鑽穿機制,以在辨識出缺陷時鑽磨掉導線架的至少一部分。在某些變化例中,排除裝置220包括晶粒衝壓機制,以在辨識出缺陷時衝壓掉銲線的至少一部分。若錯誤是在晶粒附接參數中且測 量並非與銲線相關時,這可為實用的。經修改之銲線可為具有缺陷的銲線或是可為任何便於切割、抬升、鑽孔、或衝壓以使得該總成無法通過電性連續性測試的銲線。具缺陷裝置可被排除裝置所剔除或是被組裝程序下游之裝置之處理所剔除。
在一些實例中,排除裝置220標記出具缺陷的電子總成。在變化例中,排除裝置220以顏色或劃線(scribe)標記具缺陷的電子總成。在某些變化例中,標記是機械可辨識的,且銲線接合系統下游之裝置將具缺陷的零件從製造程序中剔除。在某些變化例中,標記是大到足以被作業員所辨識出來而不需要如顯微鏡之類的視覺輔助裝置,並由作業員剔除該些零件。
在某些實例中,銲線接合系統包括控制器235。控制器235可使用硬體電路、韌體、軟體、或任何硬體、韌體、及軟體的組合來實施。實例包括處理器,例如微處理器、特定應用積體電路(ASIC)、或其他類型的處理器。控制器235經(硬體、韌體、或軟體)組態以執行所述功能。該些功能對應於模組,其等為軟體、硬體、韌體、或其任何組合。可於一或多個模組中執行多種功能。
銲線接合系統可包括整合至控制器或電耦接至控制器235之記憶體電路。排除裝置220可儲存識別符於記憶體電路中,以辨識具缺陷電子總成,該具缺陷電子總成係使用一或多個三維測量值所判定。接著可電子追蹤或映射具缺陷總成。電子映射可使下游裝置能夠使用識別符來將具缺陷零件從程序中剃除。在一些實例中,當與 銲線相關之三維測量值並未滿足三維測量值之特定範圍時,銲線接合系統可產生錯誤訊息。接著,作業員可採取必要措施來修正該錯誤。
將檢驗與銲線接合加以整合,可提供銲線接合程序的即時回授控制。測量裝置215可在銲線接合系統的測量裝置與銲線接合裝置之間傳達至少一個三維測量值。在一些實例中,三維測量值是由控制器235所接收。控制器235回應於所傳達之測量值,調整銲線接合裝置之至少一個銲線接合參數。在一些實例中,當與銲線相關之三維測量值並未滿足三維測量值之特定範圍時,控制器235調整銲線接合參數。舉例來說,若測量值指出銲線位置落於特定範圍之外時,控制器235可調整位置以使測量值回到範圍內。在一些實例中,控制器235針對該位置計算測量值與特定值之間之錯誤,並調整銲線位置以極小化該錯誤。同樣地,控制器235可提供其他銲線測量值的回授調整,例如,銲線拉弧高度與銲線長度。
在一些實例中,控制器235接收裝置之旋轉的三維測量值,該裝置例如製造程序中的晶粒附接步驟期間置放於基板上的一或多個裝置。若三維測量值指出銲線位置落於特定範圍之外,控制器235可調整該旋轉,以使測量值回到範圍之內。這可有助於銲線接合系統的初始設定。作業員可實際上設定初始銲線位置。此初始位置可能是不正確的,且可以是故意不正確的。銲線接合系統可藉由極小化正確位置之已程式化錯誤,而使用回授控制來集中在正確設定上。
控制器可基於三維測量值來採取不同的行動。所採取行動可取決於故障類型、故障次數、以及故障的嚴重程度其中一或多 者。在某些實例中,行動係基於統計製程控制(SPC)分析。舉例來說,控制器235可試著不去調整銲線接合器或晶粒附接參數,直到測量值中的錯誤超過臨界值或落於特定範圍之外為止。控制器235可僅記錄該些測量值、或指出測量值中的偏移,直到錯誤到達預定嚴重程度為止。
在某些實例中,銲線接合系統包括使用者介面,其與控制器235電連通。使用者介面可包括小鍵盤(keypad)、鍵盤、電腦滑鼠、以及顯示器其中一或多者。控制器可被程式化以顯示一或多個三維測量值。在某些變化例中,當三維測量值落於特定範圍之外時,或當測量值以其他方式指出銲線接合程序處於錯誤狀態時,控制器235產生警示。警示可使用使用者介面來顯示。在某些變化例中,將警示傳達(例如使用有線或無線通訊方式傳達的訊號)至分離的裝置或系統,以顯示給使用者。在某些變化例中,一或多個三維測量值被傳達並儲存至資料庫(例如,儲存於伺服器上的資料庫),以作為未來SPC資料分析或即時資料分析之用。若SPC分析偵測到異常狀況或規格外的狀況時,可(例如,由控制器、分離裝置、或使用者)使用警示以停止銲線接合及/或晶粒附接程序,或在現行批次之總成結束時停止程序。
圖4顯示具有回授控制之銲線接合系統中的製作流程圖。在方塊405中,例如半導體裝置的電子裝置被輸入至銲線接合系統。在方塊410中,該等裝置經過晶粒附接或銲線接合而形成電子總成或次總成。在方塊415中,判定一或多個測量值(例如三維測量值 或二維測量值)。該等測量係與銲線接合與晶粒附接其中之一或兩者相關聯。在方塊435中,回饋一或多個測量值以將程序參數維持在特定範圍內。若測量值指出錯誤時,可調整晶圓附接程序與銲線接合程序其中之一或兩者。
在方塊420中,例如藉由本文上述任何方法,辨識出具缺陷之裝置。在方塊425中,將不具缺陷的裝置傳遞至銲線接合站的輸出端。具有缺陷的裝置可被收集於排除站、或可被傳遞至輸出端以在稍後由另一裝置進行剔除。
本文所述之系統、裝置、與方法相較於離線完成且與組裝程序分離的檢驗(人工或自動的),提供了多種優點。對於銲線接合與晶粒附接其中之一或兩者的檢驗與監控係在執行銲線接合與晶粒附接時即時完成。這減少了在製程離線後進行獨立檢驗所需的時間與佔地面積。其亦可排除需由作業員進行檢驗的需求,而減少了時間與成本。與銲線接合及晶粒附接即時進行的檢驗與監控,使得系統可進行製程特徵化與SPC。其亦使得能夠進行立即機器式互動,以解決所偵測到的錯誤。其使得具缺陷裝置得以迅速自組裝程序移除,以減少因使用具缺陷零件而導致的下游組裝成本。
額外的註記與實例
實例1可包括標的(例如設備),其包含銲線接合系統,該銲線接合系統包括銲線接合裝置,該銲線接合裝置經組態以將銲線型電互連附接至電子總成。銲線係形成於第一半導體裝置與第二電子裝置之間,而形成該電子總成的至少一部分。該標的亦可包括測 量裝置及排除裝置,該測量裝置經組態以執行與銲線相關之三維測量,該排除裝置經組態以根據該三維銲線測量值辨識出電子總成以供排除。
在實例2中,實例1之該標的可視需要包括控制器,該控制器經組態以自該測量裝置接收至少一個三維測量值,並回應於該等經傳達之測量值來調整該銲線接合裝置之至少一銲線接合參數。
在實例3中,實例2之該標的可視需要包括測量裝置,該測量裝置經組態以產生該半導體裝置之旋轉的量度,其中該控制器係視需要經組態以回應於該等所產生的旋轉量度來調整至少一銲線接合參數。
在實例4中,實例1至3中之一者或任一組合之該標的可視需要包括排除裝置,該排除裝置經組態以根據該三維銲線測量值來選擇性地修改電子總成。
在實例5中,實例1至4中之一者或任一組合之該標的可視需要包括排除裝置,該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,在該銲線中形成電性不連續。
在實例6中,實例1至5中之一者或任一組合之該標的可視需要包括排除裝置,該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,標記電子總成的該至少一部分。
在實例7中,實例1至6中之一者或任一組合之該標的可視需要包括記憶體電路,該記憶體電路電耦接至或整合至該排除裝置,其中該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,針對電子總成之該至少一部分儲存識別符於該記憶體電路中。
在實例8中,實例1至7中之一者或任一組合之該標的可視需要包括測量裝置,該測量裝置經組態以產生對於銲線之拉弧高度與銲線之位置其中之一或兩者的三維測量值。
在實例9中,實例1至8中之一者或任一組合之該標的可視需要包括晶粒附接裝置,該晶粒附接裝置經組態以堆疊該第一半導體裝置與至少一第二半導體裝置而作為該電子總成的一部分,且其中該測量裝置經組態以產生對於該第一半導體裝置與該至少一第二半導體裝置之堆疊高度的三維測量值。
在實例10中,實例1至9中之一者或任一組合之該標的可視需要包括測量裝置,該測量裝置包括三維成像裝置。
在實例11中,實例1至10中之一者或任一組合之該標的可視需要包括測量裝置,該測量裝置包括雷射或紅外線成像裝置中之至少一者。
在實例12中,實例1至11中之一者或任一組合之該標的可視需要包括銲線接合裝置,該銲線接合裝置經組態以形成複數個電子總成中之電子總成的至少一部分,且其中該測量裝置經組態以對 少於該銲線接合裝置所形成之所有該複數個電子總成執行該三維測量。
在實例13中,實例1至12中之一者或任一組合之該標的可視需要包括銲線接合裝置,該銲線接合裝置經組態以在該第一半導體裝置與用於該第一半導體裝置之導線架或第二半導體裝置之至少一者之間形成銲線。
實例14可包括標的(例如方法、用於執行動作之手段、或包含指令的機器可讀媒體,該等指令由機器執行時致使該機器執行動作),或可視需要與實例1至13中之一者或任一組合之標的結合以包括此標的,該標的包含:藉由銲線接合系統附接一或多條銲線以在第一半導體裝置與第二電子裝置之間形成一或多個電互連而形成第一電子總成的至少一部分;藉由該銲線接合系統之測量裝置執行一或多個與該一或多條銲線相關聯之三維測量;以及藉由該銲線接合系統之排除裝置,根據該三維銲線測量值選擇性地辨識出該第一電子總成以供排除。
在實例15中,實例14之該標的可視需要包括在執行該一或多個與該第一電子總成之該一或多條銲線相關聯之三維測量期間,藉由該銲線接合系統形成第二電子總成的至少一部分。
在實例16中,實例14與15中之一者或兩者之該標的可視需要包括在修改該第一電子總成期間,起始與第二電子總成之一或多條銲線相關聯之一或多個三維測量。
在實例17中,實例14至16中之一者或任一組合之該標的可視需要包括:在該測量裝置與該銲線接合系統之銲線接合裝置之間傳達至少一個三維測量值;以及藉由該銲線接合系統回應於該等經傳達之測量值來調整至少一個銲線接合參數。
在實例18中,實例14至17中之或任一組合之該標的可視需要包括產生銲線之一或多個拉弧高度與銲線之位置的三維測量值。
在實例19中,實例14至18中之一者或任一組合之該標的可視需要包括堆疊該第一半導體裝置與至少一個第二半導體裝置而形成該第一電子總成的至少一部分,其中執行一或多個三維測量包括產生該第一半導體裝置與該至少一第二半導體裝置之IC堆疊高度之三維測量值。
在實例20中,實例14至19中之一者或任一組合之該標的可視需要包括使用三維成像裝置執行一或多個三維測量。
在實例21中,實例14至20中之一者或任一組合之該標的可視需要包括當與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,移除該銲線之電性連續性。
在實例22中,實例14至21中之一者或任一組合之該標的可視需要包括當與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,選擇性地標記該IC晶粒或該第一電子總成之該電子裝置其中至少一者。
實例23可包括標的,或可視需要與實例1至22中任一或多者之任何部分或任何部分之組合相結合以包括標的,該標的可包括用以執行實例1至22中之功能中任一或多者的手段,或包括指令之機器可讀媒體,該等指令當由機器執行時致使該機器執行實例1至22中之功能中任一或多者。
這些非限制性實例可以任何排列或組合來相結合。
以上實施方式包括對隨附圖式之參照,該等圖式形成實施方式之一部分。該等圖式藉由圖解說明的方式,顯示出可實行本發明的具體實施例。此等實施例在本文中亦可稱為「實例」。本文件中所參照的所有出版文件、專利、與專利文件之全文皆併入本文以供參照,如同個別併入以供參照之方式。在本文件與其他如此併入參照的文件之間發生不一致使用時,所併入參照文件的使用應被視為補充本文件之使用。對於無法調和的不一致,則依本文件之使用為準。
在本文件中,在專利文件中常見的「一」之用語是用以包括一個或多於一個的情況,並獨立於「至少一個」或「一或多個」的任何其他例子或使用。在本文件中,除非另有相反指示,否則「或」之用語係用來指非排他性的或,例如「A或B」包括「A但非B」、「B但非A」、以及「A以及B」。在後附的申請專利範圍中,「包括(including)」與「其中(in which)」之用語之用法各別為一般英語中「包含(comprising)」與「其中(wherein)」之用語的等效詞。另外,在以下申請專利範圍中,「包括」與「包含」之用語係為開放性用語,意即,一包括有請求項中用語所列以外之元件的系統、裝置、 物品、或程序,仍應視為落入該請求項的範圍內。再者,在以下申請專利範圍中,「第一」、「第二」、「第三」等用語僅為標示之用,而非意欲對其對象加諸數字上之要求。
本文所述之方法實例可至少部分為機器或電腦可實施的。一些實例可包括經編碼有指令之電腦可讀媒體或機器可讀媒體,該等指令可操作用以組態電子裝置以執行以上實例中所述的方法。此等方法的具體實施可包括程式碼,例如微程式碼、組合語言程式碼、較高階語言程式碼、或類似者。此等程式碼可包括用於執行各種方法之電腦可讀指令。程式碼可形成電腦程式產品的部分。此外,程式碼可在執行期間或其他時間期間具體地儲存於一或多個揮發性或非揮發性電腦可讀媒體上。此等電腦可讀媒體可包括(但不限於)硬碟、可移除式磁碟、可移除式光碟(例如光碟與數位影音光碟)、磁式卡匣、記憶卡或記憶條、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、與類似物。
上列敘述係意欲為說明性而非限制性。舉例來說,上述實例(或其一或多個態樣)可彼此組合而使用。其他實施例可例如由所屬技術中具有通常知識者檢閱上列敘述而使用。摘要之提供係為符合37 C.F.R.§1.72(b)之規定,以使讀者可快速的確認本技術揭露的性質。須被理解的是,本文件並不用於闡釋或限定申請專利範圍的範疇或意義。再者,在上述實施方式中,可能群組化各種特徵以簡化本揭露。這不應被闡釋為意欲使未主張之揭露特徵對任何請求項來說是必要的。應該說,發明標的可少於所揭露之一具體實施例中的所有特徵 而存在。因此,下列申請專利範圍在此併入於實施方式中,且每一請求項之本身皆為一分別的實施例。本發明之範疇應參照所附申請專利範圍以及符合申請專利範圍之均等項之完整範圍來判定。
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Claims (15)

  1. 一種銲線接合系統,其包括:銲線接合裝置,其經組態以將銲線型電互連附接於電子總成,其中銲線係形成於第一半導體裝置與第二電子裝置之間而形成該電子總成之至少一部分;測量裝置,其經組態以執行與銲線相關聯之三維測量;以及排除裝置,其經組態以根據該三維銲線測量值,辨識出電子總成以供排除。
  2. 如請求項1之銲線接合系統,其包含控制器,其中該控制器經組態以自該測量裝置接收至少一個三維測量值,並回應於所傳達之該測量值來調整該銲線接合裝置之至少一銲線接合參數。
  3. 如請求項2之銲線接合系統,其中該測量裝置經組態以產生該半導體裝置之旋轉的量度,其中該控制器經組態以回應於所產生之該旋轉量度來調整至少一銲線接合參數。
  4. 如請求項1之銲線接合系統,其中該排除裝置經組態以根據該三維銲線測量值,選擇性地修改電子總成。
  5. 如請求項1之銲線接合系統,其中該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,於該銲線中形成電性不連續性。
  6. 如請求項1之銲線接合系統,其中該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,標記電子總成的該至少一部分。
  7. 如請求項1之銲線接合系統,其中銲線接合系統包括記憶體電路,該記憶體電路電耦接至或整合至該排除裝置,其中該排除裝置經組態以在與銲線相關聯之三維測量值未滿足該三維測量值之特定範圍時,針對電子總成之該至少一部分儲存識別符於該記憶體電路中。
  8. 如請求項1之銲線接合系統,其中該測量裝置經組態以產生銲線之拉弧高度與銲線之位置其中之一或兩者的三維測量值。
  9. 如請求項1之銲線接合系統,其包括晶粒附接裝置,該晶粒附接裝置經組態以堆疊該第一半導體裝置與至少一第二半導體裝置作為該電子總成的一部分,且其中該測量裝置經組態以產生該第一半導體裝置與該至少一第二半導體裝置的堆疊高度之三維測量值。
  10. 如請求項1之銲線接合系統,其中該測量裝置包括三維成像裝置。
  11. 如請求項1之銲線接合系統,其中該測量裝置包括雷射或紅外線成像裝置中之至少一者。
  12. 如請求項1至11中任一項之銲線接合系統,其中該銲線接合裝置經組態以在該第一半導體裝置與用於該第一半導體裝置之導線架或第二半導體裝置之至少一者之間形成銲線。
  13. 一種操作銲線接合系統的方法,該方法包含:藉由該銲線接合系統,附加一或多條銲線以在第一半導體裝置與第二電子裝置之間形成一或多個電互連,而形成第一電子總成的至少一部分;藉由該銲線接合系統之測量裝置,執行與該一或多條銲線相關聯之一或多個三維測量;以及 藉由該銲線接合系統之排除裝置,根據該三維銲線測量值,選擇性地辨識出該第一電子總成以供排除。
  14. 如請求項13之方法,其包括藉由該銲線接合系統,在執行與該第一電子總成之該一或多條銲線相關聯之該一或多個三維測量期間,形成第二電子總成的至少一部分。
  15. 如請求項13或14之方法,其包括在修改該第一電子總成期間,起始與第二電子總成之一或多條銲線相關聯之一或多個三維測量。
TW103138823A 2013-12-11 2014-11-07 具有缺陷排除之整合式銲線接合器與三維測量系統 TW201532229A (zh)

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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
JP5426000B2 (ja) * 2012-11-16 2014-02-26 株式会社新川 ワイヤボンディング装置及びワイヤボンディング方法
US11923208B2 (en) * 2017-05-19 2024-03-05 Illinois Tool Works Inc. Methods and apparatuses for chemical delivery for brush conditioning
US10658328B2 (en) * 2017-11-09 2020-05-19 Asm Technology Singapore Pte Ltd Detection of foreign particles during wire bonding
CN111054638A (zh) * 2019-11-27 2020-04-24 奥特斯科技(重庆)有限公司 制造部件承载件的方法及在制造期间操控面板的设备
CN111079564B (zh) * 2019-11-27 2021-06-01 奥特斯科技(重庆)有限公司 处理部件承载件的方法及光学检查设备和计算机可读介质
US20220230314A1 (en) * 2021-01-15 2022-07-21 Kulicke And Soffa Industries, Inc. Intelligent pattern recognition systems for wire bonding and other electronic component packaging equipment, and related methods
CN112992692B (zh) * 2021-05-19 2021-07-20 佛山市联动科技股份有限公司 一种全自动切割引线的方法及系统

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080763A (zh) * 1973-11-14 1975-07-01
JPS59150433A (ja) * 1983-02-05 1984-08-28 Fujitsu Ltd ワイヤ検査装置
JPS60187033A (ja) * 1984-03-07 1985-09-24 Toshiba Corp 半導体装置の自動ワイヤボンデイング方法
US4872052A (en) * 1986-12-03 1989-10-03 View Engineering, Inc. Semiconductor device inspection system
US5030008A (en) * 1988-10-11 1991-07-09 Kla Instruments, Corporation Method and apparatus for the automated analysis of three-dimensional objects
EP0634791B1 (en) * 1993-07-16 2004-01-28 Kaijo Corporation Wire bonder and wire bonding method
US5581632A (en) * 1994-05-02 1996-12-03 Cognex Corporation Method and apparatus for ball bond inspection system
JP2973989B2 (ja) * 1997-11-19 1999-11-08 日本電気株式会社 外観検査機能付きワイヤボンディング装置
US6289492B1 (en) * 1998-12-18 2001-09-11 Cognex Corporation Methods and apparatuses for defining a region on an elongated object
JP2001060605A (ja) * 1999-08-24 2001-03-06 Murata Mfg Co Ltd 実装基板上での電子部品の接合部の検査方法および装置
US6503776B2 (en) * 2001-01-05 2003-01-07 Advanced Semiconductor Engineering, Inc. Method for fabricating stacked chip package
US20050275089A1 (en) * 2004-06-09 2005-12-15 Joshi Rajeev D Package and method for packaging an integrated circuit die
MY169616A (en) 2009-02-06 2019-04-23 Agency Science Tech & Res Methods for examining a bonding structure of a substrate and bonding structure inspection devices
JP4991893B2 (ja) * 2010-03-16 2012-08-01 常陽機械株式会社 微小径ワイヤボンディングの良否判定方法及び判定装置

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