CN105849881A - 集成的引线接合器和具有缺陷剔除的三维测量系统 - Google Patents

集成的引线接合器和具有缺陷剔除的三维测量系统 Download PDF

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Publication number
CN105849881A
CN105849881A CN201480070290.5A CN201480070290A CN105849881A CN 105849881 A CN105849881 A CN 105849881A CN 201480070290 A CN201480070290 A CN 201480070290A CN 105849881 A CN105849881 A CN 105849881A
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wire
lead
measurement
dimensional
electronic building
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达伦·W·凯勒
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

本发明公开了一种装置,所述装置包括具有引线接合装置(210)、测量装置(215)和剔除装置(220)的引线接合器系统。所述引线接合装置(210)被构造为将引线接合型电互连件附接到电子组件。引线接合在第一半导体装置和第二电子装置之间形成,以形成电子组件的至少一部分。所述测量装置(215)被构造为进行与引线接合相关联的三维测量,并且所述剔除装置(220)被构造为根据所述三维引线接合测量识别应予剔除的电子组件。

Description

集成的引线接合器和具有缺陷剔除的三维测量系统
要求优先权
本申请要求于2013年12月11日提交的美国临时专利申请序列号61/914.573的权益。
技术领域
本文件涉及电子装置,并且更具体地讲涉及半导体装置的自动引线接合。
背景技术
引线接合是指在半导体装置(例如,集成电路或IC)与其包装之间或者向另一个电子装置(诸如,用于例如半导体装置或印刷电路板(PCB)的引线框架)加入电互连的工艺。一旦引线接合工艺完成,手动检查引线接合(诸如由操作者使用显微镜)以识别缺陷。本发明人已认识到需要改善引线接合工艺。
发明内容
本文件整体涉及系统、装置以及用于组装电子装置和系统的方法,并且具体地讲涉及半导体装置的引线接合。如本文先前所解释的,一旦引线接合工艺完成,便可手动检查引线接合以识别缺陷。因为检查与接合工艺分开,所以在通过手动检查发现问题之前可能已完成一个或多个批次。这可能产生大量的缺陷产品。另外,手动检查增加制造过程的成本和时间。本主题可通过将检查与引线接合工艺实时集成来改善制造过程,而不是将检查作为离线步骤来进行。
本主题的设备例子包括具有引线接合装置、测量装置和剔除装置的引线接合器系统。引线接合装置被构造为将引线接合型电互连件附接到电子组件。引线接合在第一半导体装置和第二电子装置之间形成,以形成电子组件的至少一部分。测量装置被构造为进行与引线接合相关联的三维测量,并且剔除装置被构造为根据三维引线接合测量识别应予剔除的电子组件。
本部分旨在提供对本专利申请主题的概述。并非旨在提供本发明的排他性或穷举性说明。其中包括有详细描述,用以提供关于本专利申请的更多信息。
附图说明
在未必按比例绘制的附图中,类似的数字在不同的视图中可表示类似的部件。具有不同字母后缀的类似数字可以表示类似部件的不同示例。附图通过示例而非限制的方式概括地示出了本申请文件中讨论的各个实施例。
图1为电子装置或电子组件的引线接合方法的例子的流程图。
图2为引线接合器系统的例子的图示。
图3为引线接合器系统的另一个例子的图示。
图4示出具有反馈控制的引线接合系统中的工艺流程的示意图。
具体实施方式
如本文先前所解释的,如果检查与生产产品集成,引线接合工艺便可改善。于是,检查在组装发生时实时进行,而不是在引线接合已完成之后离线进行。
图1为电子装置或电子组件的引线接合方法100的例子的流程图。在框105处,一个或多个引线接合使用引线接合器系统被附接在第一半导体装置和第二电子装置之间。一个或多个引线接合在第一半导体装置和第二电子装置之间形成一个或多个电互连。第一半导体装置、第二电子装置以及电互连形成电子组件的至少一部分。第一半导体装置可包括IC或其他半导体装置。第二电子装置可包括例如第一半导体装置(诸如引线框架)的包装。第二电子装置可包括印刷电路板(PCB)或基板。在某些例子中,第二电子装置为第二半导体装置。
在框110处,由引线接合器系统的测量装置进行与一个或多个引线接合相关联的一个或多个三维测量。除了别的以外,与一个或多个引线接合相关联的三维测量的一些例子包括一个或多个引线接合的环路高度和一个或多个引线接合的位置。测量由测量装置自动进行并且测量不需要操作者参与。测量装置可从引线接合器系统的引线接合站接收电子组件。引线接合站可在对于电子组件的引线接合完成时将该组件传递到测量装置。测量可在引线接合器系统在线并且进行引线接合时实时进行。三维测量可用于检测组件的引线接合中的缺陷,所述缺陷,除了别的以外,诸如提升的引线接合、短路的引线接合,以及太长或太高的引线接合(过高环路高度)。
在框115处,由引线接合器系统的剔除装置根据三维引线接合测量选择性地识别应予剔除的电子组件。当三维测量不满足三维测量的规定范围时,剔除装置可识别应予剔除的电子组件。例如,当引线环路高度的三维量度高于规定的环路高度阈值,或者高于或低于环路高度值的规定范围时,电子组件可被识别以便剔除。
图2为引线接合器系统的例子的图示。该系统包括引线接合装置210、测量装置215和剔除装置220。作为制造过程的一部分,可使用输入处理器205或输入箱处理器将用于引线接合的电子装置送入到引线接合装置210中。引线接合装置210将引线接合型电互连件附接到所接收的装置,诸如具有例如数微米直径的引线或带状物。引线接合在第一半导体装置和第二电子装置之间形成,以形成电子组件的至少一部分。由引线接合装置210形成的引线接合可包括包含,除了别的以外,铜、铝或金中的一种或多种的引线或带状物,并且引线接合可附接到第一半导体装置的一个或多个接触垫。半导体装置可包括离散部件(例如,二极管或晶体管)或者可包括具有许多半导体电路的IC,诸如处理器或专用集成电路(ASIC)。第二电子装置可包括半导体装置的包装的至少一部分,或者可包括第一半导体装置附接在其上的PCB或基板。在某些例子中,第二电子装置可为第二半导体装置。引线接合的末端可使用焊料和环氧树脂中的一者或两者附接或接合到接触垫。引线接合装置可将引线接合施加到电子组件中包括的另外的半导体装置或电子装置。完成的组件由输出处理器225或输出箱处理器收集。
测量装置215可从引线接合装置210分离并且可从引线接合装置210接收电子组件。图3为引线接合器系统的另一个例子的图示。在所示的例子中,引线接合装置和测量装置被集成到单个引线接合/检查模块310中。可在进行引线接合时,或者在引线接合已完成但电子组件被传递到剔除装置320之前检查引线接合。
返回到图2,测量装置215进行与引线接合相关联的三维测量。与一个或多个引线接合相关联的三维测量的一些例子包括,除了别的以外,一个或多个引线接合的环路高度、一个或多个引线接合的长度、一个或多个引线接合的位置,以及第一半导体装置和第二电子装置中的一者或两者的旋转量。
测量装置215可包括获得电子组件的图像的三维成像装置(例如,三维照相机)。图像可包括由引线接合装置210完成的电子组件的一个或多个预定的被关注区域。测量装置215可包括处理器,诸如微处理器或数字信号处理器,以处理由三维成像装置获得的图像。可使用图案识别来识别并测量引线接合。例如,处理器可对使用成像装置获得的图像的像素采用边缘检测算法以从图像的背景识别引线接合的引线或带状物。引线接合的特征可被识别并且所检测的引线接合的坐标可被用于计算诸如引线接合环路高度和位置之类的参数。待接合的装置的特征可被识别以确定装置旋转和倾斜。电子组件中三维测量的方法可见于授予Chung等人的2010年2月8日提交的巴黎合作条约(PCT)专利申请公布No.WO2010090605,该申请以引用方式全文并入本文中。
在一些例子中,测量装置215包括红外成像装置以获得电子组件的热图像。测量装置215可包括处理器以处理热图像,以测量引线接合的参数。在一些例子中,测量装置215包括激光测量或成像装置。测量装置215可使用干涉测量法测定引线接合的特征。
三维测量可在引线接合装置完成组件的接合并且组件移动到测量装置时实时进行,或者如果两个装置集成,则三维测量可在正在接合时进行。三维测量可提供比二维测量更多的细节和准确度。然而,处理三维图像以表征引线接合可比二维测量花费更长时间。在某些例子中,如果需要更快的处理,则测量装置215可被切换到进行二维分析。例如,成像装置可包括立体照相机以创建三维图像。测量装置215可被切换到仅使用一个照相机以创建二维图像以供处理。加速处理的另一种方法是对被测量的组件进行取样。测量装置可在小于由引线接合装置形成的所有多个电子组件(例如,五分之一或十分之一)上进行三维测量。
在一些例子中,引线接合器系统包括晶粒附接装置230。晶粒附接装置230可集成到引线接合装置210中。晶粒附接装置230可将半导体装置或其他电子装置安装到基板或PCB上作为组装过程的一部分。在一些例子中,晶粒附接装置230将第一半导体装置安装在一个或多个其他电子装置附近。在一些例子中,晶粒附接装置230堆叠第一半导体装置和至少一个第二半导体装置作为电子组件的一部分。测量装置215可生成第一半导体装置和第二半导体装置的堆叠高度的三维测量。
剔除装置220根据引线接合三维测量识别应予剔除的电子组件。在某些例子中,当与引线接合相关联的三维测量不满足三维测量的规定范围时,剔除装置220识别应予剔除的电子组件。例如,测量结果可高于或低于可接受值的范围,或者可高于或低于用于测量的指定阈值。
根据一些例子,剔除装置220根据引线接合三维测量选择性地改变电子组件。该改变可为机械改变,所述机械改变使得易于在制造过程的下游识别缺陷部件。在一些例子中,当与引线接合相关联的三维测量不满足三维测量的规定范围时,剔除装置220在引线接合中形成电不连续性。以这种方式,在制造过程中的稍后阶段,可使用电测试(例如,用以评估功能性和电连续性中的一者或两者的电测试)来识别缺陷部件。
在一些变型中,剔除装置220包括引线切割机构以在缺陷被识别时切割引线接合。引线可通过加热或使用刀片或激光切断来切割。在某些变型中,剔除装置220包括提升机构以在缺陷被识别时将引线接合中的引线提升远离接合垫。在某些变型中,剔除装置220包括钻孔机构以在缺陷被识别时磨出引线框架的至少一部分。在某些变型中,剔除装置220包括模具冲压机构以在缺陷被识别时冲压出引线接合的至少一部分。如果误差在晶粒附接参数中并且测量与引线接合不相关,则这可能是有用的。改变的引线接合可为有缺陷的引线接合或者可为便于切割、提升、钻孔或冲压的任何引线接合以使得组件不能通过电连续性测试。缺陷装置可由剔除装置剔除或者可在组装过程的下游通过某种装置从过程中剔除。
在一些例子中,剔除装置220标记缺陷电子组件。在各变型中,剔除装置220用颜色或划线标记缺陷电子组件。在某些变型中,标记是机器可识别的,并且引线接合器系统下游的装置从制造过程剔除缺陷部件。在某些变型中,标记足够大以由操作者在无需视觉辅助(诸如显微镜)的情况下识别,并且缺陷部件由操作者剔除。
在一些例子中,引线接合器系统包括控制器235。控制器235可使用硬件电路、固件、软件或硬件、固件和软件的任何组合来实施。例子包括处理器,诸如微处理器、专用集成电路(ASIC)或其他类型的处理器。控制器235(由硬件、固件或软件)被构造为执行所描述的功能。这些功能对应于模块,所述模块为软件、硬件、固件或它们的任何组合。多种功能可在模块中的一个或多个中执行。
引线接合器系统可包括与控制器成整体或者电耦合到控制器235的存储器电路。剔除装置220可将标识符存储在存储器电路中以识别使用一个或多个三维测量确定的缺陷电子组件。缺陷组件然后可被跟踪或电子映射。电子映射可使下游装置能够使用标识符从过程中剔除缺陷部件。在一些例子中,当与引线接合相关联的三维测量不满足三维测量的规定范围时,引线接合器系统可生成误差消息。操作者然后可采取措施来纠正误差。
将检查与引线接合集成可提供引线接合工艺的实时反馈控制。测量装置215可在引线接合器系统的测量装置和引线接合装置之间传送至少一个三维测量。在一些例子中,三维测量由控制器235接收。控制器235响应于所传送的测量来调整引线接合装置的至少一个引线接合参数。在一些例子中,当与引线接合相关联的三维测量不满足三维测量的规定范围时,控制器235调整引线接合参数。例如,如果测量结果指示引线接合位置在规定范围之外,则控制器235可调整位置以使测量回到范围内。在一些例子中,控制器235计算位置的测量结果和规定值之间的误差并且调整引线接合位置以使误差最小化。类似地,控制器235可提供其他引线接合测量(诸如引线接合环路高度和引线接合长度)的反馈调整。
在一些例子中,控制器235在制造过程的晶粒附接步骤期间接收装置(诸如放置在基板上的一个或多个装置)旋转的三维量度。如果三维测量结果指示引线接合位置在规定范围之外,则控制器235可调整旋转以使测量回到范围内。这可能有助于引线接合器系统的初始设置。操作者可物理地设置初始引线接合位置。该初始位置可能是不正确的,并且可能是故意不正确的。引线接合器系统可使用反馈控制通过使编程误差最小化而达到与正确设置的误差归零。
控制器可基于三维测量采取不同的行动。所采取的行动可取决于故障类型、故障次数和故障严重程度中的一个或多个。在某些例子中,行动基于统计过程控制(SPC)分析。例如,控制器235可能直到测量结果中的误差超过阈值或在规定范围之外才尝试调整引线接合器或晶粒附接参数。控制器235可仅仅记录测量结果或指示测量结果的偏差,直到误差达到预定严重程度。
在一些例子中,引线接合器系统包括与控制器235电连通的用户界面。用户界面可包括小键盘、键盘、计算机鼠标和显示器中的一个或多个。控制器可被编程以显示三维测量中的一个或多个。在一些变型中,当三维测量在规定范围之外时,或者测量结果以其他方式指示引线接合工艺有误差时,控制器235生成警报。警报可使用用户界面显示。在某些变型中,警报被传送(例如,使用有线或无线通信信号传送)到单独装置或系统以用于向用户显示。在某些变型中,三维测量中的一个或多个被传送并且存储在数据库(例如,存储在服务器上的数据库)中以用于未来的SPC数据分析或实时数据分析。如果SPC分析检测到异常情况或规格之外的情况,则警报可被用来(例如,由控制器、单独装置或使用者)停止引线接合和/或晶粒附接工艺或者在当前批次的组件结束时停止该工艺。
图4示出具有反馈控制的引线接合系统中的工艺流程的示意图。在框405处,电子装置(诸如半导体装置)被输入到引线接合系统中。在框410处,装置执行晶粒附接或引线接合以形成电子组件或子组件。在框415处,确定一个或多个测量结果(例如,三维测量或二维测量)。测量结果与引线接合和晶粒附接中的一者或两者相关联。一个或多个测量结果在框435处被反馈以将工艺参数维持在规定范围内。如果测量表明误差,则晶粒附接工艺和引线接合工艺中的一者或两者可被调整。
在框420处,诸如通过本文先前所述的方法中的任一种来识别缺陷装置。在框425处,没有缺陷的装置被传递到引线接合站的输出。具有缺陷的装置可被收集在报废站处,或者可被传递到输出以便稍后由另一个装置剔除。
本文所述的系统、装置和方法相较于离线并与组装过程分开进行的检查(手动或自动)有若干优点。引线接合和晶粒附接中的一者或两者的检查和监测在引线接合和晶粒附接进行时实时执行。这减少了在过程离线之后分开检查所需的时间和地面空间。这也可消除需要由操作者进行检查,从而减少时间和成本。与引线接合和晶粒附接实时的检查和监测允许系统的过程表征和SPC。这也使基于机器的立即交互能够解决所检测到的误差。这允许缺陷装置从组装过程被快速移除以减少由使用缺陷部件而产生的下游组装成本。
附加注释和实例
实例1可包括包含引线接合器系统的主题(诸如设备),该引线接合器系统包括被构造为将引线接合型电互连件附接到电子组件的引线接合装置。引线接合在第一半导体装置和第二电子装置之间形成,以形成电子组件的至少一部分。该主题也可包括被构造为进行与引线接合相关联的三维测量的测量装置,以及被构造为根据三维引线接合测量识别应予剔除的电子组件的剔除装置。
在实例2中,实例1的主题可任选地包括控制器,该控制器被构造为从测量装置接收至少一个三维测量并且响应于所传送的测量来调整引线接合装置的至少一个引线接合参数。
在实例3中,实例2的主题可任选地包括被构造为生成半导体装置的旋转量度的测量装置,其中控制器被任选地构造为响应于所生成的旋转量度而调整至少一个引线接合参数。
在实例4中,实例1-3中的一项或任何组合的主题可任选地包括被构造为根据三维引线接合测量选择性地改变电子组件的剔除装置。
在实例5中,实例1-4中的一项或任何组合的主题可任选地包括剔除装置,该剔除装置被构造为在与引线接合相关联的三维测量不满足三维测量的规定范围时,在引线接合中形成电不连续性。
在实例6中,实例1-5中的一项或任何组合的主题可任选地包括剔除装置,该剔除装置被构造为在与引线接合相关联的三维测量不满足三维测量的规定范围时,标记电子组件的至少一部分。
在实例7中,实例1-6中的一项或任何组合的主题可任选地包括电耦合到剔除装置或与剔除装置成整体的存储器电路,其中剔除装置被构造为在与引线接合相关联的三维测量不满足三维测量的规定范围时,对于电子组件的至少一部分将标识符存储在存储器电路中。
在实例8中,实例1-7中的一项或任何组合的主题可任选地包括测量装置,该测量装置被构造为生成引线接合的环路高度和引线接合的位置中的一者或两者的三维测量。
在实例9中,实例1-8中的一项或任何组合的主题可任选地包括晶粒附接装置,该晶粒附接装置被构造为堆叠第一半导体装置和至少一个第二半导体装置作为电子组件的一部分,并且其中测量装置被构造为生成第一半导体装置和至少一个第二半导体装置的堆叠高度的三维测量。
在实例10中,实例1-9中的一项或任何组合的主题可任选地包括具有三维成像装置的测量装置。
在实例11中,实例1-10中的一项或任何组合的主题可任选地包括具有激光或红外成像装置中的至少一者的测量装置。
在实例12中,实例1-11中的一项或任何组合的主题可任选地包括引线接合装置,该引线接合装置被构造为对于多个电子组件形成电子组件的至少一部分,并且其中测量装置被构造为在小于由引线接合装置形成的所有多个电子组件上进行三维测量。
在实例13中,实例1-12中的一项或任何组合的主题可任选地包括引线接合装置,该引线接合装置被构造为在第一半导体装置和用于第一半导体装置或第二半导体装置的引线框架中的至少一个之间形成引线接合。
实例14可包括主题(诸如方法、执行动作的装置或包括指令的机器可读介质,该指令由机器执行时,使得机器执行动作),或者可任选地与实例1-13中的一项或任何组合的主题组合以涵盖此类主题,包括由引线接合器系统附接一个或多个引线接合以在第一半导体装置和第二电子装置之间形成一个或多个电互连以形成第一电子组件的至少一部分;由引线接合器系统的测量装置进行与一个或多个引线接合相关联的一个或多个三维测量;以及由引线接合器系统的剔除装置根据三维引线接合测量选择性地识别应予剔除的第一电子组件。
在实例15中,实例14的主题可任选地包括由引线接合器系统在进行与第一电子组件的一个或多个引线接合相关联的一个或多个三维测量期间形成第二电子组件的至少一部分。
在实例16中,实例14和15中的一者或两者的主题可任选地包括在改变第一电子组件期间开始与第二电子组件的一个或多个引线接合相关联的一个或多个三维测量。
在实例17中,实例14-16中的一项或任何组合的主题可任选地包括在引线接合器系统的测量装置和引线接合装置之间传送至少一个三维测量,以及响应于所传送的测量而通过引线接合器系统调整至少一个引线接合参数。
在实例18中,实例14-17中的一项或任何组合的主题可任选地包括生成引线接合的环路高度和引线接合的位置中的一个或多个的三维测量。
在实例19中,实例14-18中的一项或任何组合的主题可任选地包括堆叠第一半导体装置和至少一个第二半导体装置以形成第一电子组件的至少一部分,其中进行一个或多个三维测量包括生成第一半导体装置和至少一个第二半导体装置的IC堆叠高度的三维测量。
在实例20中,实例14-19中的一项或任何组合的主题可任选地包括使用三维成像装置进行一个或多个三维测量。
在实例21中,实例14-20中的一项或任何组合的主题可任选地包括在与引线接合相关联的三维测量不满足三维测量的规定范围时,移除引线接合的电连续性。
在实例22中,实例14-21中的一项或任何组合的主题可任选地包括在与引线接合相关联的三维测量不满足三维测量的规定范围时,选择性地标记第一电子组件的IC管芯或电子装置中的至少一者。
实例23可以包括或可任选地与实例1至22中任何一项或多项的任何部分或任何部分的组合相结合,以涵盖可包括用于执行实例1至22的功能中任何一者或多者的装置或含指令的机器可读介质的主题,所述指令当由机器执行时会使机器执行实例1至22的功能中的任何一者或多者。
这些非限制性实例可以任何排列或组合来进行组合。
上述具体实施方式包括对附图的参考,这些附图形成具体实施方式的一部分。附图以举例说明的方式示出了可实施本发明的具体实施例。这些实施例在本文中也称为“实例”。在本文件中提及的所有出版物、专利和专利文件的全文以引用方式并入本文,如同以引入方式单独并入一样。如果本文与以引用方式并入的那些文件的用法相矛盾,则所并入的参考文献中的用法应视为对本文件的补充;若两者之间存在不能协调的差异,则以本文件的用途为准。
在本文件中,术语“一个”或“一种”如专利文件中常见的,用来包括一个或一个以上,而与“至少一个”或“一个或多个”的任何其他情况或用法无关。在本文件中,除非另外指明,否则术语“或”用来指非排他性的或,使得“A或B”包括“A而非B”、“B而非A”以及“A和B”。在所附权利要求书中,术语“包括”和“在其中”用作各自术语“包含”和“其中”的通俗英语等同物。而且,在所附权利要求中,术语“包括”和“包含”是开放式的,即,包括除了在权利要求中这样的术语之后列出的那些元件之外的元件的系统、装置、物品或方法仍将认为落入该权利要求范围内。此外,在以下权利要求书中,术语“第一”、“第二”和“第三”等仅仅用作标号,并非旨在将数字要求强加于它们的对象。
本文所述的方法实例可以至少部分地由机器或计算机实现。一些实例可包括使用指令编码的计算机可读介质或机器可读介质,该指令可操作将电子装置配置成执行上述实例中描述的方法。这类方法的实现可包括代码,诸如微码、汇编语言代码、高级语言代码等。该代码可包括用于执行各种方法的计算机可读指令。该代码可形成计算机程序产品的一部分。另外,在执行期间或其他时间,该代码可有形地存储在一个或多个易失性或非易失性计算机可读介质中。这些计算机可读介质可包括但不限于硬盘、可移除磁盘、可移除光盘(例如,高密度磁盘和数字视频盘)、磁带、存储卡或存储棒、随机存取存储器(RAM)、只读存储器(ROM)等。
以上说明旨在是示例性的,而非限制性的。例如,上述实例(或其一个或多个方面)可彼此结合使用。其他实施例可诸如由本领域的普通技术人员在查看上述说明后使用。根据专利实施细则37C.F.R.§1.72(b)提供说明书摘要,以便读者快速确定本技术公开的实质。说明书摘要的提交不旨在用于解释或限制权利要求的范围或含义。同样,在上面的具体实施方式中,可将各种特征归类以使本公开简明。这不应理解成未要求权利的公开特征对于任何权利要求必不可少。相反,本发明的主题具有的特征可少于特定公开的实施例的所有特征。因此,下面的权利要求据此并入具体实施方式中,每个权利要求自身代表独立的实施例。应结合所附权利要求以及这些权利要求所拥有的等同物的所有范围来确定本发明的范围。

Claims (20)

1.一种包括引线接合器系统的设备,所述引线接合器系统包括:
被构造为将引线接合型电互连件附接到电子组件的引线接合装置,其中引线接合在第一半导体装置和第二电子装置之间形成,以形成所述电子组件的至少一部分;
被构造为进行与引线接合相关联的三维测量的测量装置;以及
被构造为根据所述三维引线接合测量识别应予剔除的电子组件的剔除装置。
2.根据权利要求1所述的设备,包括控制器,其中所述控制器被构造为从所述测量装置接收至少一个三维测量并且响应于所述所传送的测量来调整所述引线接合装置的至少一个引线接合参数。
3.根据权利要求2所述的设备,其中所述测量装置被构造为生成所述半导体装置的旋转量度,其中所述控制器被构造为响应于所述所生成的旋转量度而调整至少一个引线接合参数。
4.根据权利要求1-3中任一项所述的设备,其中所述剔除装置被构造为根据所述三维引线接合测量选择性地改变电子组件。
5.根据权利要求1-4中任一项所述的设备,其中所述剔除装置被构造为在与所述引线接合相关联的三维测量不满足所述三维测量的规定范围时,在引线接合中形成电不连续性。
6.根据权利要求1-5中任一项所述的设备,其中所述剔除装置被构造为在与所述引线接合相关联的三维测量不满足所述三维测量的规定范围时,标记电子组件的所述至少一部分。
7.根据权利要求1-6中任一项所述的设备,其中引线接合器系统包括电耦合到所述剔除装置或与所述剔除装置成整体的存储器电路,其中所述剔除装置被构造为在与所述引线接合相关联的三维测量不满足所述三维测量的规定范围时,对于电子组件的所述至少一部分将标识符存储在所述存储器电路中。
8.根据权利要求1-7中任一项所述的设备,其中所述测量装置被构造为生成引线接合的环路高度和引线接合的位置中的一者或两者的三维测量。
9.根据权利要求1-8中任一项所述的设备,包括晶粒附接装置,所述晶粒附接装置被构造为堆叠所述第一半导体装置和至少一个第二半导体装置作为所述电子组件的一部分,并且其中所述测量装置被构造为生成所述第一半导体装置和所述至少一个第二半导体装置的堆叠高度的三维测量。
10.根据权利要求1-9中任一项所述的设备,其中所述测量装置包括三维成像装置。
11.根据权利要求1-10中任一项所述的设备,其中所述测量装置包括激光或红外成像装置中的至少一者。
12.根据权利要求1-11中任一项所述的设备,其中所述引线接合装置被构造为对于多个电子组件形成电子组件的所述至少一部分,并且其中所述测量装置被构造为在小于由所述引线接合装置形成的所有所述多个电子组件上进行所述三维测量。
13.根据权利要求1-12中任一项所述的设备,其中所述引线接合装置被构造为在所述第一半导体装置和用于所述第一半导体装置或所述第二半导体装置的引线框架中的至少一个之间形成引线接合。
14.一种方法,所述方法包括:
由引线接合器系统附接一个或多个引线接合以在第一半导体装置和第二电子装置之间形成一个或多个电互连,以形成第一电子组件的至少一部分;
由所述引线接合器系统的测量装置进行与所述一个或多个引线接合相关联的一个或多个三维测量;以及
由所述引线接合器系统的剔除装置根据所述三维引线接合测量选择性地识别应予剔除的所述第一电子组件。
15.根据权利要求14所述的方法,包括由所述引线接合器系统在进行与所述第一电子组件的所述一个或多个引线接合相关联的所述一个或多个三维测量期间形成第二电子组件的至少一部分。
16.根据权利要求14-15中任一项所述的方法,包括在改变所述第一电子组件期间开始与第二电子组件的一个或多个引线接合相关联的一个或多个三维测量。
17.根据权利要求14-16中任一项所述的方法,所述方法包括:
在所述引线接合器系统的所述测量装置和引线接合装置之间传送至少一个三维测量;以及
响应于所述所传送的测量而通过所述引线接合器系统调整至少一个引线接合参数。
18.根据权利要求14-17中任一项所述的方法,其中进行一个或多个三维测量包括生成引线接合的环路高度和引线接合的位置中的一个或多个的三维测量。
19.根据权利要求14-18中任一项所述的方法,还包括堆叠所述第一半导体装置和至少一个第二半导体装置以形成所述第一电子组件的所述至少一部分,其中进行一个或多个三维测量包括生成所述第一半导体装置和所述至少一个第二半导体装置的IC堆叠高度的三维测量。
20.根据权利要求14-19中任一项所述的方法,其中进行一个或多个三维测量包括使用三维成像装置进行一个或多个三维测量。
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Publication number Priority date Publication date Assignee Title
CN111054638A (zh) * 2019-11-27 2020-04-24 奥特斯科技(重庆)有限公司 制造部件承载件的方法及在制造期间操控面板的设备
US11935221B2 (en) 2019-11-27 2024-03-19 AT&S (Chongqing) Company Limited User interface for judgment concerning quality classification of displayed arrays of component carriers

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5426000B2 (ja) * 2012-11-16 2014-02-26 株式会社新川 ワイヤボンディング装置及びワイヤボンディング方法
US11923208B2 (en) * 2017-05-19 2024-03-05 Illinois Tool Works Inc. Methods and apparatuses for chemical delivery for brush conditioning
US10658328B2 (en) * 2017-11-09 2020-05-19 Asm Technology Singapore Pte Ltd Detection of foreign particles during wire bonding
US20220230314A1 (en) * 2021-01-15 2022-07-21 Kulicke And Soffa Industries, Inc. Intelligent pattern recognition systems for wire bonding and other electronic component packaging equipment, and related methods
CN112992692B (zh) * 2021-05-19 2021-07-20 佛山市联动科技股份有限公司 一种全自动切割引线的方法及系统

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60187033A (ja) * 1984-03-07 1985-09-24 Toshiba Corp 半導体装置の自動ワイヤボンデイング方法
US4872052A (en) * 1986-12-03 1989-10-03 View Engineering, Inc. Semiconductor device inspection system
EP0634791A2 (en) * 1993-07-16 1995-01-18 Kaijo Corporation Wire bonder and wire bonding method
US5581632A (en) * 1994-05-02 1996-12-03 Cognex Corporation Method and apparatus for ball bond inspection system
JPH11150146A (ja) * 1997-11-19 1999-06-02 Nec Corp 外観検査機能付きワイヤボンディング装置
US20020090753A1 (en) * 2001-01-05 2002-07-11 Advanced Semiconductor Engineering Inc. Method for fabricating stacked chip package
CN101015054A (zh) * 2004-06-09 2007-08-08 飞兆半导体公司 用于封装集成电路晶片的封装和方法
US20130006565A1 (en) * 2010-03-16 2013-01-03 Jtekt Corporation Method and apparatus for determining acceptance/rejection of fine diameter wire bonding

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080763A (zh) * 1973-11-14 1975-07-01
JPS59150433A (ja) * 1983-02-05 1984-08-28 Fujitsu Ltd ワイヤ検査装置
US5030008A (en) * 1988-10-11 1991-07-09 Kla Instruments, Corporation Method and apparatus for the automated analysis of three-dimensional objects
US6289492B1 (en) * 1998-12-18 2001-09-11 Cognex Corporation Methods and apparatuses for defining a region on an elongated object
JP2001060605A (ja) * 1999-08-24 2001-03-06 Murata Mfg Co Ltd 実装基板上での電子部品の接合部の検査方法および装置
MY169616A (en) 2009-02-06 2019-04-23 Agency Science Tech & Res Methods for examining a bonding structure of a substrate and bonding structure inspection devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60187033A (ja) * 1984-03-07 1985-09-24 Toshiba Corp 半導体装置の自動ワイヤボンデイング方法
US4872052A (en) * 1986-12-03 1989-10-03 View Engineering, Inc. Semiconductor device inspection system
EP0634791A2 (en) * 1993-07-16 1995-01-18 Kaijo Corporation Wire bonder and wire bonding method
US5581632A (en) * 1994-05-02 1996-12-03 Cognex Corporation Method and apparatus for ball bond inspection system
JPH11150146A (ja) * 1997-11-19 1999-06-02 Nec Corp 外観検査機能付きワイヤボンディング装置
US20020090753A1 (en) * 2001-01-05 2002-07-11 Advanced Semiconductor Engineering Inc. Method for fabricating stacked chip package
CN101015054A (zh) * 2004-06-09 2007-08-08 飞兆半导体公司 用于封装集成电路晶片的封装和方法
US20130006565A1 (en) * 2010-03-16 2013-01-03 Jtekt Corporation Method and apparatus for determining acceptance/rejection of fine diameter wire bonding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111054638A (zh) * 2019-11-27 2020-04-24 奥特斯科技(重庆)有限公司 制造部件承载件的方法及在制造期间操控面板的设备
US11935221B2 (en) 2019-11-27 2024-03-19 AT&S (Chongqing) Company Limited User interface for judgment concerning quality classification of displayed arrays of component carriers

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