TW201440151A - 半導體裝置以及半導體裝置的製造方法 - Google Patents

半導體裝置以及半導體裝置的製造方法 Download PDF

Info

Publication number
TW201440151A
TW201440151A TW102135774A TW102135774A TW201440151A TW 201440151 A TW201440151 A TW 201440151A TW 102135774 A TW102135774 A TW 102135774A TW 102135774 A TW102135774 A TW 102135774A TW 201440151 A TW201440151 A TW 201440151A
Authority
TW
Taiwan
Prior art keywords
capillary
semiconductor device
wire
pad
electrode
Prior art date
Application number
TW102135774A
Other languages
English (en)
Other versions
TWI518814B (zh
Inventor
Shinji Kumamoto
Naoki Sekine
Motoki Nakazawa
Yasuo Nagashima
Original Assignee
Shinkawa Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Kk filed Critical Shinkawa Kk
Publication of TW201440151A publication Critical patent/TW201440151A/zh
Application granted granted Critical
Publication of TWI518814B publication Critical patent/TWI518814B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48455Details of wedge bonds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06506Wire or wire-like electrical connections between devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本發明提供一種半導體裝置及半導體裝置的製造方法。半導體裝置100交替地形成接合部75~接合部72及環接部85~環接部82,而接合部75~接合部72使導線12的側面接合於焊墊65~焊墊62,環接部85~環接部82自接合部75~接合部72環接至與焊墊65~焊墊62鄰接的其他焊墊64~焊墊61上為止,且包括依次連接3個以上的焊墊65~焊墊61的共用的導線12。在焊墊65~61自半導體晶片55~半導體晶片51的表面凹陷的情況下,將共用的導線12壓扁至比焊墊65~焊墊61的凹陷深度厚的厚度而形成扁平形狀。

Description

半導體裝置以及半導體裝置的製造方法
本發明是有關於一種半導體裝置的構造以及半導體裝置的製造方法。
近年來,根據半導體裝置的大容量化的要求,多使用將多個半導體晶片積層於基板或引線框架(lead frame)上而構成的積層型半導體裝置。而且,此種積層型半導體裝置中,同時有薄型化、小形化的要求,因而使用如下的打線接合(wire bonding)方法,即,並非將各層的半導體晶片的焊墊(pad)與引線框架分別加以連接,而是將鄰接的各半導體晶片的焊墊間或半導體晶片的焊墊與引線框架的引線之間利用導線依次連接。就該方法而言,使用的是如下的方法,即,為了在打線接合時不對半導體晶片造成損傷,首先,在各半導體晶片的各焊墊上形成凸塊(bump),然後,自引線框架的引線朝向半導體晶片的焊墊上進行逆接合,進而,自接合好的凸塊上朝向鄰接的半導體晶片的凸塊上進行下一逆接合,以此方式將導線自引線框架朝向最上層的半導體晶片 的焊墊依次連接(例如,參照專利文獻1)。
而且,提出有如下方法:在位於積層型半導體裝置的中間層的各焊墊面形成凸塊,對最上層的半導體晶片的焊墊進行球形接合,將導線環接(looping)至形成於中間層的焊墊上的凸塊上而接合在凸塊上,然後進而將導線環接至下一半導體晶片的凸塊上來進行接合,以此方式利用導線將鄰接的中間層的焊墊間予以連接(例如,參照專利文獻2)。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本專利第3573133號說明書
[專利文獻2]】日本專利第3662461號說明書
然而,專利文獻1中記載的現有技術中,是在各半導體晶片的焊墊上形成凸塊之後進行打線接合,因而存在步驟數多且接合耗費時間、成本的問題。例如,積層為兩層的積層型半導體的各焊墊與引線的連接需要:在兩層的各半導體晶片的焊墊上形成各個凸塊的步驟(2個步驟),引線與第一層半導體晶片的焊墊上的凸塊之間的接合,第一層凸塊與第二層半導體晶片的焊墊上的凸塊之間的接合這總計4個步驟。而且,專利文獻2中記載的現有技術中,是在位於中間層的半導體晶片的焊墊上形成凸塊之後進行接合,因而步驟數比專利文獻1記載的現有技術少,但須 有別於接合步驟而另外設置凸塊形成步驟,從而無法解決步驟數多的問題。
而且,半導體晶片中亦多使用焊墊自半導體晶片的表面凹陷的半導體晶片。如此,在自半導體晶片的表面凹陷的焊墊上進行接合的情況下,為了抑制毛細管(capillary)的前端觸碰到焊墊周邊的半導體晶片的表面,而無法增多導線的按壓量(毛細管下沉量)。因此,如專利文獻1、專利文獻2中記載的現有技術般,必須在焊墊上暫時形成凸塊後,在該凸塊上進行接合,從而存在無法進行有效率的接合的問題。
本發明的目的在於在半導體裝置中,減少對半導體晶片造成的損傷且以少的接合次數進行導線的連接。而且,本發明的目的在於對自半導體晶片的表面凹陷的電極有效率地進行接合。
本發明的半導體裝置的特徵在於:交替地形成有接合部以及環接部,接合部是使側面接合於電極,環接部則是自接合部環接至其他電極上為止,且上述半導體裝置包括將3個以上的電極依次連接的共用的導線。
本發明的半導體裝置中,較佳為電極為半導體晶片的焊墊,且較佳為半導體裝置為積層著半導體晶片的積層體,共用的導線將鄰接層的半導體晶片的電極間依次連接。
本發明的半導體裝置中,較佳為接合部為壓扁至共用的導線的直徑的1/4~1/2的厚度的扁平形狀,環接部包括自接合部 向斜上方向彎折而延伸的根(heel)部,根部的厚度為共用的導線的直徑的1/2~4/5的厚度。
而且,本發明的半導體裝置中,較佳為電極自半導體晶片的表面凹陷,接合部的厚度比電極的凹陷深度厚。
本發明的半導體裝置的製造方法是藉由共用的導線將3個以上的半導體晶片或基板的電極依次連接的打線接合方法,上述半導體裝置的製造方法的特徵在於交替地重複接合步驟及環接步驟,從而藉由上述共用的導線將3個以上的上述電極依次連接,其中接合步驟是藉由毛細管將導線的側面按壓至一電極,而將導線的側面接合於一電極,環接步驟則是在接合步驟之後,藉由毛細管使導線環接至其他電極上為止。
本發明的半導體裝置的製造方法中,較佳為接合步驟藉由毛細管將共用的導線壓扁至其直徑的1/4~1/2的厚度而形成扁平形狀,並且進行超音波激振而將共用的導線接合於各電極。
本發明的半導體裝置的製造方法中,較佳為環接步驟包括:第一上升步驟,在接合步驟之後,使毛細管自一電極垂直地上升;第一傾斜移動步驟,在第一上升步驟之後,使毛細管朝向其他電極而向斜下方向移動;第二上升步驟,在第一傾斜移動步驟之後,再次使毛細管垂直地上升;反向步驟,在第二上升步驟之後,使毛細管朝向其他電極的相反側而向斜下方向移動;第二傾斜移動步驟,在反向步驟之後,使毛細管向斜上方向移動至一電極正上方為止;第三上升步驟,在第二傾斜移動步驟之後,再 次使毛細管垂直地上升;以及弧狀移動步驟,在第三上升步驟之後,使毛細管朝向其他電極的正上方呈弧狀地移動。
本發明的半導體裝置的製造方法中,較佳為反向步驟使毛細管移動至相對於通過接合部且與電極垂直的線的角度為10°~20°的點為止。
本發明的半導體裝置的製造方法中,較佳為電極中的至少一個為自半導體晶片的表面凹陷的焊墊,接合步驟藉由毛細管將共用的導線壓扁至比焊墊的凹陷深度厚的厚度而形成扁平形狀,並且進行超音波激振而將共用的導線接合於焊墊。
本發明在半導體裝置中,實現如下的效果:可減少對半導體晶片造成的損傷且以少的接合次數進行導線的連接,並且對自半導體晶片的表面凹陷的電極有效率地進行接合。
10‧‧‧基板
12‧‧‧導線
13‧‧‧接合臂
13b‧‧‧超音波喇叭形輻射體
14‧‧‧接合載台
15‧‧‧超音波振盪器
16‧‧‧毛細管
16a‧‧‧孔
16b‧‧‧前端面
17‧‧‧夾持器
18‧‧‧移動機構
19‧‧‧接合頭
20‧‧‧XY平台
27‧‧‧夾持器開閉機構
28‧‧‧旋轉中心
29‧‧‧毛細管高度檢測器
30‧‧‧電腦
31‧‧‧控制部
32‧‧‧記憶部
33‧‧‧控制程式
34‧‧‧控制資料
35‧‧‧夾持器開閉機構介面
36‧‧‧毛細管高度檢測介面
37‧‧‧超音波振盪器介面
38‧‧‧移動機構介面
39‧‧‧資料匯流排
51~56‧‧‧半導體晶片
61~66‧‧‧焊墊
70‧‧‧電極
71~75‧‧‧接合部
71a~75a‧‧‧金屬接合部
71b~75b‧‧‧根部
71c~75c‧‧‧點
80‧‧‧無空氣焊球
81~86‧‧‧環接部
81a~86a‧‧‧始端部
82b~86b‧‧‧終端部
90‧‧‧壓接球
100‧‧‧半導體裝置
101‧‧‧打線接合裝置
a、b、c、d、e、f、g‧‧‧點
C1~C12‧‧‧高度
D‧‧‧導線12的直徑
D1‧‧‧凹陷深度
H1‧‧‧接合部75~接合部71的厚度(高度)
H2‧‧‧根部75b~根部71b的厚度(高度)
p、q‧‧‧箭頭
t1~t12‧‧‧時刻
X、Y、Z‧‧‧方向
θ1‧‧‧角度
圖1是表示本發明的實施形態的半導體裝置的構造的剖面圖。
圖2是表示本發明的實施形態的半導體裝置的接合部的立體圖。
圖3是表示形成本發明的實施形態的半導體裝置的接合部的步驟的說明圖。
圖4是本發明的實施形態的半導體裝置的接合部的側面圖。
圖5是製造本發明的實施形態的半導體裝置的打線接合裝置 的系統圖。
圖6的(a)~(d)是表示使用圖5所示的打線接合裝置製造本發明的半導體裝置的步驟的說明圖。
圖7的(e)~(h)是表示使用圖5所示的打線接合裝置製造本發明的半導體裝置的步驟的說明圖。
圖8是表示製造本發明的半導體裝置時的環接步驟中的毛細管前端的軌跡的說明圖。
圖9是本發明的其他實施形態的半導體裝置的接合部的側面圖。
以下,一面參照圖式一面對本發明的實施形態進行說明。如圖1所示,本實施形態的半導體裝置100是在基板10上積層多層半導體晶片56~半導體晶片51的積層體,藉由1根共用的導線12將作為設置於各半導體晶片56~半導體晶片51的表面的電極的焊墊66~焊墊61依次連接而成。如圖1所示,半導體晶片56~半導體晶片51為相互鄰接的層的半導體晶片,各焊墊66~焊墊61為相互鄰接的層的焊墊。而且,各焊墊66~焊墊61亦為相互鄰接的焊墊。共用的導線12可為金線,亦可為鋁線、銅線等。共用的導線12球形接合(ball bonding)於最上層的半導體晶片56的焊墊66上,且在焊墊66上形成著壓接球90。本實施形態的半導體裝置100形成著環接部86,該環接部86是使導線12自壓接球90側的始端部86a朝向下一層的半導體晶片55的焊墊65側 的終端部86b呈弧狀地環接而成。在環接部86的終端部86b,將導線12的側面按壓並接合於焊墊65上而形成接合部75。而且,再次使導線12自接合部75側的始端部85a朝向下一層的半導體晶片54的焊墊64側的終端部85b呈弧狀地環接,形成自焊墊65側的始端部85a朝向焊墊64側的終端部85b的弧狀的環接部85。在環接部85的終端部85b,將導線12的側面按壓並接合於焊墊64上而形成接合部74。同樣地,依次形成著環接部84、接合部73、環接部83、接合部72、環接部82、接合部71,最後導線12自焊墊61環接至基板10的電極70上而其側面接合於電極70上之後被切斷。如此,本實施形態的半導體裝置100中,藉由1個共用的導線12將各半導體晶片56~半導體晶片51的各焊墊66~焊墊61、及基板10的電極70依次連接。
亦即,本實施形態的半導體裝置100如圖1所示,交替地形成環接部86~環接部82、接合部75~接合部71,且將鄰接層的半導體晶片55~半導體晶片51的5個焊墊65~焊墊61利用1根導線12依次連接而成。另外,本實施形態中,在最上層的半導體晶片56的焊墊66進行球形接合而將導線12與焊墊66予以接合並進行了說明,但接合的方法並不限定於此,亦可如接合部75~接合部72般,將導線12的側面接合於焊墊66的表面。
其次,一邊參照圖2~圖4,一邊對本實施形態的半導體裝置100的接合部75~接合部71、環接部86~環接部82的終端部86b~終端部82b、環接部85~環接部81的始端部85a~始 端部81a的詳情進行說明。如圖2所示,接合部75~接合部71為厚度(高度)H1的橢圓形的扁平板狀,環接部86~環接部82的終端部86b~終端部82b與環接部85~環接部81的始端部85a~始端部81a分別自接合部75~接合部71的各長徑端朝向斜上方向延伸,並且其剖面形狀自扁平形狀變為直徑D的圓形。如圖2所示,環接部85~環接部81的始端部85a~始端部81a相對於焊墊66~焊墊61的表面以角度θ1向斜上方向延伸,根部75b~根部71b的厚度(高度)為厚度(高度)H2
如圖3所示,接合部75~接合部71將毛細管16的前端面16b如圖3所示的箭頭p般按壓至導線12的側面,將直徑D的圓形剖面的導線12壓扁至厚度(高度)H1的圓形或橢圓形的扁平的板狀而成。接合部75~接合部71的厚度(高度)H1為導線12的直徑D的1/4~1/2左右的厚度(高度)。而且,導線12藉由毛細管16的前端面16b壓扁至扁平形狀,並且如圖3的橫方向的箭頭q所示,沿水平方向施加超音波振動,藉此,形成圖3所示的金屬接合部75a~金屬接合部71a,將導線12的側面金屬接合於焊墊65~焊墊61上。
而且,如圖4所示,在鄰接於接合部75~接合部71的金屬接合部75a~金屬接合部71a的部分,導線12的側面成為與焊墊65~焊墊61的表面相接的狀態,在圖4的點75c~點71c導線12的側面自焊墊65~焊墊61的表面上升,且以角度θ1向斜上方延伸而與環接部85~環接部81的始端部85a~始端部81a相 連。自圖4所示的接合部75~接合部71經由點75c~點71c而與環接部85~環接部81的始端部85a~始端部81a相連為止的部分是根部75b~根部71b。根部75b~根部71b的接合部75~接合部71側的剖面與接合部75~接合部71同樣地成為導線12的直徑D的1/4~1/2的扁平形狀,並隨著朝向始端部85a~始端部81a而成為與導線12相同的直徑D的圓形剖面形狀。如圖4所示,點75c~點71c的根部75b~根部71b的厚度(高度)H2為導線12的直徑D的1/2~4/5左右,成為接合部75~接合部71的厚度(高度)的約2倍的厚度(高度)。
接合部75~接合部71僅壓扁至導線12的直徑D的1/4~1/2的厚度(高度)H1為止,因而維持著與根部75b~根部71b相連的充分的強度。而且,根部75b~根部71b的厚度(高度)H2為如下的厚度(高度),即,在環接時能夠使導線12自根部75b~根部71b與環接部85~環接部81的始端部85a~始端部81a相連而不會產生龜裂等損傷。根部75b~根部71b的角度θ1較佳設為45°~60°左右。而且,如以後說明般,在形成接合部75~接合部71時將超音波振盪器的輸入電壓設為通常的第二接合的1.5倍左右,因而即便以少的壓扁量亦可充分形成金屬接合部75a~金屬接合部71a,從而導線12的側面與焊墊66~焊墊61的接合強度充分,在環接時導線12不會自焊墊66~焊墊61剝離。
在以上說明的實施形態中,接合部75~接合部71的厚度(高度)H1設為導線12的直徑D的1/4~1/2並進行了說明, 但並不限定於此,例如亦可為導線12的直徑D的8/30~12/30,若為導線12的直徑D的9/30~11/30或者1/3左右則更佳。而且,根部75b~根部71b的厚度(高度)H2設為導線12的直徑D的1/2~4/5並進行了說明,但並不限定於此,例如亦可設為導線12的直徑D的16/30~24/30,若為18/30~22/30或2/3左右則更佳。
其次,參照圖5~圖8對藉由打線接合裝置101製造參照圖1~圖4說明的實施形態的半導體裝置100的步驟進行說明。首先,一邊參照圖5一邊對半導體裝置100的製造中使用的打線接合裝置101進行說明。圖5中,信號線由單點鏈線表示。如圖5所示,打線接合裝置101包括XY平台(table)20、設置於XY平台20上的接合頭19、及吸附固定基板10的接合載台(stage)14。在接合頭19上安裝著藉由Z方向馬達而繞旋轉中心28驅動的接合臂13,並在其前端安裝著超音波喇叭形輻射體(Ultrasonic Horns)13b,超音波喇叭形輻射體13b的前端以相對於接合載台14的表面呈弧狀地進行相接或離開動作的方式而構成。超音波喇叭形輻射體13b的前端在接合載台14的表面的附近沿作為上下方向的Z方向移動。而且,在超音波喇叭形輻射體13b的根部安裝著超音波振盪器15,且構成為對安裝於超音波喇叭形輻射體13b的前端的毛細管16進行超音波激振。XY平台20與接合頭19構成移動機構18,移動機構18可藉由XY平台20而將接合頭19在沿著接合載台14的表面的面內(XY面內)移動至隨意的位置,從而可使安裝於接合臂13的前端的超音波喇叭形輻射體13b的前 端及安裝於該前端的毛細管16沿XYZ方向自如地移動。
如圖5所示,打線接合裝置101藉由內部具有中央處理單元(Central Processing Unit,CPU)的控制部31進行各部的位置的檢測及動作的控制。在XY平台20中內置著對接合頭19的XY方向位置進行檢測的XY位置檢測單元。而且,接合頭19上設置著毛細管高度檢測器29,該毛細管高度檢測器29藉由對接合臂13的繞旋轉中心28的旋轉角度進行檢測而檢測毛細管16前端的Z方向高度。毛細管高度檢測器29亦可不檢測旋轉角度,而直接檢測接合臂13前端或毛細管16前端的位置。而且,毛細管高度檢測器29可為非接觸式,亦可為接觸式。
毛細管高度檢測器29的檢測信號經由毛細管高度檢測介面36自資料匯流排39輸入至包含CPU的控制部31。而且,包含XY平台20與接合頭19的移動機構18、夾持器開閉機構27、超音波振盪器15構成為:分別經由移動機構介面38、夾持器開閉機構介面35、超音波振盪器介面37而自資料匯流排39連接至控制部31,且藉由來自控制部31的指令使各機器動作。
資料匯流排39上連接有記憶部32。記憶部32中儲存著對接合控制整體進行控制的控制程式33、及控制部31進行位置檢測處理或控制指令輸出動作所需的控制資料34,且控制部31、資料匯流排39、記憶部32及各介面35~介面38是作為一體而構成的電腦30。
對藉由如以上般構成的打線接合裝置101製造圖1所示 的半導體裝置100的方法進行說明。如圖5所示,在接合載台14的表面,藉由未圖示的黏晶機(die bonder)裝置等吸附固定有基板10,該基板10是階梯狀地積層固定著大小不同的半導體晶片56~半導體晶片51所得(圖1中未圖示積層數)。而且,如圖6的(a)所示,毛細管16位於最上層的半導體晶片56的焊墊66的正上方,其前端的高度成為高度C1。
控制部31在圖6的(a)~(d)的時刻t1使毛細管16自高度C1朝向最上層的半導體晶片56的焊墊66下降而開始球形接合。毛細管16的高度藉由圖5所示的毛細管高度檢測器29而檢測,且自毛細管高度檢測介面36輸入至控制部31。控制部31若在圖6的(a)~(d)的時刻t2被輸入毛細管16的高度已下降至高度C3為止的信號,則延緩毛細管16的下降速度,一邊搜尋毛細管16前端的無空氣焊球(free air ball)80是否接地到焊墊66的表面一邊使毛細管16進一步下降。而且,控制部31在圖6的(a)~(d)的時刻t3毛細管16成為高度C4,並檢測到無空氣焊球80接地到焊墊66的表面的信號後,使毛細管16進一步下降而將無空氣焊球80按壓至焊墊66的表面從而形成壓接球90。與此同時,控制部31使圖5所示的超音波振盪器15通電而產生超音波振動,藉由毛細管16以規定的時間對壓接球90進行超音波激振而使其金屬接合在焊墊66的表面。在接地的檢測中,例如當藉由毛細管高度檢測器29檢測的信號在每規定的單位時間內不發生變化時,可判斷為接地,而且,亦可對半導體晶片56與導線12 之間施加電壓,而對半導體晶片56與導線12之間流動電流進行檢測。
控制部31在圖6的(a)~(d)的時刻t4結束球形接合後,如圖6的(c)、(d)所示開始進行第二接合。控制部31在使毛細管16上升至高度C2為止後,使毛細管16的前端呈弧狀地朝向下一層的半導體晶片55的焊墊65移動並使毛細管16移動至焊墊65的正上方為止,並且使毛細管16下降至高度c5為止。然後,控制部31在圖6的(a)~(d)的時刻t5毛細管的高度成為C5後,延緩毛細管16的下降速度,一邊搜尋毛細管16前端的導線12的側面是否接地到焊墊65的表面一邊使毛細管16進一步下降。然後,控制部31在圖6的(a)~(d)的時刻t6毛細管16成為高度C8,並檢測到導線12的側面已接地到焊墊65的表面的信號後,如圖3所示,將毛細管16的前端面16b按壓至導線12的側面。控制部31藉由圖5所示的毛細管高度檢測器29檢測毛細管16的下沉量、亦即導線12的壓扁量,將導線12壓扁導線12的直徑D的2/3左右,並按壓導線12直至接合部75的厚度(高度)H1為導線12的直徑D的1/3左右。然後,在接合部75的厚度(高度)H1為導線12的直徑D的1/3左右時停止按壓。而且,與導線12的按壓一併,控制部31使圖5所示的超音波振盪器15通電而產生超音波振動,藉由毛細管16以規定的時間對接合部75進行超音波激振而在其與焊墊65的表面之間形成金屬接合部75a。若在圖7的(e)~(h)所示的時刻t7形成接合部75,則焊 墊66與焊墊65藉由環接部86而連接。環接部86如參照圖2、圖4說明般具備焊墊66側的始端部86a與焊墊65側的終端部86b,終端86b與連接部75相連。若形成接合部75,則對焊墊65的第二接合結束。若第二接合結束,則如圖3所示,插通至毛細管16的孔16a的導線12自焊墊65向大致垂直上方延伸。
在對焊墊65的第二接合結束後,控制部31如圖8所示進行使毛細管16的前端移動的環接。控制部31使毛細管16自焊墊65向垂直上方上升至圖8的點a為止(第一上升步驟)。繼而自圖8所示的點a朝向點b,即,自焊墊65朝向繼而進行接合的焊墊64的方向,使毛細管16呈圓弧狀地向斜下方向移動(第一傾斜移動步驟)。然後,控制部31使毛細管16自點b垂直地上升至點c為止(第二上升步驟)。使毛細管16移動至點c為止後,控制部31進行反向步驟。反向步驟使毛細管16自點c朝向下一焊墊64的相反側而呈圓弧狀地向斜下方向移動至點d為止。點d是相對於通過接合部75且與焊墊65垂直的線(第一上升步驟時的毛細管16的軌跡)的角度為10°~20°的點。毛細管16若移動至點d為止,則如圖7的(e)所示,在毛細管16的前端彎曲傾斜(bending inclination)的導線12成為自接合部75延伸的狀態。繼而,控制部31使毛細管16沿著剛才的反向步驟的自點c到點d為止的毛細管16的軌跡而朝向下一焊墊64向斜上方向移動,從而使毛細管16的位置為焊墊65的正上方的點e(第二傾斜移動步驟)。然後,控制部31使毛細管16自點e再次垂直地上升至點f 為止(第三上升步驟)。然後,控制部31使毛細管16自點f呈弧狀地移動至焊墊64的正上方的點g為止。如此,以自焊墊65經過第一上升步驟、第一傾斜移動步驟、第二上升步驟、反向步驟、第二傾斜移動步驟、第三上升步驟的方式使毛細管16移動後,使毛細管16朝向焊墊64正上方的點g呈弧狀地移動,藉此形成如參照圖2、圖4說明般形狀的根部75b~根部71b及環接部85的始端部85a。尤其於反向步驟中,使毛細管移動至相對於通過接合部75且與焊墊65垂直的線(第一上升步驟時的毛細管16的軌跡)的角度為10°~20°的點d為止,藉此形成根部75b的厚度(高度)H2與朝向斜上方45°~60°的角度θ1
而且,若在圖7的(e)~(h)所示的時刻t8毛細管16下降至高度C9為止,則與先前對焊墊65形成接合部75同樣地,減小毛細管16的下降速度,進行檢測毛細管16前端的導線12的側面是否接地到焊墊64的搜尋動作,並在圖7的(e)~(h)的時刻t9毛細管16成為高度C10,檢測到導線12的側面接地到焊墊64的表面的信號後,如圖3所示,將毛細管16的前端面16b按壓至導線12的側面,一邊藉由毛細管高度檢測器29控制毛細管16的下沉量,一邊將導線12按壓至接合部74的厚度(高度)H1為導線12的直徑D的1/3左右為止,並且使超音波振盪器15通電而產生超音波振動,藉由毛細管16以規定的時間對接合部74進行超音波激振而在其與焊墊64的表面之間形成金屬接合部74a。若在圖7的(e)~(h)的時刻t10形成接合部74,則焊墊 65與焊墊64藉由具有始端部85a及終端部85b的環接部85連接。若形成接合部74,則對焊墊64的第二接合結束。
在圖7的(e)~(h)的時刻t10對焊墊64的第二接合結束後,控制部31與先前說明的焊墊65與焊墊64之間的連接同樣地,如圖7的(g)、(h)所示,自焊墊64以如自圖8所示的點a到f般的軌跡而使毛細管16移動後,使毛細管16朝向焊墊63環接,並在圖7的(e)~(h)的時刻t11毛細管16成為高度C11後,減小毛細管16的下降速度,一邊進行搜尋一邊使毛細管下降至導線12的側面與焊墊63的表面相接為止,並在圖7的(e)~(h)的時刻t12檢測到接地後,一邊藉由毛細管高度檢測器29檢測毛細管16的高度一邊將導線12按壓至焊墊63,並且對超音波振盪器15施加電壓,對接合部73進行超音波激振而形成圖3所示的金屬接合部73a。
以下,同樣地藉由1根共用的導線12將焊墊63與焊墊62、焊墊62與焊墊61依次連接。而且,在對焊墊61的第二接合結束後,控制部31使毛細管16朝向基板10的電極70環接,在基板10的電極70上進行通常的第二接合後,使毛細管16上升,之後閉合圖5所示的夾持器17而使毛細管16進一步上升,切斷導線12,從而結束1根導線12的接合。此處,對基板10的電極70的通常的第二接合以能夠順暢地進行對導線12的切斷的方式,使導線12的壓扁量為形成接合部75~接合部71時的導線12的壓扁量的2倍以上,且按壓負載亦比形成接合部75~接合部71 時的按壓負載大得多。另一方面,因按壓負載大,故即便超音波激振少但亦可將導線12與電極70充分地進行金屬接合,因而施加至超音波振盪器15的電壓比形成接合部75~接合部71時的電壓小,例如為1/1.5左右。
在以上說明的本實施形態中,導線12的壓扁量少,為接合之後切斷導線12而形成導線尾端(wire tail)的通常的第二接合時的壓扁量的一半左右,且導線12的按壓負載亦少,因而即便將導線12的側面直接接合於半導體晶片55~半導體晶片51的焊墊65~焊墊61的表面,對半導體晶片55~半導體晶片51造成的損傷亦減小。而且,超音波激振藉由將通常的第二接合時的1.5倍左右的電壓施加至超音波振盪器15而進行,即便按壓負載少亦可充分地形成圖3所示的金屬接合部75a~金屬接合部71a,從而確保導線12與焊墊65~焊墊61的接合強度。進而,藉由將接合部75~接合部71的厚度(高度)H1設為導線12的直徑D的1/3左右的厚度(高度),而環接部86~環接部82的終端部86b~終端部82b以及環接部85~環接部81的始端部85a~始端部81a與接合部75~接合部71順暢地相連,不會產生龜裂等,可良好地將導線12的側面接合於焊墊65~焊墊61,藉此可利用1根導線12將焊墊65~焊墊61予以連接。
而且,本實施形態中,藉由毛細管高度檢測器29檢測毛細管16的高度並控制導線12的壓扁量,將接合部75~接合部71的高度設為導線12的直徑D的1/3左右並進行了說明,但亦可 預先按導線12的直徑D或材料對按壓負載與導線12的壓扁量的關係進行作圖,藉由檢測毛細管16的按壓負載來控制導線12的壓扁量從而使接合部75~接合部71的高度為導線12的直徑D的1/3左右。該情況下,亦可使按壓負載比通常的第二接合低,因而可抑制對半導體晶片55~半導體晶片51的損傷。
如以上所述般,本實施形態的打線接合方法可減少對半導體晶片55~半導體晶片51造成的損傷並以少的接合次數進行共用的導線12的連接,因而可有效率地製造半導體裝置100。而且,本發明的半導體裝置100利用1根導線12將半導體晶片55~半導體晶片51的各焊墊65~焊墊61依次連接,因而各焊墊65~焊墊61與導線12之間的金屬接合面為一個,從而與在焊墊65~焊墊61上形成凸塊並進行接合的情況相比,各焊墊65~焊墊61與共用的導線12之間的導通電阻減少,因而可降低各焊墊65~焊墊61間的電性連接電阻,從而可製成可靠性高的半導體裝置。
其次,一邊參照圖9一邊對本發明的其他實施形態進行說明。對與先前參照圖1~圖8說明的實施形態相同的部分附上相同的符號並省略說明。先前參照圖1至圖8說明的實施形態中,半導體晶片56~半導體晶片51的各焊墊66~焊墊61設為自各半導體晶片56~半導體晶片51的表面突出的形狀並進行了說明,但有時半導體晶片56~半導體晶片51中焊墊66~焊墊61亦成為自半導體晶片56~51的表面凹陷的凹部。將導線12的側面按壓至此種凹部形狀的焊墊65~焊墊61而形成接合部75~接合部71 時,必須使圖3所示的毛細管16的前端面16b不觸碰到半導體晶片55~半導體晶片51的表面。該情況下,以接合部75~接合部71的厚度(高度)H1高於焊墊65~焊墊61的凹陷深度D1的方式,控制接合時的毛細管16的下沉量。而且,在凹陷深度D1比導線12的直徑D的1/3左右深的情況下,因接合部75~接合部71的厚度(高度)H1比1/3厚,故亦可為了確保接合部75~接合部71的金屬接合部75a~金屬接合部71a的接合強度,進一步增大輸入至超音波振盪器15的電壓。除上述方面以外,本實施形態與參照圖1~圖8說明的半導體裝置100相同,其製造步驟亦相同。
本實施形態的效果除先前說明的實施形態外,因在各焊墊65~焊墊61自各半導體晶片55~半導體晶片51的表面凹陷的情況下,亦可確保導線12與各焊墊65~焊墊61的接合強度,故即便對自半導體晶片55~半導體晶片51的表面凹陷的焊墊65~焊墊61亦無須暫時形成凸塊,而可將導線12的側面直接接合於焊墊65~焊墊61的表面,因而即便在焊墊65~焊墊61自半導體晶片55~半導體晶片51的表面凹陷的情況下,亦實現短時間內能夠進行接合的效果。
10‧‧‧基板
12‧‧‧導線
51~56‧‧‧半導體晶片
61~66‧‧‧焊墊
70‧‧‧電極
71~75‧‧‧接合部
81~86‧‧‧環接部
81a~86a‧‧‧始端部
82b~86b‧‧‧終端部
90‧‧‧壓接球
100‧‧‧半導體裝置

Claims (10)

  1. 一種半導體裝置,其特徵在於:交替地形成有接合部以及環接部,接合部是使側面接合於電極,環接部則是自上述接合部環接至其他電極上為止,且上述半導體裝置包括將3個以上的上述電極依次連接的共用的導線。
  2. 如申請專利範圍第1項所述的半導體裝置,其中上述電極為半導體晶片的焊墊。
  3. 如申請專利範圍第2項所述的半導體裝置,其中上述半導體裝置為積層著上述半導體晶片的積層體,上述共用的導線將鄰接層的上述半導體晶片的電極間依次連接。
  4. 如申請專利範圍第1項至第3項中任一項所述的半導體裝置,其中上述接合部為壓扁至上述共用的導線的直徑的1/4~1/2的厚度的扁平形狀,上述環接部包括自上述接合部向斜上方向彎折而延伸的根部,上述根部的厚度為上述共用的導線的直徑的1/2~4/5的厚度。
  5. 如申請專利範圍第2項至第4項中任一項所述的半導體裝置,其中上述電極自上述半導體晶片的表面凹陷, 上述接合部的厚度比上述電極的凹陷深度厚。
  6. 一種半導體裝置的製造方法,藉由共用的導線將3個以上的半導體晶片或基板的電極依次連接,上述半導體裝置的製造方法的特徵在於:交替地重複接合步驟及環接步驟,從而藉由上述共用的導線將3個以上的上述電極依次連接,其中接合步驟是藉由毛細管將上述導線的側面按壓至一電極,而將上述導線的上述側面接合於上述一電極,環接步驟則是在上述接合步驟之後,藉由上述毛細管使上述導線環接至其他電極上為止。
  7. 如申請專利範圍第6項所述的半導體裝置的製造方法,其中上述接合步驟藉由上述毛細管將上述共用的導線壓扁至其直徑的1/4~1/2的厚度而形成扁平形狀,並且進行超音波激振而將上述共用的導線接合於上述各電極。
  8. 如申請專利範圍第6項或第7項所述的半導體裝置的製造方法,其中上述環接步驟包括:第一上升步驟,在上述接合步驟後,使上述毛細管自上述一電極垂直地上升;第一傾斜移動步驟,在上述第一上升步驟之後,使上述毛細管朝向其他電極而向斜下方向移動;第二上升步驟,在上述第一傾斜移動步驟之後,再次使上述毛細管垂直地上升; 反向步驟,在上述第二上升步驟之後,使上述毛細管朝向上述其他電極的相反側而向斜下方向移動;第二傾斜移動步驟,在上述反向步驟之後,使上述毛細管向斜上方向移動至上述一電極正上方為止;第三上升步驟,在上述第二傾斜移動步驟之後,再次使上述毛細管垂直地上升;以及弧狀移動步驟,在上述第三上升步驟之後,使毛細管朝向上述其他電極的正上方呈弧狀地移動。
  9. 如申請專利範圍第8項所述的半導體裝置的製造方法,其中上述反向步驟使毛細管移動至相對於通過上述接合部且與上述電極垂直的線的角度為10°~20°的點為止。
  10. 如申請專利範圍第6項所述的半導體裝置的製造方法,其中上述電極中的至少一個為自半導體晶片的表面凹陷的焊墊,上述接合步驟藉由上述毛細管將上述共用的導線壓扁至比上述焊墊的凹陷深度厚的厚度而形成扁平形狀,並且進行超音波激振而將上述共用的導線接合於上述焊墊。
TW102135774A 2013-04-15 2013-10-03 半導體裝置以及半導體裝置的製造方法 TWI518814B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013084801 2013-04-15

Publications (2)

Publication Number Publication Date
TW201440151A true TW201440151A (zh) 2014-10-16
TWI518814B TWI518814B (zh) 2016-01-21

Family

ID=51731121

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102135774A TWI518814B (zh) 2013-04-15 2013-10-03 半導體裝置以及半導體裝置的製造方法

Country Status (7)

Country Link
US (1) US9379086B2 (zh)
JP (1) JP5714195B2 (zh)
KR (1) KR101643240B1 (zh)
CN (1) CN104885208B (zh)
SG (1) SG11201508291QA (zh)
TW (1) TWI518814B (zh)
WO (1) WO2014171160A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102273570B1 (ko) 2015-04-01 2021-07-07 주식회사 만도 출차 지원 시스템
JP6437668B2 (ja) * 2015-11-05 2018-12-12 株式会社新川 半導体装置およびその製造方法
US10658326B2 (en) * 2016-07-20 2020-05-19 Samsung Electronics Co., Ltd. Bonding wire having a silver alloy core, wire bonding method using the bonding wire, and electrical connection part of semiconductor device using the bonding wire
US10600756B1 (en) * 2017-02-15 2020-03-24 United States Of America, As Represented By The Secretary Of The Navy Wire bonding technique for integrated circuit board connections
KR102413267B1 (ko) * 2019-03-13 2022-06-27 가부시키가이샤 신가와 와이어 불착 검사 시스템, 와이어 불착 검출 장치 및 와이어 불착 검출 방법
KR102548627B1 (ko) 2019-04-09 2023-06-30 가부시끼가이샤가이죠 절연 피복선의 접합 방법, 접속 구조, 절연 피복선의 박리 방법 및 본딩 장치
TWI739379B (zh) * 2019-04-24 2021-09-11 日商新川股份有限公司 半導體裝置、半導體裝置的製造方法、以及打線接合裝置
US11581285B2 (en) * 2019-06-04 2023-02-14 Kulicke And Soffa Industries, Inc. Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine
CN111774752B (zh) * 2020-07-15 2021-10-29 荆州市弘晟光电科技有限公司 一种铜线焊接工艺
JP2022033633A (ja) * 2020-08-17 2022-03-02 キオクシア株式会社 半導体装置
US20220199571A1 (en) * 2020-12-23 2022-06-23 Skyworks Solutions, Inc. Apparatus and methods for tool mark free stitch bonding
WO2022249384A1 (ja) * 2021-05-27 2022-12-01 株式会社新川 半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2814151B2 (ja) * 1991-02-27 1998-10-22 株式会社新川 ワイヤボンデイング方法
DE69739125D1 (de) * 1996-10-01 2009-01-02 Panasonic Corp Kapillare zum Drahtverbinden zur Herstellung von Höckerelektroden
JP3333413B2 (ja) * 1996-12-27 2002-10-15 株式会社新川 ワイヤボンディング方法
JP3455092B2 (ja) * 1997-10-27 2003-10-06 株式会社新川 半導体装置及びワイヤボンディング方法
JP3662461B2 (ja) 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP3474132B2 (ja) * 1999-09-28 2003-12-08 インターナショナル・ビジネス・マシーンズ・コーポレーション ワイヤボンディング方法および装置
JP3573133B2 (ja) 2002-02-19 2004-10-06 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3767512B2 (ja) * 2002-04-25 2006-04-19 株式会社デンソー ワイヤボンディング方法
JP3946730B2 (ja) * 2004-04-26 2007-07-18 株式会社カイジョー ボンディングワイヤのループ形状及びそのループ形状を備えた半導体装置並びにワイヤボンディング方法
US7780064B2 (en) * 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
WO2008057776A1 (en) * 2006-10-27 2008-05-15 Kulicke And Soffa Industries, Inc. Method of controlling the trajectory of a bonding tool during the formation of a wire loop
JP4397408B2 (ja) 2007-09-21 2010-01-13 株式会社新川 半導体装置及びワイヤボンディング方法
JP4361593B1 (ja) * 2008-10-21 2009-11-11 株式会社新川 ワイヤボンディング方法
JP4344002B1 (ja) * 2008-10-27 2009-10-14 株式会社新川 ワイヤボンディング方法

Also Published As

Publication number Publication date
CN104885208A (zh) 2015-09-02
SG11201508291QA (en) 2015-11-27
US9379086B2 (en) 2016-06-28
KR101643240B1 (ko) 2016-07-27
TWI518814B (zh) 2016-01-21
KR20150046161A (ko) 2015-04-29
US20160035695A1 (en) 2016-02-04
WO2014171160A1 (ja) 2014-10-23
JPWO2014171160A1 (ja) 2017-02-16
JP5714195B2 (ja) 2015-05-07
CN104885208B (zh) 2018-02-13

Similar Documents

Publication Publication Date Title
TWI518814B (zh) 半導體裝置以及半導體裝置的製造方法
US7314818B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US6946380B2 (en) Method for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
TWI506710B (zh) 半導體裝置之製造方法
US6921016B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
JP2002280414A (ja) 半導体装置およびその製造方法
US20050242159A1 (en) System and method for low loop wire bonding
JP3762475B2 (ja) ワイヤボンディング方法及び半導体装置
JP4369401B2 (ja) ワイヤボンディング方法
TW202044438A (zh) 針狀線成形方法以及打線接合裝置
TWI816255B (zh) 打線結構、打線結構形成方法以及電子裝置
WO2022249384A1 (ja) 半導体装置の製造方法
JP6973831B2 (ja) ワイヤボンディング装置
JP2007266062A (ja) 半導体装置の製造方法
JP2003086621A (ja) 半導体装置およびその製造方法
TWI818362B (zh) 半導體裝置的製造以及半導體裝置的製造裝置
JP4616924B2 (ja) 半導体装置
JP5048990B2 (ja) 半導体装置及びその製造方法
TW202347535A (zh) 半導體裝置的製造方法
JP2008085094A (ja) 半導体装置の製造方法
JP4558832B2 (ja) 半導体装置
JP2009076767A (ja) 半導体装置の製造方法及びワイヤボンディング装置
JP2009044115A (ja) ワイヤボンディング方法及び半導体装置
JPH10199913A (ja) ワイヤボンディング方法
JPH08153756A (ja) 半導体装置のワイヤボンディング方法及びそのための装置