TW201420331A - 鎳／銦／錫／銅多層結構之製造方法 - Google Patents

鎳／銦／錫／銅多層結構之製造方法 Download PDF

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Publication number
TW201420331A
TW201420331A TW101143180A TW101143180A TW201420331A TW 201420331 A TW201420331 A TW 201420331A TW 101143180 A TW101143180 A TW 101143180A TW 101143180 A TW101143180 A TW 101143180A TW 201420331 A TW201420331 A TW 201420331A
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layer
substrate
nickel
tin
multilayer structure
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TW101143180A
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English (en)
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TWI449620B (zh
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Yee-Wen Yen
Pin-Ju Huang
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Univ Nat Taiwan Science Tech
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Priority to US13/682,707 priority Critical patent/US8956473B2/en
Priority to TW101143180A priority patent/TWI449620B/zh
Publication of TW201420331A publication Critical patent/TW201420331A/zh
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K31/00—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups
    • B23K31/02—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups relating to soldering or welding
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
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    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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    • H01L2924/15747—Copper [Cu] as principal constituent

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  • Electroplating Methods And Accessories (AREA)
  • Wire Bonding (AREA)

Abstract

本發明係與一種鎳/銦/錫/銅多層結構之製造方法有關，其係將鎳/銦/錫/銅之多層結構形成於一第一基板(銅基板)與一第二基板(例如矽晶圓)之間，並進一步地藉由迴焊接合製程與時效熱處理後，形成複數個介金屬層於該鎳/銦/錫/銅多層結構之內，該複數個介金屬層係包括：一第一介金屬層、一第二介金屬層與一第三介金屬層，分別為(Cu,Ni)6(Sn,In)5、(Cu,Ni)6(Sn,In)5與(Ni,Cu)3(Sn,In)4；如此，藉由該些金屬層之形成，係使得鎳/銦/錫/銅之多層結構具有良好之濕潤性、延展性、抗潛變能力與抗疲勞性；此外，該鎳/銦/錫/銅之多層結構可經由低溫接合而製得，故其適合作為傳統高溫含鉛焊料之替代焊料，並應用於三維IC之構裝製程中。

Description

鎳/銦/錫/銅多層結構之製造方法
本發明係與以多層結構作為基板接合之製程方法有關，尤指一種鎳/銦/錫/銅多層結構之製造方法，由該製造方法所製得之鎳/銦/錫/銅多層結構係由具有良好的濕潤性、高延展性、抗潛變能力、以及抗疲勞性，並且係適合作為傳統高溫含鉛焊料之替代焊料，並可應用於三維IC之立體構裝製程中。
隨著時代的演進，人們對電子產品需求也趨於輕薄化，因而使得電子構裝的技術有了進一步的發展。電子產品的基礎是IC，為了使IC內部元件更趨微小化，IC元件的設計上係朝著高腳數和多功能化發展，而覆晶技術為一種取代傳統接合方式的高腳數IC元件的封裝技術；此外，為了在有限的空間內填裝數量龐大的電子元件，構裝技術走向System in Package(SiP)的系統整合階段，因此IC三維立體的構裝方式逐漸成為發展的關鍵。
在半導體元件接合製程中，錫鉛為常用的銲錫，但近年來，由於環保意識高漲，歐盟和美國、日本等先進國家已通過相關法令，禁止含鉛電子產品的生產；因此，產業界遂開始研發其他二元合金焊錫，以取代錫鉛焊錫。請參 閱第一圖，其係為習用之一種具預銲錫結構之半導體封裝基板及其製法，如第一圖所示，習用之具預銲錫結構之半導體封裝基板係包括：一封裝基板3、一有機絕緣保護層33、一導電膜35、以及一焊錫材料38。其中，該封裝基板3之一表面係形成有數個電性連接墊32。該有機絕緣保護層33係形成於該封裝基板3之表面，且，藉由厚度薄化製程，該些電性連接墊32係露出於該有機絕緣保護層33之上表面。該導電膜35係與一阻層依序地形成於該封裝基板3之表面，且該阻層係形成有數個開孔。該導電膜35與該焊錫材料38係經由電鍍製程而沉積於電性連接墊32之表面，且其係透過阻層之該些開孔而露出。
其中，封裝基板3上之電性連接墊32上係藉由電鍍而形成有銲錫材料(銲錫凸塊38)，該銲錫材料可為選自鉛、錫、銀、銅、鉍、銻、鋅、鎳、鋯、鎂、銦、碲以及鎵所構成之組群之元素的混合物所構成之合金。並且，在該電性連接墊32上所電鍍完成之銲錫材料可為一導電柱形式，俾以在後續用以電性導接覆晶式半導體晶片51之電極銲墊52。另外，半導體晶片51之電極銲墊52具有數個金屬凸塊53，其中電極銲墊52為金屬銅，金屬凸塊53則可為銲錫凸塊、金凸塊、銅凸塊或以銲錫帽(Solder Caps)覆蓋之銅柱。
承上述，由於習用之具預銲錫結構之半導體封裝基板 及其製法所使用之接合材料仍以覆錫銅柱為主，故接合介面處僅會形成錫銅之二元合金；並且，由於該錫銅之二元合金具有較差的濕潤性、延展性，且其接合溫度也相當高，故易造成電路板損壞。
因此，有鑑於習用之具預銲錫結構之半導體封裝基板及其製法係仍具有缺點與不足，故本案之發明人係極力地加以研究，終於研發完成之本發明之一種鎳/銦/錫/銅多層結構之製造方法，由該製造方法所製得之鎳/銦/錫/銅多層結構係由具有良好的濕潤性、高延展性、抗潛變能力、以及抗疲勞性，並且係適合作為傳統高溫含鉛焊料之替代焊料，並可應用於三維IC之立體構裝製程中。
本發明之主要目的，在於提供一種鎳/銦/錫/銅多層結構之製造方法，其係將鎳/銦/錫/銅之多層結構形成於一第一基板(銅基板)與一第二基板(例如矽晶圓)之間，並進一步地藉由迴焊接合製程與時效熱處理後，形成複數個介金屬層於該鎳/銦/錫/銅多層結構之內，該複數個介金屬層係包括：一第一介金屬層、一第二介金屬層與一第三介金屬層，分別為(Cu,Ni)6(Sn,In)5、(Cu,Ni)6(Sn,In)5與(Ni,Cu)3(Sn,In)4；如此，藉由該些金屬層之形成，係使得鎳/銦/錫/銅之多層結構具有良好之濕潤性、延展性、抗潛變能力與抗疲勞性，又可達到低溫接合之效果，進而適合作為傳統高溫含鉛焊料之替 代焊料，並應用於三維IC之立體構裝製程中。
因此，為了達成本發明上述之目的，本案之發明人提出一種/銦/錫/銅多層結構之製造方法，其係包括：(1)於一第一基板上依序電鍍一第一鎳層與一銦層；(2)於一第二基板上濺鍍一第二鎳層，並透過微影技術於該第二鎳層上，形成具有一特定圖案的一光阻層；(3)於該第二基板與該光阻層之上，依序電鍍一銅層與一錫層；(4)去除該光阻層以使得複數個銅柱形成於該第二基板上；(5)將上述之該第一基板疊合至該第二基板上，以使得該第一基板表面之銦層與該第二基板上的該些銅柱緊密接觸；(6)對該第一基板或該第二基板施予一荷重後，再於一特定迴焊溫度下進行一特定迴焊時間的一迴焊接合製程；以及(7)將上述迴焊接合步驟之產物進行烘烤，並於一特定熱處理溫度下進行一特定熱處理時間的一時效熱處理，藉以形成包含複數個介金屬層之一多層結構。
為了能夠更清楚地描述本發明所提出之一種鎳/銦/錫/銅多層結構之製造方法，以下將配合圖式，詳盡說明本發 明之實施例。
參閱第二A圖與第二B圖，其等係為本發明之一種鎳/銦/錫/銅多層結構之製造方法的流程圖；並且，請同時參閱第三A圖與第三B圖，其等係為本發明之製程示意圖，其中，本發明之方法主要包括7個步驟流程：首先，如第二A圖與第三A圖所示，該方法係執行步驟(201)，以製備一第一基板11，並依序於該第一基板之表面上電鍍一第一鎳層111與一銦層112；其中，該第一基板11為一銅基板，且該銅基板可能位於矽晶圓(wafer)、電路晶片或電路板之上。接著，該方法係執行步驟(202)，於一第二基板12上濺鍍一第二鎳層122，並透過微影技術於該第二鎳層122上形成具有一特定圖案的一光阻層123；其中，相對於前述之第一基板11，第二基板12可為矽晶圓(wafer)、電路晶片或者電路板。
完成步驟(202)後，該方法係繼續地執行步驟(203)，依序於第二基板12與光阻層123之上電鍍一銅層與一錫層；接著，於步驟(204)中，係以酒精去除具有特定圖案的該光阻層123及形成於光阻層123上的銅層與錫層，如此，如第三A圖所示，即可形成複數個銅柱121於第二基板12之上，且每一個銅柱121之表面係覆有錫層。於此，必須補充說明的是，由於光阻層123具有正光阻特性，因此藉由顯影製程可形成該具有特定圖案的光阻層123於第二基 板12之上；接著，當銅層與錫層被同時電鍍至第二基板12與光阻層123之上後，便可使用酒精去除光阻層123，進而同時去除不需要的銅層與錫層，此種方式即稱為舉離法(lift off)。
繼續地，如第二B圖與第三B圖所示，該方法係繼續地執行步驟(205)，並將步驟(201)所製得的第一基板11疊合至步驟(204)所製得的第二基板12之上，以使得該第一基板11表面之銦層112，與該第二基板12上的該些銅柱121緊密接觸。
接著，該方法係執行步驟(206)，並對第一基板11或該第二基板12施予一荷重後，再於一特定迴焊溫度下進行一特定迴焊時間的一迴焊接合製程。最後，將步驟(206)所得之產物，於一特定熱處理溫度下進行一特定熱處理時間的一時效熱處理後，則可形成包含複數個介金屬層之一鎳/銦/錫/銅多層結構；如第三B圖所示，該鎳/銦/錫/銅多層結構包含一第一介金屬層131、一第二介金屬層132、以及一第三介金屬層133等複數個介金屬層。在完成上述步驟後所製得之多層結構，係如第四圖所示之鎳/銦/錫/銅多層結構之示意圖，該鎳/銦/錫/銅多層結構係由第二基板12、複數個銅柱121、第一介金屬層131、第二介金屬層132、第三介金屬層133與第一基板11所構成。
必須特別說明的是，於上述之鎳/銦/錫/銅多層結構之 製造方法中，步驟(201)係由以下之詳細步驟所達成：使用面積為1 cm2，厚度為1 mm的銅片作為該第一基材11，且以5 ASD(A/dm2)的電流密度於銅基材11的表面電鍍2 μm的第一鎳層111，接著再鍍上6 μm的銦層112。並且，於該步驟(202)中，於第二基板12表面所濺鍍之第二鎳層122，其之厚度為20 nm，且經微影技術所形成之該光阻層123，其之該特定圖案係為面積1 mm×1 mm的正方形。再者，於前述之步驟(203)中，該銅層與該錫層係以5 ASD(A/dm2)的電流密度，而於該第二基板12與該光阻層123之表面進行電鍍，且該銅層與該錫層之電鍍厚度分別為25 μm與5 μm。
並且，如第二B圖與第三B圖所示，前述之步驟(205)係使用一助銲劑，而將步驟(201)所製得的第一基板11疊合至步驟(204)所製得的第二基板12上，以使得第一基板1表面之銦層112，能夠與該第二基板12上的該些銅柱121緊密接觸。另外，步驟(206)中所使用的該迴焊接合製程包括下列兩種：一為在溫度200℃下，歷時10分鐘之迴焊接合製程，另一則為在溫度180℃下，歷時10分鐘之迴焊接合製程。在完成上述任一種迴焊接合製程後，可更進一步地，在溫度100℃下進行時效熱處理20~70小時(步驟(207))，即可製得如第四圖所示之鎳/銦/錫/銅多層結構，其中該鎳/銦/錫/銅多層結構之該複數個介金屬層係包括：一第一介金屬層131、一第二介金屬層132與一第三介金屬 層133，其等係分別為(Cu,Ni)6(Sn,In)5、(Cu,Ni)6(Sn,In)5與(Ni,Cu)3(Sn,In)4。
上述說明係已完整且清楚地說明本發明之一種鎳/銦/錫/銅多層結構之製造方法；接著，為了證明本發明之方法的可行性，以下將藉由呈現各種實驗資料來加以證明。請參閱第五圖，其係為鎳/銦/錫/銅多層結構之背向散射微結構影像圖；其中，第五圖所示之鎳/銦/錫/銅多層結構係以上述之鎳/銦/錫/銅多層結構之製造方法所製得，且其之迴焊溫度為200℃；並且，請相互對照第五圖與第四圖，當接合完成後於該複數個銅柱121與該第一基板11之介面處，可分別發現些許之(Cu,Ni)6(Sn,In)5的生成；進一步地，再經過步驟(207)所述之時效熱處理後，由(Cu,Ni)6(Sn,In)5所組成之第一介金屬層131即形成於複數個銅柱121之介面處，且由(Cu,Ni)6(Sn,In)5所組成之第二介金屬層132係形成第一基板11之介面處；此外，由(Ni,Cu)3(Sn,In)4所組成之第三介金屬層133亦形成於第一基板11之介面處，並且係介於第一基板11之介面與該第二介金屬層132之間。
繼續地，請參閱第六A圖，其係為鎳/銦/錫/銅多層結構之背向散射微結構影像圖；其中，第六A圖所示之鎳/銦/錫/銅多層結構，係藉由以上所述之鎳/銦/錫/銅多層結構之製造方法所製得，且其之迴焊溫度為180℃。如第六A圖所示，當接合完成後其可於複數個銅柱121之介面處，發 現一中間產物Cu6(Sn,In)5的生成。
並且，如第六B圖所示，其係為鎳/銦/錫/銅多層結構之背向散射微結構影像圖；其中，第六B圖所示之鎳/銦/錫/銅多層結構，係以上述之鎳/銦/錫/銅多層結構之製造方法所製得，且其之迴焊溫度係為180℃。進一步地，對第六A圖之鎳/銦/錫/銅多層結構進行步驟(207)所述之時效熱處理後，則該中間產物Cu6(Sn,In)5即轉變為(Cu,Ni)6(Sn,In)5(如第六B圖所示)；並且，由(Cu,Ni)6(Sn,In)5組成之第一介金屬層131即可形成於複數個銅柱121之介面處，而由(Cu,Ni)6(Sn,In)5組成之第二介金屬層132亦即可形成第一基板11之介面處，且由(Ni,Cu)3(Sn,In)4組成之第三介金屬層133亦即形成於第一基板11之介面處，並介於第一基板11之介面與該第二介金屬層132之間。
如此，藉由上述之詳細說明，使得本發明之鎳/銦/錫/銅多層結構之製造方法皆已被完整且清楚地揭露，並且，經由上述，可得知本發明係具有下列之優點：
1.本發明之鎳/銦/錫/銅多層結構之製造方法係將鎳/銦/錫/銅之多層結構形成於一第一基板(銅基板)與一第二基板(例如矽晶圓)之間，並進一步地藉由迴焊接合製程與時效熱處理後，形成產生由(Cu,Ni)6(Sn,In)5與(Cu,Ni)6(Sn,In)5組成之複數個介金屬層，如此，藉由該些金屬層之形成，係使得鎳/銦/錫/銅之多層結構具有良好之濕潤性、延展性、 抗潛變能力與抗疲勞性；此外，該鎳/銦/錫/銅之多層結構可經由低溫接合而製得，故其適合作為傳統高溫含鉛焊料之替代焊料，並應用於三維IC之構裝製程中。
2.承上述，此具有(Cu,Ni)6(Sn,In)5與(Cu,Ni)6(Sn,In)5介金屬層之多層結構係適合用於接合兩基板，原因在於(Cu,Ni)6(Sn,In)5與(Cu,Ni)6(Sn,In)5具有高熔點特性，故可提高兩基板接合強度，並且亦可避免發生傳統含鉛焊料於接合時所產生的橋接現象，因此具有(Cu,Ni)6(Sn,In)5與(Cu,Ni)6(Sn,In)5介金屬層之多層結構係適合應用於作為IC三維立體的構裝接合。
上述之詳細說明係針對本發明可行實施例之具體說明，惟該實施例並非用以限制本發明之專利範圍，凡未脫離本發明技藝精神所為之等效實施或變更，均應包含於本案之專利範圍中。
11‧‧‧第一基板
111‧‧‧第一鎳層
112‧‧‧銦層
12‧‧‧第二基板
121‧‧‧複數個銅柱
122‧‧‧第二鎳層
123‧‧‧光阻層
131‧‧‧第一介金屬層
132‧‧‧第二介金屬層
133‧‧‧第三介金屬層
201~204‧‧‧方法步驟
205~207‧‧‧方法步驟
3‧‧‧封裝基板
32‧‧‧連接墊
33‧‧‧有機絕緣保護層
35‧‧‧導電膜
38‧‧‧焊錫材料
51‧‧‧半導體晶片
52‧‧‧電極銲墊
53‧‧‧金屬凸塊
第一圖係習用之一種具預銲錫結構之半導體封裝基板的製程示意圖；第二A圖與第二B圖係為本發明之一種鎳/銦/錫/銅多層結構之製造方法的流程圖；第三A圖與第三B圖係為該鎳/銦/錫/銅多層結構之製造方法的製程示意圖；第四圖係為鎳/銦/錫/銅多層結構之架構示意圖； 第五圖係為鎳/銦/錫/銅多層結構之背向散射微結構影像圖；以及第六A圖與第六B圖係為鎳/銦/錫/銅多層結構之背向散射微結構影像圖。
201~204‧‧‧方法步驟
205~207‧‧‧方法步驟

Claims (10)

  1. 一種鎳/銦/錫/銅多層結構之製造方法，係包括以下步驟：(1)於一第一基板上依序電鍍一第一鎳層與一銦層；(2)於一第二基板上濺鍍一第二鎳層，並透過微影技術於該第二鎳層上，形成具有一特定圖案的一光阻層；(3)於該第二基板與該光阻層之上，依序電鍍一銅層與一錫層；(4)去除該光阻層以使得複數個銅柱形成於該第二基板上；(5)將上述之該第一基板疊合至該第二基板上，以使得該第一基板表面之銦層與該第二基板上的該些銅柱緊密接觸；(6)對該第一基板或該第二基板施予一荷重後，再於一特定迴焊溫度下進行一特定迴焊時間的一迴焊接合製程；以及(7)將上述步驟(6)之產物進行烘烤，並於一特定熱處理溫度下進行一特定熱處理時間的一時效熱處理，藉以形成包含複數個介金屬層之一多層結構。
  2. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該步驟(1)更包括以下詳細步驟：(11)使用面積為1 cm2，厚度為1 mm的銅片作為該第一基材，以及； (12)以5 ASD(A/dm2)的電流，於該第一基材表面依序電鍍厚度為2 μm的該第一鎳層與6 μm的該銦層。
  3. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，於該步驟(2)中，該第二鎳層之厚度為20 nm。
  4. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中於該第二基板上所形成之該光阻層，其所具有之該特定圖案係為面積為1 mm×1 mm的正方形。
  5. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，於該步驟(3)中，該銅層與該錫層以5 ASD(A/dm2)的電流被電鍍於該第二基板與該光阻之表面上，且該銅層與該錫層之電鍍厚度分別為25 μm與5 μm。
  6. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該步驟(5)係使用一助銲劑將該第一基板疊合至該第二基板上。
  7. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該步驟(6)所述之該特定迴焊溫度為200℃，且該特定迴焊時間為10分鐘。
  8. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該步驟(6)所述之該迴焊接合製程的該特定迴焊溫度為180℃，該特定迴焊時間為10分鐘。
  9. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該步驟(7)所述的該特定熱處理溫度為100℃，且該特定熱處理時間為20~70小時。
  10. 如申請專利範圍第1項所述之鎳/銦/錫/銅多層結構之製造方法，其中，該複數個介金屬層包括：一第一介金屬層，係為(Cu,Ni)6(Sn,In)5、一第二介金屬層係為(Cu,Ni)6(Sn,In)5、以及一第三介金屬層係為(Ni,Cu)3(Sn,In)4。
TW101143180A 2012-11-20 2012-11-20 鎳／銦／錫／銅多層結構之製造方法 TWI449620B (zh)

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