TW201330051A - 晶圓之接合方法及接合部之構造 - Google Patents

晶圓之接合方法及接合部之構造 Download PDF

Info

Publication number
TW201330051A
TW201330051A TW101134103A TW101134103A TW201330051A TW 201330051 A TW201330051 A TW 201330051A TW 101134103 A TW101134103 A TW 101134103A TW 101134103 A TW101134103 A TW 101134103A TW 201330051 A TW201330051 A TW 201330051A
Authority
TW
Taiwan
Prior art keywords
layer
wafer
bonding
joint portion
ausn
Prior art date
Application number
TW101134103A
Other languages
English (en)
Other versions
TWI484532B (zh
Inventor
Takeshi Fujiwara
Toshiaki Okuno
Katsuyuki Inoue
Junya Yamamoto
Kenichi Hinuma
Yoshiki Ashihara
Takaaki Miyaji
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Publication of TW201330051A publication Critical patent/TW201330051A/zh
Application granted granted Critical
Publication of TWI484532B publication Critical patent/TWI484532B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00269Bonding of solid lids or wafers to the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/01Packaging MEMS
    • B81C2203/0172Seals
    • B81C2203/019Seals characterised by the material or arrangement of seals between parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • H01L2224/06182On opposite sides of the body with specially adapted redistribution layers [RDL]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13007Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13173Rhodium [Rh] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13176Ruthenium [Ru] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13178Iridium [Ir] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16057Shape in side view
    • H01L2224/16058Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16501Material at the bonding interface
    • H01L2224/16502Material at the bonding interface comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16505Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H01L2224/16506Material outside the bonding interface, e.g. in the bulk of the bump connector comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325Material
    • H01L2224/32501Material at the bonding interface
    • H01L2224/32502Material at the bonding interface comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325Material
    • H01L2224/32505Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83193Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS

Abstract

[目的]當藉由共晶接合來接合晶圓之接合部時,防止一黏著層因AuSn而變差。[解決方法]在一晶圓1之一表面上形成一黏著層4,以及在該黏著層4上方堆疊一由對於AuSn具有低可濕性之材料所形成之防擴散層7。此外,在該防擴散層7之一表面上形成一接合層8,以便從該防擴散層7之邊緣縮進,藉此在該晶圓1之表面上形成一接合部3。同時,在一晶圓11之下表面上提供一接合部13,以及在該接合部13下方提供一AuSn焊料層19。使該AuSn焊料層19熔化,以及在該第一晶圓1與該第二晶圓11彼此相對之狀況下,藉由AuSn共晶接合以一AuSn焊料22接合該第一接合部與該第二接合部。

Description

晶圓之接合方法及接合部之構造
本發明係有關於一種接合晶圓之方法及一種接合部之結構,以及更特別地,是有關於一種藉由AuSn共晶接合(eutectic bonding)接合兩個晶圓之方法及一種它的接合部之結構。
當接合兩個晶圓之接合部時,在某些情況中使用AuSn共晶接合。該AuSn共晶接合係指一種使用金屬與AuSn之共晶反應的接合方法及使用於先進MEMS封裝及3維堆疊技術之領域中。依據該AuSn共晶接合,使該AuSn熔化成類似焊料,且其具有如下優點:甚至當該接合部之表面像一電鍍層粗糙時,可輕易地實施接合。
因此,當藉由該AuSn共晶接合接合該等晶圓之接合部時,關於一晶圓,在某些情況中提供一由Cr所形成之黏著層做為一與該晶圓接觸之層(最下層)(參考專利文件1)。此黏著層之作用提高該接合部與該晶圓間之黏著性。
然而,當在接合該等接合部時,該熔化AuSn焊料與該黏著層接觸及該AuSn擴散至該黏著層中的時候,該黏著層與該晶圓間之黏著力降低了及該接合部之可靠性減少了。
此外,關於另一種晶圓,在某些情況中,使一穿過該晶圓之貫穿佈線連接至在該晶圓之表面上所提供之該接合部(電 極)(參考專利文件2)。在此情況中,在該晶圓之表面上事先提供該接合部;在該晶圓中形成一介層孔,以便穿過它;藉由一電鍍法在該介層孔中形成該貫穿佈線;以及使該貫穿佈線接合至該接合部。然而,該接合部通常係由相同於在該介層孔中之該貫穿佈線的材料(例如,Al)所形成,以致於當藉由蝕刻該晶圓來形成該介層孔時,或者當藉由電鍍形成該貫穿佈線時,該接合部可能被蝕刻液或電鍍液(通常是酸性溶液)所蝕刻及損害。
[習知技藝文件] [專利文件]
[專利文件1]:日本專利第3303227號
[專利文件2]:日本未審查專利公告第2007-311771號
[本發明之揭露]
有鑑於上述技術問題而產生本發明,以及本發明之一目的提供一種用以接合晶圓之方法及一種接合部之結構,其能防止該接合部因AuSn而變差。此外,本發明之另一目的提供一種接合部之結構,其中當在一介層孔中形成一貫穿佈線時,該結構能防止該接合部被損害。
依據本發明之一種接合晶圓的方法包括下列步驟:藉由將 一由對於AuSn具有低可濕性之材料所形成之防擴散層堆疊於一第一晶圓上方及使一接合層從該防擴散層之邊緣縮進之方式於該防擴散層之一表面上形成該接合層,而於該第一晶圓之一表面上形成一第一接合部;於一第二晶圓之一表面上形成一第二接合部;以及在該第一晶圓與該第二晶圓彼此相對之狀況下,藉由共晶接合一AuSn焊料而接合該第一接合部與該第二接合部。
依據本發明之接合晶圓的方法,該接合層係以從該防擴散層之邊緣縮進的方式設置在由對於AuSn具有低可濕性之材料所形成之該防擴散層的表面上,以致於當藉由該AuSn共晶接合接合該第一接合部時,該熔化AuSn焊料不太可能在該防擴散層之表面上散開,以及防止該AuSn焊料朝該第一晶圓流動。因此,甚至當在該第一晶圓與該防擴散層間提供一很可能因該AuSn之擴散而變差之層時,該層不太可能變差,因為該AuSn沒有向那裡擴散。有一種情況是,在該第一晶圓之表面上形成一含有Cr做為其主要成分之黏著層。這是因為Cr對於該晶圓具有高黏著性,以致於該第一接合部可牢固地黏附至該第一晶圓。在此情況中,當該AuSn擴散至該黏著層中時,該黏著層之黏著性變差了,但是依據本發明,可防止該AuSn擴散至該黏著層中,以致於可防止該黏著層剝落。此外,在該第一接合部下方形成一致動器之情況中,可防止該AuSn焊料超出該防擴散層及黏附至該致動 器。
依據本發明之接合晶圓的方法,藉由交替地堆疊Au與Sn或以一AuSn合金,在該第一接合部及該第二接合部之至少一表面上事先形成一AuSn焊料層,以及藉由該AuSn共晶接合以該熔化AuSn焊料層接合該第一接合部與該第二接合部。因此,因為事先提供該AuSn焊料層,所以當接合該第一接合部及該第二接合部時,沒有必要塗施該AuSn焊料至任一接合部。
此外,較佳的是,該第一接合部之防擴散層係由一包含像Pt、Rh、Pd、Ir、Ru或Os之白金族金屬做為它的主要成分之材料所形成。因為該包含白金族金屬做為它的主要成分之材料對於AuSn具有低的可濕性,所以該熔化AuSn不太可能在該防擴散層之表面上散開。另外,該包含白金族金屬做為它的主要成分之材料可防止該AuSn通過該防擴散層及擴散至該防擴散層之下層。
較佳的是,該第一接合部之接合層係由一包含Au做為它主要成分之材料所形成。這是因為它與AuSn係相容的。
此外,可以在該黏著層與該防擴散層間提供一Au層。該防擴散層具有強的應力及可能剝落,但是藉由在該黏著層與該防擴散層間提供該Au層,可減少該防擴散層之應力及防止該防擴散層剝落。
另外,依據本發明之接合晶圓的方法之一態樣,在於該第 一晶圓之表面上形成該第一接合部的步驟中,藉由堆疊以相同於該第一接合部之順序及材料所形成之層而於該第一晶圓之表面上形成一打開或關閉接觸點。特別是,較佳地提供該打開或關閉接觸點之每一層具有相同於在該第一接合部中之對應層的厚度及從該第一晶圓之表面算起的高度。依據此態樣,可在形成該第一接合部之步驟的同時,製造該打開或關閉接觸點,以致於可減少製造成本。
依據本發明之接合晶圓的方法之另一態樣,一在該第二部分中與該第二晶圓接觸之面係一由具有高化學抗性之材料(例如,選自Ti、TiN、W或白金族材料中之一或多個材料)形成之導電層所構成,在該第二晶圓中之對應於該第二接合部之位置中形成一介層孔,以及在該介層孔中形成一貫穿佈線,以連接至由具有高化學抗性之材料所形成之該導電層。有一種情況是在該第二晶圓上提供有一半導體積體電路或一致動器且該半導體積體電路或該致動器係連接至第二晶圓之第二接合部,或者在一些情況中,在該第一晶圓上提供該致動器或該半導體積體電路且該致動器或該半導體積體電路係經由該第一接合部連接至該第二接合部。在此情況下,該第二接合部係經由在該第二晶圓中所提供之該介層孔中所形成之該貫穿佈線而連接至一在第二晶圓之外表面上所提供之凸塊。甚至在此情況下,依據此態樣,因為在該第二接合部中與該第二晶圓接觸之面係由具有高化學抗性之 材料形成之該導電層所構成,所以該第二接合部不太可能受在該第二晶圓中開出該介層孔時所使用之蝕刻液或在形成該貫穿佈線時所使用之電鍍液損害。
此外,藉由在該第二接合部中提供由選自Al、Cu、Ni、U或複晶矽中之一或多個材料所形成且具有相對大厚度之該導電層,可在該第一晶圓與該第二晶圓間形成一較大空間。
另外,藉由在該第二接合部之一表面上形成一Au層及以一絕緣塗膜覆蓋該第二接合部之表面的外周圍表面及外周圍邊緣,減少該第二接合部之表面的暴露區域,以致於當藉由該AuSn共晶接合連接該第二接合部時,該AuSn不太可能在該第二接合部之表面上散開。
依據本發明之第一接合部的結構,在一晶圓上方堆疊一由對於AuSn具有低可濕性之材料所形成之防擴散層,以一接合層從該防擴散層之邊緣縮進之方式形成該接合層於該防擴散層之一表面上,以及在該晶圓與該防擴散層間形成一會因該AuSn之擴散而變差或容易變差之功能層。依據該接合部之結構,因為在由對於AuSn具有低可濕性之材料所形成之該防擴散層的表面上所提供之該接合層係形成從該防擴散層之邊緣縮進,所以當藉由AuSn共晶接合連接該第一接合部時,一熔化AuSn焊料不太可能在該防擴散層之表面上散開,以及該AuSn焊料不太可能流入容易因該AuSn之擴 散而變差之該功能層。因此,該功能層幾乎沒有變差,因為該AuSn沒有擴散至該功能層中。
較佳的是,該第一接合部之防擴散層係由一包含像Pt、Rh、Pd、Ir、Ru或Os之白金族金屬做為它的主要成分之材料所形成。因為該包含白金族金屬做為它的主要成分之材料對於該AuSn具有低的可濕性,所以該熔化AuSn焊料不太可能在該防擴散層之表面上散開。此外,該包含白金族金屬做為它的主要成分之材料可防止該AuSn通過該防擴散層及擴散至該防擴散層之下層。
該第一接合部之功能層係一在該第一晶圓之一表面上所形成且含有Cr做為它的主要成分之黏著層。因為該Cr對於該晶圓具有高的黏著性,所以可牢固地黏著該第一接合部與該第一晶圓。當該AuSn擴散至該黏著層中時,該黏著層之黏著性變差了,但是依據本發明,可防止該AuSn擴散至該黏著層中。
較佳的是,該第一接合部之接合層係由一含有Au做為它的主要成分之材料所形成。這是因為它與該AuSn係相容的。
依據本發明之接合部的結構之一態樣,藉由堆疊以相同於該第一接合部之順序及材料所構成之層,而於該第一晶圓之表面上形成一打開或關閉接觸點。特別地,較佳的是,該打開或關閉接觸點之每一層具有相同於該第一接合部中之對應層的厚度及從該第一晶圓之表面算起的高度。依據此態 樣,可在相同於該第一接合部之步驟的同時,製造該打開或關閉接觸點,以使製造成本降低。
本發明之第二接合部的結構具有一在一晶圓之一表面上的由具有高化學抗性之材料所形成之第一導電層、一在該第一導電層上所形成且具有相對大厚度之第二導電層及一在該第二導電層上所形成之阻障層。依據該接合部之結構,與該晶圓接觸之表面係由具有高化學抗性之材料形成之該導電層所構成,以致於該接合部不受在該晶圓中開出該介層孔時所使用之蝕刻液或在形成該貫穿佈線時所使用之電鍍液損害。
此外,藉由在以依據本發明之接合晶圓的方法所接合之該對晶圓中形成一電子零件結構體,可製造一電子零件。
另外,在本發明中用以解決問題之手段具有藉由適當地組合上述成分所提供之特性,以及本發明藉由組合上述成分而具有許多變化。
以下,將參考所附圖式來描述本發明之一較佳具體例。然而,本發明並非侷限於下面具體例,以及可以不同方式設計而不脫離本發明之範圍。
(接合部之結構及接合方法)
圖1A及1B係描述依據本發明之一具體例的用以接合晶圓之方法的示意剖面圖。圖1A顯示在接合一第一晶圓與一 第二晶圓前之結構,以及圖1B顯示在已接合該等晶圓後之結構。
如圖1A所示,在一第一晶圓(亦即,一晶圓1)上提供一第一接合部(亦即,一接合部3)。該晶圓1係一矽(Si)晶圓,以及在它的表面上形成一由SiO2或SiN所製成之絕緣層2。此外,在該絕緣層2之上表面上形成一黏著層4,以及在該黏著層4之上表面上形成一Au層6。再者,在該Au層6上依序形成一防擴散層7及一接合層8。因此,該接合部3係由該黏著層4、該Au層6、該防擴散層7及該接合層8所組成。該接合部3可以是塊狀,或者可以拉長成帶狀。
該黏著層4係一藉由濺鍍在該絕緣層2之表面上所形成之Cr薄膜。該Cr黏著層4係提供來確保該接合部3與該絕緣層2間之黏著性,以防止該接合部3剝落。
在該Au層6上所形成之該防擴散層7係由一對於AuSn具有低可濕性之材料(亦即,一包含像鉑Pt、Rh、Pd、Ir、Ru或Os之白金族金屬做為它的主要成分之材料)所形成。該防擴散層7做為一阻障層,以防止AuSn焊料擴散至該Au層6中。
該防擴散層7可因它的強應力而輕易剝落,以致於當它直接形成於該黏著層4之上表面時,該防擴散層7可能剝落。因此,在該接合部3中,藉由將軟性且相對厚之該金層6夾於該黏著層4與該防擴散層7間,可減輕該防擴散層7 之應力及使該防擴散層7黏附至該Au層6。此外,藉由提供具有小電阻之該Au層6,可使用該接合部3做為一佈線。
該接合層8係形成做為一鍍Au膜,以提供與該AuSn焊料之共晶接合。此外,該接合層8之形成係保持在該防擴散層7之邊緣的後面。亦即,在該接合部3為塊狀之情況中,該接合層8之整個周圍從該防擴散層7之外周圍側縮進。此外,在該接合部3為帶狀之情況中,該接合層8在寬度方向上的兩個邊緣保持在該防擴散層7之兩個邊緣的後面。
如圖1A所示,在一第二晶圓(亦即,一晶圓11)之下表面上提供一第二接合部(亦即,一接合部13)。該晶圓11係一矽晶圓,以及在該下表面上形成一由SiO2或SiN所製成之絕緣層12。此外,在該絕緣層12之下表面上形成一高化學抗性之導電層(特別地,保持不受酸類之改變)(亦即,一第一導電層14),在該第一導電層14之下表面上形成一由可輕易變厚之材料所形成之導電層(亦即,一第二導電層15),以及在該第二導電層15之下表面上形成一阻障層16。因此,該接合部13係由該第一導電層14、該第二導電層15及該阻障層16所組成。該接合部13亦可以是塊狀或可以拉長成為帶狀。
該第一導電層14係由一具有高化學抗性之導電材料所形成。該第一導電層14係由Ti、TiN、W或白金族材料所形成。在它們之間,較佳係該第一導電層14使用對做為電鍍 液之硫酸銅具有高抗性及具有與該絕緣層12之高黏著性的Ti,以及它的厚度為500至1000Å。該第二導電層15係由一具有相對大厚度及便於形成一控制電路或一佈線之材料所形成。該第二導電層15只需要能藉由一像電鍍、濺鍍或CVD之薄膜形成法來厚厚地形成。例如,它是由2μm厚之Al、Cu、Ni、W或複晶矽所形成。在它們之間,較佳係使用Al,因為它價格便宜、多方面適用的及具有高的生產量。同時,在傳送一高頻信號至該接合部13之情況中,使用為磁性材料之Ni係比較不佳的。此外,當使用Al時,較佳係添加5%wt之Cu,以防止Al穿刺(spike)。該阻障層16防止Au擴散至該第二導電層l5、防止該第二導電層15之材料(Al)擴散至一Ti/Au層18之Au中及防止佈線材料與接合材料混合。該阻障層16係由具有高阻障特性之400 Å厚的TiN所形成。
以一由SiO2或SiN所構成之絕緣塗膜17覆蓋該接合部13之外周圍表面及下表面之外周圍部分,以及該絕緣塗膜17沒有覆蓋該接合部13之下表面(該阻障層16)的一部分。在此,該絕緣塗膜17之開口寬度小於該阻障層16之寬度。此外,使由一下層Ti及一上層Au所組成之該Ti/Au層18形成於該接合部13之下表面上成具有大於該絕緣塗膜17之開口的面積。該Ti/Au層18之寬度係大於該絕緣塗膜17之開口寬度,但是小於該阻障層16之寬度。以交替地堆疊 一Sn層20與一Au層21之方式,在該Ti/Au層18之下表面上形成一AuSn焊料層19。此外,該AuSn焊料層19可以由AuSn合金所形成。
如圖1A所示,在其上表面上具有該接合部3之該晶圓1與在其下表面上具有該接合部13之該晶圓11係彼此相對,以及在該接合部13之下表面上所提供之該AuSn焊料層19係堆疊在該接合部3之上表面上。在此狀態中,在熔化該AuSn焊料層19之狀況下使該晶圓11以適當壓力壓靠著該晶圓1。結果,如圖1B所示,該Ti/Au層18之Au層和該接合層8(Au層)係與該AuSn焊料層19熔化在一起而變成一AuSn焊料22,以及藉由該共晶接合來接合該接合部13與該接合部3。
因為該接合層8從該防擴散層7之邊緣縮進,以及包含該白金族金屬做為其主要成分之該防擴散層7對於AuSn具有低的之可濕性,所以該熔化AuSn焊料22沒有散開至該防擴散層7之邊緣。因此,該AuSn焊料22沒有流至該接合部3之側面且沒有到達該黏著層4,以致於該AuSn沒有擴散至該黏著層4中。因此,沒有損害該黏著層4之黏著性,因為該AuSn沒有擴散至該黏著層4中。
此外,因為以該絕緣塗膜17覆蓋該阻障層16之下表面的外周圍部分及減少該阻障層16之暴露面積,所以該AuSn焊料22亦不太可能在該接合部13中擴散。
此外,當該第二導電層15具有大的膜厚時,該等晶圓1及11間之空間會是大的。
(本發明之具體例與比較例間之比較)
接下來,將描述藉由在一比較例中之接合晶圓的方法以AuSn共晶接合來接合該等接合部3及13之情況。圖2A顯示在該比較例中接合一第一晶圓與一第二晶圓前之結構,以及圖2B顯示在該比較例中接合一第一晶圓與一第二晶圓後之缺陷。
本發明之具體例與該比較例間之差異在於:在圖1A所示之本發明的具體例中,使該接合層8之寬度比在該接合部3中之該防擴散層7的寬度短,以及該接合層8從該防擴散層7之邊緣縮進時,然而在圖2A所示之比較例中,該接合層8與該防擴散層7之寬度係相同的,以及該接合層8之邊緣與該防擴散層7之邊緣係重疊的。
依據該比較例,該接合層8覆蓋該整個防擴散層7,以致於當熔化該AuSn焊料層19時,該熔化AuSn焊料22可能散開至該防擴散層7之末端及沿著接合部3之側面流下而越過該防擴散層7之末端。因此,當該熔化AuSn焊料22與該黏著層4接觸時,該AuSn擴散至該黏著層4,此阻礙該黏著層4與該晶圓1間之黏著性。結果,依據該比較實例,會減少該等晶圓之接合產物的產量。
另一方面,依據本發明之具體例,因為沒有以該接合層8 覆蓋之該防擴散層7對於AuSn的可濕性係低的,所以該AuSn焊料22沒有散開至該防擴散層7之末端,以及該AuSn不太可能擴散至該黏著層4中。
圖3A係顯示在藉由該比較例中之方法以AuSn接合來接合該等晶圓之情況中的該黏著層4之狀態的紅外線照片。圖3B係顯示在藉由本發明之具體例中的方法以AuSn接合來接合該等晶圓之情況中的該黏著層4之狀態的紅外線照片。圖3A及3B之每一者顯示從下表面側所攝取之該黏著層4與該絕緣層2間之界面。
如該比較例中之圖3A所示,該AuSn擴散至該黏著層4中,以致於該黏著層4變得相當差。特別地,K所示之部分因該擴散而嚴重變差。同時,如本發明之具體例中的圖3B所示,該黏著層4保持在乾淨及平滑的狀態中。
(提供介層孔及貫穿佈線之情況)
圖1B所示之接合結構對於一只在該等晶圓之接合部間提供該AuSn共晶接合的部分(例如,在一將描述於後之靜電式繼電器中之一用以密閉該等晶圓之外周圍部分的接合部)係夠好的。然而,具有在該晶圓11(第二晶圓)之下表面上形成一半導體積體電路及使該半導體積體電路連接至該接合部13之情況。在此情況中,必需在該晶圓11中形成一介層孔,以及使該接合部13經由一在該介層孔中所提供之貫穿佈線連接至一在該晶圓11之上表面上所提供之凸塊。此 外,具有在該晶圓1(第一晶圓)上提供一致動器(actuator)及使該致動器之一電極經由該導電接合部3電連接至該接合部13之情況。同樣地,在此情況中,必需在該晶圓11中形成該介層孔,以及使該接合部13經由在該介層孔中所提供之該貫穿佈線連接至在該晶圓11之上表面上所提供之該凸塊。
因此,在在該晶圓中必須提供該介層孔及該貫穿佈線之情況中,在接合該等晶圓1及11後,將如圖4A至6B所示處理該晶圓11。
圖4A至6B顯示在依據本發明之一具體例接合該等晶圓1及11後,在該晶圓11中提供一介層孔32及一貫穿佈線33之步驟。以下,將參考圖4A至6B來描述這些步驟。
首先,如圖4A所示,在該晶圓11之上表面上形成一由SiO2或SiN所製成之絕緣層31,以及在該晶圓11中且正好在該接合部13上方形成該介層孔32,以致於使該絕緣層12暴露於該介層孔32之底面。
然後,如圖4B所示,藉由在該晶圓11之整個表面上使SiO2或SiN蒸發,以在該介層孔32之內面上形成該絕緣層31,以及使該晶圓11之上表面上的絕緣層31變厚。
接著,如圖5A所示,藉由蝕刻移除在該介層孔32之底面上之絕緣層31及絕緣層12,以及使該第一導電層14暴露於該介層孔32之底面。
然後,如圖5B所示,藉由在該介層孔32之底面及內周面至該絕緣層31之上表面間之表面上電鍍一像Cu或Al之導電材料,形成該貫穿佈線33,以及接著,如圖6A所示,藉由蝕刻使該貫穿佈線33成為一預定圖案。該第一導電層14係由具有高化學抗性之Ti、TiN或W所形成,以致於當形成該介層孔32,以及藉由電鍍形成該貫穿佈線33時,以該第一導電層14阻止蝕刻液及電鍍液,以及保護該接合部13不受蝕刻液及電鍍液之影響。
接著,如圖6B所示,以一由聚醯亞胺所形成之保護膜34覆蓋該晶圓11之上表面,使該保護膜34之部分成為開口,以暴露該貫穿佈線33,以及在該貫穿佈線33之暴露部分上形成一凸塊35。
(靜電式繼電器之情況)
將描述一靜電式繼電器41(電子零件)做為該等晶圓之接合體的一特定實例。圖7係該靜電式繼電器之示意剖面圖。
已藉由MEMS技術在該晶圓1上製造該靜電式繼電器41。該靜電式繼電器41係由配置成彼此相對之一固定接觸部46及一可移動接觸部45(每一者充當一打開或關閉接點)以及一藉由靜電力轉移該可移動接觸部45之靜電致動器42所組成。該靜電致動器42係由在該晶圓1之一部分中所製造之一固定部43及一可移動部44所組成。該可移動部44亦具有一處於複數列之梳狀齒形結構,以及在與該晶圓1 分離之狀態中被支撐,以致於可使它水平地前後移動。該固定部分43之梳狀齒形結構與該可移動部44之梳狀齒形結構彼此嚙合而沒有接觸。因此,當在該等梳狀齒形結構間施加一電壓時,朝該固定部43拉動該可移動部44及藉由在該固定部43之梳狀齒形結構與該可移動部44之梳狀齒形結構間所產生之靜電力水平地移動該可移動部44。
在該等晶圓1及11之外周圍邊緣的每一者中放置一接合部47,以及該接合部47密閉該等晶圓1及11間之空間。藉由共晶接合以該AuSn焊料22接合該接合部3與該接合部13,以提供該接合部47。
一接合部48係一使該靜電致動器42電連接至該貫穿佈線33及該凸塊35之部分。亦藉由該共晶接合以該AuSn焊料22接合該接合部3與該接合部13,以提供該接合部48。
該可移動接觸部45係設置在該靜電致動器42之可移動部44的上表面上。該固定接觸部46係設置在該晶圓1之上表面上,以便相對於該可移動接觸部45。該可移動接觸部45及該固定接觸部46不是該等接合部,但是它們與該接合部3係同時形成的,以及具有相同於該接合部3之層狀結構。亦即,該可移動接觸部45及該固定接觸部46之每一者係藉由依序堆疊該黏著層4、該Au層6、該防擴散層7及該接合層8所構成,以及每一層具有相同於該接合部3中之對應層的厚度及從該晶圓1之表面算起的高度。因此,一包 含該白金族金屬做為它的主要成分之層(對應於該防擴散層7)充當一固定接觸點45a及一可移動接觸點46a。此外,一由Au所形成之層(對應於該Au層6)係一平行於該晶圓1之上表面行進且連接至該固定接觸點45a或該可移動接觸點46a之佈線部。
此外,藉由增加在該接合部13中之由Al所形成之該第二導電層15的厚度,可增加該等晶圓1及11間之空間的高度,以致於當水平地移動該可移動接觸部45時,可防止該可移動接觸部45妨礙該晶圓11。
另外,因為該接合層8之寬度小於該防擴散層7之寬度,以及該AuSn焊料不太可能流至該接合部3之下部分,所以可防止該可移動部44黏著,因為該AuSn焊料沒有流至該可移動部44。
此外,在該晶圓11之下表面上提供一用以處理從該靜電式繼電器41輸出之偵測信號的處理電路。
1‧‧‧晶圓
2‧‧‧絕緣層
3‧‧‧接合部
4‧‧‧黏著層
6‧‧‧Au層
7‧‧‧防擴散層
8‧‧‧接合層
11‧‧‧晶圓
12‧‧‧絕緣層
13‧‧‧接合部
14‧‧‧第一導電層
15‧‧‧第二導電層
16‧‧‧阻障層
17‧‧‧絕緣塗膜
18‧‧‧Ti/Au層
19‧‧‧AuSn焊料層
20‧‧‧Sn層
21‧‧‧Au層
22‧‧‧AuSn焊料
31‧‧‧絕緣層
32‧‧‧介層孔
33‧‧‧貫穿佈線
34‧‧‧保護膜
35‧‧‧凸塊
41‧‧‧靜電式繼電器
42‧‧‧靜電致動器
43‧‧‧固定部
44‧‧‧可移動部
45‧‧‧可移動接觸部
45a‧‧‧固定接觸點
46‧‧‧固定接觸部
46a‧‧‧可移動接觸點
47‧‧‧接合部
48‧‧‧接合部
圖1A及1B係描述依據本發明之一具體例的一種接合晶圓之方法的示意剖面圖。
圖2A及2B係描述依據一比較實例之一種接合晶圓的方法之示意剖面圖。
圖3A係顯示在該比較例中接合該等晶圓後之一黏著層的狀態之紅外線照片。圖3B係顯示在本發明之具體例中接合 該等晶圓後之一黏著層的狀態之紅外線照片。
圖4A及4B係描述在使該等晶圓彼此接合後在一第二晶圓中形成一貫穿佈線之步驟的示意剖面圖。
圖5A及5B係描述在圖4B所示之步驟後的在使該等晶圓彼此接合後在該第二晶圓中形成該貫穿佈線之步驟的示意剖面圖。
圖6A及6B係描述在圖5B所示之步驟後的在使該等晶圓彼此接合後在該第二晶圓中形成該貫穿佈線之步驟的示意剖面圖。
圖7係一藉由依據本發明之接合晶圓的方法所製造之靜電式繼電器的示意剖面圖。
1‧‧‧晶圓
3‧‧‧接合部
2‧‧‧絕緣層
6‧‧‧Au層
4‧‧‧黏著層
8‧‧‧接合層
7‧‧‧防擴散層
12‧‧‧絕緣層
11‧‧‧晶圓
14‧‧‧第一導電層
13‧‧‧接合部
16‧‧‧阻障層
15‧‧‧第二導電層
18‧‧‧Ti/Au層
17‧‧‧絕緣塗膜
20‧‧‧Sn層
19‧‧‧AuSn焊料層
21‧‧‧Au層

Claims (21)

  1. 一種晶圓之接合方法,包括下列步驟:藉由將一由對於AuSn具有低可濕性之材料所形成之防擴散層堆疊於一第一晶圓上方及使一接合層從該防擴散層之邊緣縮進之方式於該防擴散層之一表面上形成該接合層,而於該第一晶圓之一表面上形成一第一接合部;於一第二晶圓之一表面上形成一第二接合部;以及在該第一晶圓與該第二晶圓彼此相對之狀況下,藉由共晶接合一AuSn焊料而接合該第一接合部與該第二接合部。
  2. 如申請專利範圍第1項之晶圓之接合方法,其中,該第一接合部之防擴散層係由一含有像Pt、Rh、Pd、Ir、Ru或Os之白金族金屬做為其主要成分之材料所形成。
  3. 如申請專利範圍第1項之晶圓之接合方法,其中,該第一接合部之接合層係由一含有Au做為其主要成分之材料所形成。
  4. 如申請專利範圍第1項之晶圓之接合方法,其中,在該第一晶圓之表面上形成一含有Cr做為其主要成分之黏著層。
  5. 如申請專利範圍第4項之晶圓之接合方法,其中,在該黏著層與該防擴散層間形成一Au層。
  6. 如申請專利範圍第1項之晶圓之接合方法,其中,藉由交替地堆疊Au與Sn或以一AuSn合金,在該第一接 合部及該第二接合部之至少一表面上事先形成一AuSn焊料層,以及藉由AuSn共晶接合熔化之AuSn焊料層而接合該第一接合部與該第二接合部。
  7. 如申請專利範圍第1項之晶圓之接合方法,其中,在於該第一晶圓之表面上形成該第一接合部的步驟中,藉由堆疊以相同於該第一接合部之順序及材料所形成之層,而於該第一晶圓之表面上形成一打開或關閉接觸點。
  8. 如申請專利範圍第7項之晶圓之接合方法,其中,該打開或關閉接觸點之每一層具有相同於在該第一接合部中之對應層的厚度及從該第一晶圓之表面算起的高度。
  9. 如申請專利範圍第1項之晶圓之接合方法,其中,一在該第二接合部中與該第二晶圓接觸之面包括一由具有高化學抗性之材料所形成之導電層,在該第二晶圓中之對應於該第二接合部之位置中形成一介層孔,以及在該介層孔中形成一貫穿佈線,以連接至由具有高化學抗性之材料所形成之該導電層。
  10. 如申請專利範圍第1項之晶圓之接合方法,其中,該第二接合部具有一有相對大厚度之導電層。
  11. 如申請專利範圍第1項之晶圓之接合方法,其中,該第二接合部之一表面包括一Au層,以及以一絕緣塗膜覆蓋該第二接合部之表面的外周圍表面及外周圍邊緣。
  12. 如申請專利範圍第9項之晶圓之接合方法,其中,該具有高化學抗性之材料係選自Ti、TiN、W或白金族材料中之一或多個材料。
  13. 如申請專利範圍第10項之晶圓之接合方法,其中,該具有相對大厚度之導電層係由選自Al、Cu、Ni、W或複晶矽中之一或多個材料所形成。
  14. 一種接合部之構造,包括:一防擴散層,其由對於AuSn具有低可濕性之材料所形成,該防擴散層係堆疊在一晶圓上方,一接合層,其以該接合層從該防擴散層之邊緣縮進之方式形成於該防擴散層之一表面上;以及一會因對AuSn之擴散而變差之功能層,其形成於該晶圓與該防擴散層之間。
  15. 如申請專利範圍第14項之接合部之構造,其中,該第一接合部之防擴散層係由一含有像Pt、Rh、Pd、Ir、Ru或Os之白金族金屬做為它的主要成分之材料所形成。
  16. 如申請專利範圍第14項之接合部之構造,其中,該第一接合部之功能層係一在該第一晶圓之一表面上所形成且含有Cr做為它的主要成分之黏著層。
  17. 如申請專利範圍第14項之接合部之構造,其中,該第一接合部之接合層係由一含有Au做為它的主要成分之材料所形成。
  18. 如申請專利範圍第14項之接合部之構造,其中,藉由堆疊以相同於該第一接合部之順序及材料所構成之層,而於該第一晶圓之表面上,形成一打開或關閉接觸點。
  19. 如申請專利範圍第14項之接合部之構造,其中,該打開或關閉接觸點之每一層具有相同於在該第一接合部中之對應層的厚度及從該第一晶圓之表面算起的高度。
  20. 一種接合部之構造,具有:一第一導電層,其在一晶圓之一表面上由具有高化學抗性之材料所形成;一第二導電層,其形成於該第一導電層上且具有相對大厚度;以及一阻障層,其形成於該第二導電層上。
  21. 一種電子零件,其包括在藉由申請專利範圍第1項之晶圓之接合方法所接合之一對晶圓中所形成之一電子零件構造體。
TW101134103A 2011-10-06 2012-09-18 晶圓之接合方法及接合部之構造 TWI484532B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011222284A JP5716627B2 (ja) 2011-10-06 2011-10-06 ウエハの接合方法及び接合部の構造

Publications (2)

Publication Number Publication Date
TW201330051A true TW201330051A (zh) 2013-07-16
TWI484532B TWI484532B (zh) 2015-05-11

Family

ID=48043623

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101134103A TWI484532B (zh) 2011-10-06 2012-09-18 晶圓之接合方法及接合部之構造

Country Status (5)

Country Link
US (1) US9136232B2 (zh)
JP (1) JP5716627B2 (zh)
DE (1) DE112012004162B4 (zh)
TW (1) TWI484532B (zh)
WO (1) WO2013051463A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107848789A (zh) * 2015-09-17 2018-03-27 株式会社村田制作所 Mems设备及其制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508663B2 (en) * 2013-07-24 2016-11-29 Invensense, Inc. Assembly and packaging of MEMS device
WO2015046326A1 (ja) * 2013-09-26 2015-04-02 デクセリアルズ株式会社 発光装置、異方性導電接着剤、発光装置製造方法
JP6546376B2 (ja) * 2014-08-07 2019-07-17 浜松ホトニクス株式会社 電子部品
JP6891203B2 (ja) * 2014-08-11 2021-06-18 レイセオン カンパニー 応力低減レイヤを有する密封されたパッケージ
JP6891202B2 (ja) * 2014-08-11 2021-06-18 レイセオン カンパニー 応力低減レイヤを有する密封されたパッケージ
JP6487032B2 (ja) * 2014-08-11 2019-03-20 レイセオン カンパニー 応力低減レイヤを有する密封されたパッケージ
US11018099B2 (en) * 2014-11-26 2021-05-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having a conductive bump with a plurality of bump segments
EP3064166B1 (de) 2015-03-06 2018-07-04 Schott AG Hermetisch abgedichtete led-leuchte sowie verfahren zur herstellung einer hermetisch abgedichteten led-leuchte
CN106373900A (zh) * 2015-07-20 2017-02-01 中芯国际集成电路制造(北京)有限公司 晶圆级键合封装方法以及共晶键合的晶圆结构
DE112017007356T5 (de) * 2017-03-29 2019-12-12 Mitsubishi Electric Corporation Hohle versiegelte Vorrichtung und Herstellungsverfahren dafür
WO2023242185A1 (en) * 2022-06-14 2023-12-21 Ams-Osram International Gmbh Method for producing a semiconductor device and semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3303227B2 (ja) 1996-06-13 2002-07-15 日本航空電子工業株式会社 AuSn多層ハンダ
JP2000288770A (ja) * 1999-03-31 2000-10-17 Kyocera Corp AuSn多層ハンダ
JP3718380B2 (ja) * 1999-08-18 2005-11-24 株式会社日立製作所 はんだ接続構造を有する回路装置およびその製造方法
JP3994980B2 (ja) * 2004-03-29 2007-10-24 株式会社日立製作所 素子搭載用基板及びその製造方法並びに半導体素子実装方法
JP2007311771A (ja) 2006-04-21 2007-11-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5273073B2 (ja) * 2010-03-15 2013-08-28 オムロン株式会社 電極構造及び当該電極構造を備えたマイクロデバイス用パッケージ
US8962358B2 (en) * 2011-03-17 2015-02-24 Tsmc Solid State Lighting Ltd. Double substrate multi-junction light emitting diode array structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107848789A (zh) * 2015-09-17 2018-03-27 株式会社村田制作所 Mems设备及其制造方法
CN107848789B (zh) * 2015-09-17 2020-10-27 株式会社村田制作所 Mems设备及其制造方法

Also Published As

Publication number Publication date
TWI484532B (zh) 2015-05-11
DE112012004162T5 (de) 2014-07-10
JP2013084689A (ja) 2013-05-09
WO2013051463A1 (ja) 2013-04-11
US20140339710A1 (en) 2014-11-20
JP5716627B2 (ja) 2015-05-13
DE112012004162B4 (de) 2017-12-21
US9136232B2 (en) 2015-09-15

Similar Documents

Publication Publication Date Title
TWI484532B (zh) 晶圓之接合方法及接合部之構造
TW511200B (en) Semiconductor device and manufacturing method thereof
US6927493B2 (en) Sealing and protecting integrated circuit bonding pads
TWI720233B (zh) 半導體裝置及其製造方法
US20080081398A1 (en) Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same
US20100164105A1 (en) Semiconductor device and method of manufacturing the same
CN106206505B (zh) 半导体装置以及半导体装置的制造方法
US20100013008A1 (en) Semiconductor device and method of manufacturing the same
TWI594369B (zh) 與互補式金屬氧化物半導體相容的晶圓接合層及製程
KR102478381B1 (ko) 반도체 패키지
JP6277693B2 (ja) 半導体装置
US20110221056A1 (en) Electrode structure and microdevice package provided therewith
CN206639796U (zh) 半导体器件
JP6380946B2 (ja) 半導体装置および半導体装置の製造方法
WO2006070808A1 (ja) 半導体チップおよびその製造方法、半導体チップの電極構造およびその形成方法、ならびに半導体装置
US20080099919A1 (en) Semiconductor device including copper interconnect and method for manufacturing the same
CN103367243B (zh) 通过氧化形成浅通孔
US10184911B2 (en) Method for manufacturing humidity sensor
JP5273920B2 (ja) 半導体装置
US10418301B2 (en) Power device
JP2013128145A (ja) 半導体装置
JP5273921B2 (ja) 半導体装置およびその製造方法
KR101375707B1 (ko) 구리 본딩 패드 구조 및 방법
JP2005294678A (ja) 半導体装置およびその製造方法
JP2016139711A (ja) 半導体装置およびその製造方法